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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/kernel/r4k_fpu.S
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/kernel/r4k_fpu.S')
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diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
7 *
8 * Multi-arch abstraction and asm macros for easier reading:
9 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
10 *
11 * Carsten Langgaard, carstenl@mips.com
12 * Copyright (C) 2000 MIPS Technologies, Inc.
13 * Copyright (C) 1999, 2001 Silicon Graphics, Inc.
14 */
15#include <linux/config.h>
16#include <asm/asm.h>
17#include <asm/errno.h>
18#include <asm/fpregdef.h>
19#include <asm/mipsregs.h>
20#include <asm/offset.h>
21#include <asm/regdef.h>
22
23 .macro EX insn, reg, src
24 .set push
25 .set nomacro
26.ex\@: \insn \reg, \src
27 .set pop
28 .section __ex_table,"a"
29 PTR .ex\@, fault
30 .previous
31 .endm
32
33 .set noreorder
34 .set mips3
35 /* Save floating point context */
36LEAF(_save_fp_context)
37 cfc1 t1, fcr31
38
39#ifdef CONFIG_MIPS64
40 /* Store the 16 odd double precision registers */
41 EX sdc1 $f1, SC_FPREGS+8(a0)
42 EX sdc1 $f3, SC_FPREGS+24(a0)
43 EX sdc1 $f5, SC_FPREGS+40(a0)
44 EX sdc1 $f7, SC_FPREGS+56(a0)
45 EX sdc1 $f9, SC_FPREGS+72(a0)
46 EX sdc1 $f11, SC_FPREGS+88(a0)
47 EX sdc1 $f13, SC_FPREGS+104(a0)
48 EX sdc1 $f15, SC_FPREGS+120(a0)
49 EX sdc1 $f17, SC_FPREGS+136(a0)
50 EX sdc1 $f19, SC_FPREGS+152(a0)
51 EX sdc1 $f21, SC_FPREGS+168(a0)
52 EX sdc1 $f23, SC_FPREGS+184(a0)
53 EX sdc1 $f25, SC_FPREGS+200(a0)
54 EX sdc1 $f27, SC_FPREGS+216(a0)
55 EX sdc1 $f29, SC_FPREGS+232(a0)
56 EX sdc1 $f31, SC_FPREGS+248(a0)
57#endif
58
59 /* Store the 16 even double precision registers */
60 EX sdc1 $f0, SC_FPREGS+0(a0)
61 EX sdc1 $f2, SC_FPREGS+16(a0)
62 EX sdc1 $f4, SC_FPREGS+32(a0)
63 EX sdc1 $f6, SC_FPREGS+48(a0)
64 EX sdc1 $f8, SC_FPREGS+64(a0)
65 EX sdc1 $f10, SC_FPREGS+80(a0)
66 EX sdc1 $f12, SC_FPREGS+96(a0)
67 EX sdc1 $f14, SC_FPREGS+112(a0)
68 EX sdc1 $f16, SC_FPREGS+128(a0)
69 EX sdc1 $f18, SC_FPREGS+144(a0)
70 EX sdc1 $f20, SC_FPREGS+160(a0)
71 EX sdc1 $f22, SC_FPREGS+176(a0)
72 EX sdc1 $f24, SC_FPREGS+192(a0)
73 EX sdc1 $f26, SC_FPREGS+208(a0)
74 EX sdc1 $f28, SC_FPREGS+224(a0)
75 EX sdc1 $f30, SC_FPREGS+240(a0)
76 EX sw t1, SC_FPC_CSR(a0)
77 cfc1 t0, $0 # implementation/version
78 EX sw t0, SC_FPC_EIR(a0)
79
80 jr ra
81 li v0, 0 # success
82 END(_save_fp_context)
83
84#ifdef CONFIG_MIPS32_COMPAT
85 /* Save 32-bit process floating point context */
86LEAF(_save_fp_context32)
87 cfc1 t1, fcr31
88
89 EX sdc1 $f0, SC32_FPREGS+0(a0)
90 EX sdc1 $f2, SC32_FPREGS+16(a0)
91 EX sdc1 $f4, SC32_FPREGS+32(a0)
92 EX sdc1 $f6, SC32_FPREGS+48(a0)
93 EX sdc1 $f8, SC32_FPREGS+64(a0)
94 EX sdc1 $f10, SC32_FPREGS+80(a0)
95 EX sdc1 $f12, SC32_FPREGS+96(a0)
96 EX sdc1 $f14, SC32_FPREGS+112(a0)
97 EX sdc1 $f16, SC32_FPREGS+128(a0)
98 EX sdc1 $f18, SC32_FPREGS+144(a0)
99 EX sdc1 $f20, SC32_FPREGS+160(a0)
100 EX sdc1 $f22, SC32_FPREGS+176(a0)
101 EX sdc1 $f24, SC32_FPREGS+192(a0)
102 EX sdc1 $f26, SC32_FPREGS+208(a0)
103 EX sdc1 $f28, SC32_FPREGS+224(a0)
104 EX sdc1 $f30, SC32_FPREGS+240(a0)
105 EX sw t1, SC32_FPC_CSR(a0)
106 cfc1 t0, $0 # implementation/version
107 EX sw t0, SC32_FPC_EIR(a0)
108
109 jr ra
110 li v0, 0 # success
111 END(_save_fp_context32)
112#endif
113
114/*
115 * Restore FPU state:
116 * - fp gp registers
117 * - cp1 status/control register
118 */
119LEAF(_restore_fp_context)
120 EX lw t0, SC_FPC_CSR(a0)
121#ifdef CONFIG_MIPS64
122 EX ldc1 $f1, SC_FPREGS+8(a0)
123 EX ldc1 $f3, SC_FPREGS+24(a0)
124 EX ldc1 $f5, SC_FPREGS+40(a0)
125 EX ldc1 $f7, SC_FPREGS+56(a0)
126 EX ldc1 $f9, SC_FPREGS+72(a0)
127 EX ldc1 $f11, SC_FPREGS+88(a0)
128 EX ldc1 $f13, SC_FPREGS+104(a0)
129 EX ldc1 $f15, SC_FPREGS+120(a0)
130 EX ldc1 $f17, SC_FPREGS+136(a0)
131 EX ldc1 $f19, SC_FPREGS+152(a0)
132 EX ldc1 $f21, SC_FPREGS+168(a0)
133 EX ldc1 $f23, SC_FPREGS+184(a0)
134 EX ldc1 $f25, SC_FPREGS+200(a0)
135 EX ldc1 $f27, SC_FPREGS+216(a0)
136 EX ldc1 $f29, SC_FPREGS+232(a0)
137 EX ldc1 $f31, SC_FPREGS+248(a0)
138#endif
139 EX ldc1 $f0, SC_FPREGS+0(a0)
140 EX ldc1 $f2, SC_FPREGS+16(a0)
141 EX ldc1 $f4, SC_FPREGS+32(a0)
142 EX ldc1 $f6, SC_FPREGS+48(a0)
143 EX ldc1 $f8, SC_FPREGS+64(a0)
144 EX ldc1 $f10, SC_FPREGS+80(a0)
145 EX ldc1 $f12, SC_FPREGS+96(a0)
146 EX ldc1 $f14, SC_FPREGS+112(a0)
147 EX ldc1 $f16, SC_FPREGS+128(a0)
148 EX ldc1 $f18, SC_FPREGS+144(a0)
149 EX ldc1 $f20, SC_FPREGS+160(a0)
150 EX ldc1 $f22, SC_FPREGS+176(a0)
151 EX ldc1 $f24, SC_FPREGS+192(a0)
152 EX ldc1 $f26, SC_FPREGS+208(a0)
153 EX ldc1 $f28, SC_FPREGS+224(a0)
154 EX ldc1 $f30, SC_FPREGS+240(a0)
155 ctc1 t0, fcr31
156 jr ra
157 li v0, 0 # success
158 END(_restore_fp_context)
159
160#ifdef CONFIG_MIPS32_COMPAT
161LEAF(_restore_fp_context32)
162 /* Restore an o32 sigcontext. */
163 EX lw t0, SC32_FPC_CSR(a0)
164 EX ldc1 $f0, SC32_FPREGS+0(a0)
165 EX ldc1 $f2, SC32_FPREGS+16(a0)
166 EX ldc1 $f4, SC32_FPREGS+32(a0)
167 EX ldc1 $f6, SC32_FPREGS+48(a0)
168 EX ldc1 $f8, SC32_FPREGS+64(a0)
169 EX ldc1 $f10, SC32_FPREGS+80(a0)
170 EX ldc1 $f12, SC32_FPREGS+96(a0)
171 EX ldc1 $f14, SC32_FPREGS+112(a0)
172 EX ldc1 $f16, SC32_FPREGS+128(a0)
173 EX ldc1 $f18, SC32_FPREGS+144(a0)
174 EX ldc1 $f20, SC32_FPREGS+160(a0)
175 EX ldc1 $f22, SC32_FPREGS+176(a0)
176 EX ldc1 $f24, SC32_FPREGS+192(a0)
177 EX ldc1 $f26, SC32_FPREGS+208(a0)
178 EX ldc1 $f28, SC32_FPREGS+224(a0)
179 EX ldc1 $f30, SC32_FPREGS+240(a0)
180 ctc1 t0, fcr31
181 jr ra
182 li v0, 0 # success
183 END(_restore_fp_context32)
184 .set reorder
185#endif
186
187 .type fault@function
188 .ent fault
189fault: li v0, -EFAULT # failure
190 jr ra
191 .end fault
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 00:09:41 -0500