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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 22:07:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-19 22:07:12 -0400
commit25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (patch)
treee0977d906193eadeafebc442775491b844be79d5 /arch/mips/kernel/ptrace32.c
parent4c84a39c8adba6bf2f829b217e78bfd61478191a (diff)
parent1723b4a34af85447684c9696af83929d2c1e8e6b (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits) [MIPS] Make timer interrupt frequency configurable from kconfig. [MIPS] Correct HAL2 Kconfig description [MIPS] Fix R4K cache macro names [MIPS] Add Missing R4K Cache Macros to IP27 & IP32 [MIPS] Support for the RM9000-based Basler eXcite smart camera platform. [MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board [MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors. [MIPS] SN: include asm/sn/types.h for nasid_t. [MIPS] Random fixes for sb1250 [MIPS] Fix bcm1480 compile [MIPS] Remove support for NEC DDB5476. [MIPS] Remove support for NEC DDB5074. [MIPS] Cleanup memory managment initialization. [MIPS] SN: Declare bridge_pci_ops. [MIPS] Remove unused function alloc_pci_controller. [MIPS] IP27: Extract pci_ops into separate file. [MIPS] IP27: Use symbolic constants instead of magic numbers. [MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig. [MIPS] IP27: Cleanup N/M mode configuration. [MIPS] IP27: Throw away old unused hacks. ...
Diffstat (limited to 'arch/mips/kernel/ptrace32.c')
-rw-r--r--arch/mips/kernel/ptrace32.c16
1 files changed, 5 insertions, 11 deletions
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 8704dc0496ea..f40ecd8be05f 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -166,10 +166,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
166 tmp = regs->lo; 166 tmp = regs->lo;
167 break; 167 break;
168 case FPC_CSR: 168 case FPC_CSR:
169 if (cpu_has_fpu) 169 tmp = child->thread.fpu.fcr31;
170 tmp = child->thread.fpu.hard.fcr31;
171 else
172 tmp = child->thread.fpu.soft.fcr31;
173 break; 170 break;
174 case FPC_EIR: { /* implementation / version register */ 171 case FPC_EIR: { /* implementation / version register */
175 unsigned int flags; 172 unsigned int flags;
@@ -288,9 +285,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
288 285
289 if (!tsk_used_math(child)) { 286 if (!tsk_used_math(child)) {
290 /* FP not yet used */ 287 /* FP not yet used */
291 memset(&child->thread.fpu.hard, ~0, 288 memset(&child->thread.fpu, ~0,
292 sizeof(child->thread.fpu.hard)); 289 sizeof(child->thread.fpu));
293 child->thread.fpu.hard.fcr31 = 0; 290 child->thread.fpu.fcr31 = 0;
294 } 291 }
295 /* 292 /*
296 * The odd registers are actually the high order bits 293 * The odd registers are actually the high order bits
@@ -318,10 +315,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
318 regs->lo = data; 315 regs->lo = data;
319 break; 316 break;
320 case FPC_CSR: 317 case FPC_CSR:
321 if (cpu_has_fpu) 318 child->thread.fpu.fcr31 = data;
322 child->thread.fpu.hard.fcr31 = data;
323 else
324 child->thread.fpu.soft.fcr31 = data;
325 break; 319 break;
326 case DSP_BASE ... DSP_BASE + 5: { 320 case DSP_BASE ... DSP_BASE + 5: {
327 dspreg_t *dregs; 321 dspreg_t *dregs;