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authorGabor Juhos <juhosg@openwrt.org>2013-01-31 07:20:43 -0500
committerJohn Crispin <blogic@openwrt.org>2013-02-16 19:25:34 -0500
commit0916b46962cbcac9465d253d0a398435b3965fd5 (patch)
tree67670d815840f79290048cdc230609ea925e2a7d /arch/mips/kernel/irq_cpu.c
parentdcc7310e144c3bf17a86d2f058d60fb525d4b34a (diff)
MIPS: add irqdomain support for the CPU IRQ controller
Add code to load a irq_domain for the MIPS IRQ controller from a devicetree file. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4902/
Diffstat (limited to 'arch/mips/kernel/irq_cpu.c')
-rw-r--r--arch/mips/kernel/irq_cpu.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 972263bcf403..49bc9caaddf8 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -31,6 +31,7 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/irqdomain.h>
34 35
35#include <asm/irq_cpu.h> 36#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h> 37#include <asm/mipsregs.h>
@@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
113 irq_set_chip_and_handler(i, &mips_cpu_irq_controller, 114 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
114 handle_percpu_irq); 115 handle_percpu_irq);
115} 116}
117
118#ifdef CONFIG_IRQ_DOMAIN
119static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
120 irq_hw_number_t hw)
121{
122 static struct irq_chip *chip;
123
124 if (hw < 2 && cpu_has_mipsmt) {
125 /* Software interrupts are used for MT/CMT IPI */
126 chip = &mips_mt_cpu_irq_controller;
127 } else {
128 chip = &mips_cpu_irq_controller;
129 }
130
131 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
132
133 return 0;
134}
135
136static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
137 .map = mips_cpu_intc_map,
138 .xlate = irq_domain_xlate_onecell,
139};
140
141int __init mips_cpu_intc_init(struct device_node *of_node,
142 struct device_node *parent)
143{
144 struct irq_domain *domain;
145
146 /* Mask interrupts. */
147 clear_c0_status(ST0_IM);
148 clear_c0_cause(CAUSEF_IP);
149
150 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
151 &mips_cpu_intc_irq_domain_ops, NULL);
152 if (!domain)
153 panic("Failed to add irqdomain for MIPS CPU\n");
154
155 return 0;
156}
157#endif /* CONFIG_IRQ_DOMAIN */