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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-11-01 12:08:36 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:46 -0500
commit1603b5aca4f15b34848fb5594d0c7b6333b99144 (patch)
tree79272aa41d6510b7256df62e287676885c3960cf /arch/mips/kernel/irq_cpu.c
parentc87b6ebaea034c0e0ce86127870cf1511a307b64 (diff)
[MIPS] IRQ cleanups
This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq_cpu.c')
-rw-r--r--arch/mips/kernel/irq_cpu.c77
1 files changed, 13 insertions, 64 deletions
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 9bb21c7f2149..3b7cfa407e87 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static inline void mips_cpu_irq_enable(unsigned int irq)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
60 local_irq_restore(flags);
61}
62
63static void mips_cpu_irq_disable(unsigned int irq)
64{
65 unsigned long flags;
66
67 local_irq_save(flags);
68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
70 local_irq_restore(flags);
71}
72
73static unsigned int mips_cpu_irq_startup(unsigned int irq)
74{
75 mips_cpu_irq_enable(irq);
76
77 return 0;
78}
79
80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
81
82/*
83 * While we ack the interrupt interrupts are disabled and thus we don't need
84 * to deal with concurrency issues. Same for mips_cpu_irq_end.
85 */
86static void mips_cpu_irq_ack(unsigned int irq)
87{
88 mask_mips_irq(irq);
89}
90
91static void mips_cpu_irq_end(unsigned int irq) 53static void mips_cpu_irq_end(unsigned int irq)
92{ 54{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -96,11 +58,10 @@ static void mips_cpu_irq_end(unsigned int irq)
96 58
97static struct irq_chip mips_cpu_irq_controller = { 59static struct irq_chip mips_cpu_irq_controller = {
98 .typename = "MIPS", 60 .typename = "MIPS",
99 .startup = mips_cpu_irq_startup, 61 .ack = mask_mips_irq,
100 .shutdown = mips_cpu_irq_shutdown, 62 .mask = mask_mips_irq,
101 .enable = mips_cpu_irq_enable, 63 .mask_ack = mask_mips_irq,
102 .disable = mips_cpu_irq_disable, 64 .unmask = unmask_mips_irq,
103 .ack = mips_cpu_irq_ack,
104 .end = mips_cpu_irq_end, 65 .end = mips_cpu_irq_end,
105}; 66};
106 67
@@ -110,8 +71,6 @@ static struct irq_chip mips_cpu_irq_controller = {
110 71
111#define unmask_mips_mt_irq unmask_mips_irq 72#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq 73#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115 74
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) 75static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{ 76{
@@ -119,13 +78,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
119 78
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 79 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags); 80 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq); 81 unmask_mips_mt_irq(irq);
123 82
124 return 0; 83 return 0;
125} 84}
126 85
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/* 86/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need 87 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end. 88 * to deal with concurrency issues. Same for mips_cpu_irq_end.
@@ -143,10 +100,10 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
143static struct irq_chip mips_mt_cpu_irq_controller = { 100static struct irq_chip mips_mt_cpu_irq_controller = {
144 .typename = "MIPS", 101 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup, 102 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack, 103 .ack = mips_mt_cpu_irq_ack,
104 .mask = mask_mips_mt_irq,
105 .mask_ack = mips_mt_cpu_irq_ack,
106 .unmask = unmask_mips_mt_irq,
150 .end = mips_mt_cpu_irq_end, 107 .end = mips_mt_cpu_irq_end,
151}; 108};
152 109
@@ -163,19 +120,11 @@ void __init mips_cpu_irq_init(int irq_base)
163 * leave them uninitialized for other processors. 120 * leave them uninitialized for other processors.
164 */ 121 */
165 if (cpu_has_mipsmt) 122 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) { 123 for (i = irq_base; i < irq_base + 2; i++)
167 irq_desc[i].status = IRQ_DISABLED; 124 set_irq_chip(i, &mips_mt_cpu_irq_controller);
168 irq_desc[i].action = NULL; 125
169 irq_desc[i].depth = 1; 126 for (i = irq_base + 2; i < irq_base + 8; i++)
170 irq_desc[i].chip = &mips_mt_cpu_irq_controller; 127 set_irq_chip(i, &mips_cpu_irq_controller);
171 }
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1;
177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 }
179 128
180 mips_cpu_irq_base = irq_base; 129 mips_cpu_irq_base = irq_base;
181} 130}