aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/irq-rm9000.c
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-01-07 12:14:29 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-02-06 11:53:08 -0500
commit97dcb82de6cc99a5669eb8e342efc24cceb1e77e (patch)
treee195fd57deda8d38652c746c04a7c374cdf951a0 /arch/mips/kernel/irq-rm9000.c
parentb6ec8f069bf202d2bd888aa9137b2cc3aad4c573 (diff)
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq-rm9000.c')
-rw-r--r--arch/mips/kernel/irq-rm9000.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 2e68e4b639f7..27886db89a65 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -18,16 +18,14 @@
18#include <asm/mipsregs.h> 18#include <asm/mipsregs.h>
19#include <asm/system.h> 19#include <asm/system.h>
20 20
21static int irq_base;
22
23static inline void unmask_rm9k_irq(unsigned int irq) 21static inline void unmask_rm9k_irq(unsigned int irq)
24{ 22{
25 set_c0_intcontrol(0x1000 << (irq - irq_base)); 23 set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
26} 24}
27 25
28static inline void mask_rm9k_irq(unsigned int irq) 26static inline void mask_rm9k_irq(unsigned int irq)
29{ 27{
30 clear_c0_intcontrol(0x1000 << (irq - irq_base)); 28 clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
31} 29}
32 30
33static inline void rm9k_cpu_irq_enable(unsigned int irq) 31static inline void rm9k_cpu_irq_enable(unsigned int irq)
@@ -93,8 +91,9 @@ unsigned int rm9000_perfcount_irq;
93 91
94EXPORT_SYMBOL(rm9000_perfcount_irq); 92EXPORT_SYMBOL(rm9000_perfcount_irq);
95 93
96void __init rm9k_cpu_irq_init(int base) 94void __init rm9k_cpu_irq_init(void)
97{ 95{
96 int base = RM9K_CPU_IRQ_BASE;
98 int i; 97 int i;
99 98
100 clear_c0_intcontrol(0x0000f000); /* Mask all */ 99 clear_c0_intcontrol(0x0000f000); /* Mask all */
@@ -106,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base)
106 rm9000_perfcount_irq = base + 1; 105 rm9000_perfcount_irq = base + 1;
107 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 106 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
108 handle_level_irq); 107 handle_level_irq);
109
110 irq_base = base;
111} 108}