diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/kernel/irq-mv6434x.c |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'arch/mips/kernel/irq-mv6434x.c')
-rw-r--r-- | arch/mips/kernel/irq-mv6434x.c | 161 |
1 files changed, 161 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c new file mode 100644 index 000000000000..088bbbc869e6 --- /dev/null +++ b/arch/mips/kernel/irq-mv6434x.c | |||
@@ -0,0 +1,161 @@ | |||
1 | /* | ||
2 | * Copyright 2002 Momentum Computer | ||
3 | * Author: mdharm@momenco.com | ||
4 | * Copyright (C) 2004 Ralf Baechle <ralf@linux-mips.org> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | #include <linux/module.h> | ||
12 | #include <linux/interrupt.h> | ||
13 | #include <linux/kernel.h> | ||
14 | #include <asm/ptrace.h> | ||
15 | #include <linux/sched.h> | ||
16 | #include <linux/kernel_stat.h> | ||
17 | #include <asm/io.h> | ||
18 | #include <asm/irq.h> | ||
19 | #include <linux/mv643xx.h> | ||
20 | |||
21 | static unsigned int irq_base; | ||
22 | |||
23 | static inline int ls1bit32(unsigned int x) | ||
24 | { | ||
25 | int b = 31, s; | ||
26 | |||
27 | s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; | ||
28 | s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; | ||
29 | s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; | ||
30 | s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; | ||
31 | s = 1; if (x << 1 == 0) s = 0; b -= s; | ||
32 | |||
33 | return b; | ||
34 | } | ||
35 | |||
36 | /* mask off an interrupt -- 1 is enable, 0 is disable */ | ||
37 | static inline void mask_mv64340_irq(unsigned int irq) | ||
38 | { | ||
39 | uint32_t value; | ||
40 | |||
41 | if (irq < (irq_base + 32)) { | ||
42 | value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); | ||
43 | value &= ~(1 << (irq - irq_base)); | ||
44 | MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); | ||
45 | } else { | ||
46 | value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); | ||
47 | value &= ~(1 << (irq - irq_base - 32)); | ||
48 | MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); | ||
49 | } | ||
50 | } | ||
51 | |||
52 | /* unmask an interrupt -- 1 is enable, 0 is disable */ | ||
53 | static inline void unmask_mv64340_irq(unsigned int irq) | ||
54 | { | ||
55 | uint32_t value; | ||
56 | |||
57 | if (irq < (irq_base + 32)) { | ||
58 | value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); | ||
59 | value |= 1 << (irq - irq_base); | ||
60 | MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value); | ||
61 | } else { | ||
62 | value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); | ||
63 | value |= 1 << (irq - irq_base - 32); | ||
64 | MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value); | ||
65 | } | ||
66 | } | ||
67 | |||
68 | /* | ||
69 | * Enables the IRQ on Marvell Chip | ||
70 | */ | ||
71 | static void enable_mv64340_irq(unsigned int irq) | ||
72 | { | ||
73 | unmask_mv64340_irq(irq); | ||
74 | } | ||
75 | |||
76 | /* | ||
77 | * Initialize the IRQ on Marvell Chip | ||
78 | */ | ||
79 | static unsigned int startup_mv64340_irq(unsigned int irq) | ||
80 | { | ||
81 | unmask_mv64340_irq(irq); | ||
82 | return 0; | ||
83 | } | ||
84 | |||
85 | /* | ||
86 | * Disables the IRQ on Marvell Chip | ||
87 | */ | ||
88 | static void disable_mv64340_irq(unsigned int irq) | ||
89 | { | ||
90 | mask_mv64340_irq(irq); | ||
91 | } | ||
92 | |||
93 | /* | ||
94 | * Masks and ACKs an IRQ | ||
95 | */ | ||
96 | static void mask_and_ack_mv64340_irq(unsigned int irq) | ||
97 | { | ||
98 | mask_mv64340_irq(irq); | ||
99 | } | ||
100 | |||
101 | /* | ||
102 | * End IRQ processing | ||
103 | */ | ||
104 | static void end_mv64340_irq(unsigned int irq) | ||
105 | { | ||
106 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
107 | unmask_mv64340_irq(irq); | ||
108 | } | ||
109 | |||
110 | /* | ||
111 | * Interrupt handler for interrupts coming from the Marvell chip. | ||
112 | * It could be built in ethernet ports etc... | ||
113 | */ | ||
114 | void ll_mv64340_irq(struct pt_regs *regs) | ||
115 | { | ||
116 | unsigned int irq_src_low, irq_src_high; | ||
117 | unsigned int irq_mask_low, irq_mask_high; | ||
118 | |||
119 | /* read the interrupt status registers */ | ||
120 | irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW); | ||
121 | irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH); | ||
122 | irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW); | ||
123 | irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH); | ||
124 | |||
125 | /* mask for just the interrupts we want */ | ||
126 | irq_src_low &= irq_mask_low; | ||
127 | irq_src_high &= irq_mask_high; | ||
128 | |||
129 | if (irq_src_low) | ||
130 | do_IRQ(ls1bit32(irq_src_low) + irq_base, regs); | ||
131 | else | ||
132 | do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs); | ||
133 | } | ||
134 | |||
135 | #define shutdown_mv64340_irq disable_mv64340_irq | ||
136 | |||
137 | struct hw_interrupt_type mv64340_irq_type = { | ||
138 | "MV-64340", | ||
139 | startup_mv64340_irq, | ||
140 | shutdown_mv64340_irq, | ||
141 | enable_mv64340_irq, | ||
142 | disable_mv64340_irq, | ||
143 | mask_and_ack_mv64340_irq, | ||
144 | end_mv64340_irq, | ||
145 | NULL | ||
146 | }; | ||
147 | |||
148 | void __init mv64340_irq_init(unsigned int base) | ||
149 | { | ||
150 | int i; | ||
151 | |||
152 | /* Reset irq handlers pointers to NULL */ | ||
153 | for (i = base; i < base + 64; i++) { | ||
154 | irq_desc[i].status = IRQ_DISABLED; | ||
155 | irq_desc[i].action = 0; | ||
156 | irq_desc[i].depth = 2; | ||
157 | irq_desc[i].handler = &mv64340_irq_type; | ||
158 | } | ||
159 | |||
160 | irq_base = base; | ||
161 | } | ||