diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-27 09:19:28 -0400 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-29 08:48:07 -0400 |
commit | e4ec7989b4e55d9275ebac66230b7dac6dcb1fae (patch) | |
tree | b42cd789681bada83b0051899ed66c1c0e2bbea2 /arch/mips/kernel/irq-msc01.c | |
parent | 9efbc3fba2cd7f703b55d72e5168ed4348930442 (diff) |
MIPS: Convert the irq functions to the new names
Scripted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index fc800cd9947e..0c6afeed89d2 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -137,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma | |||
137 | 137 | ||
138 | switch (imp->im_type) { | 138 | switch (imp->im_type) { |
139 | case MSC01_IRQ_EDGE: | 139 | case MSC01_IRQ_EDGE: |
140 | set_irq_chip_and_handler_name(irqbase + n, | 140 | irq_set_chip_and_handler_name(irqbase + n, |
141 | &msc_edgeirq_type, handle_edge_irq, "edge"); | 141 | &msc_edgeirq_type, |
142 | handle_edge_irq, | ||
143 | "edge"); | ||
142 | if (cpu_has_veic) | 144 | if (cpu_has_veic) |
143 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 145 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
144 | else | 146 | else |
145 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 147 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
146 | break; | 148 | break; |
147 | case MSC01_IRQ_LEVEL: | 149 | case MSC01_IRQ_LEVEL: |
148 | set_irq_chip_and_handler_name(irqbase+n, | 150 | irq_set_chip_and_handler_name(irqbase + n, |
149 | &msc_levelirq_type, handle_level_irq, "level"); | 151 | &msc_levelirq_type, |
152 | handle_level_irq, | ||
153 | "level"); | ||
150 | if (cpu_has_veic) | 154 | if (cpu_has_veic) |
151 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
152 | else | 156 | else |