diff options
author | Chris Dearman <chris@mips.com> | 2007-05-08 09:05:39 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 09:28:31 -0400 |
commit | d725cf3818b12a17d78b87a2de19e8eec17126ae (patch) | |
tree | 9d200020488b886201771bd6516c63ef43397baa /arch/mips/kernel/irq-msc01.c | |
parent | ef300e42234eac066b193c871714203d999b481c (diff) |
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/irq-msc01.c')
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 2967537221e2..410868b5ea5f 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = { | |||
132 | }; | 132 | }; |
133 | 133 | ||
134 | 134 | ||
135 | void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | 135 | void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) |
136 | { | 136 | { |
137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); | 137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); |
138 | 138 | ||
139 | _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000); | 139 | _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); |
140 | 140 | ||
141 | /* Reset interrupt controller - initialises all registers to 0 */ | 141 | /* Reset interrupt controller - initialises all registers to 0 */ |
142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); | 142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); |
@@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
148 | 148 | ||
149 | switch (imp->im_type) { | 149 | switch (imp->im_type) { |
150 | case MSC01_IRQ_EDGE: | 150 | case MSC01_IRQ_EDGE: |
151 | set_irq_chip(base+n, &msc_edgeirq_type); | 151 | set_irq_chip(irqbase+n, &msc_edgeirq_type); |
152 | if (cpu_has_veic) | 152 | if (cpu_has_veic) |
153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
154 | else | 154 | else |
155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
156 | break; | 156 | break; |
157 | case MSC01_IRQ_LEVEL: | 157 | case MSC01_IRQ_LEVEL: |
158 | set_irq_chip(base+n, &msc_levelirq_type); | 158 | set_irq_chip(irqbase+n, &msc_levelirq_type); |
159 | if (cpu_has_veic) | 159 | if (cpu_has_veic) |
160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
161 | else | 161 | else |
@@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
163 | } | 163 | } |
164 | } | 164 | } |
165 | 165 | ||
166 | irq_base = base; | 166 | irq_base = irqbase; |
167 | 167 | ||
168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ | 168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ |
169 | 169 | ||