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authorTejun Heo <tj@kernel.org>2009-08-14 01:41:02 -0400
committerTejun Heo <tj@kernel.org>2009-08-14 01:45:31 -0400
commit384be2b18a5f9475eab9ca2bdfa95cc1a04ef59c (patch)
tree04c93f391a1b65c8bf8d7ba8643c07d26c26590a /arch/mips/kernel/irq-gic.c
parenta76761b621bcd8336065c4fe3a74f046858bc34c (diff)
parent142d44b0dd6741a64a7bdbe029110e7c1dcf1d23 (diff)
Merge branch 'percpu-for-linus' into percpu-for-next
Conflicts: arch/sparc/kernel/smp_64.c arch/x86/kernel/cpu/perf_counter.c arch/x86/kernel/setup_percpu.c drivers/cpufreq/cpufreq_ondemand.c mm/percpu.c Conflicts in core and arch percpu codes are mostly from commit ed78e1e078dd44249f88b1dd8c76dafb39567161 which substituted many num_possible_cpus() with nr_cpu_ids. As for-next branch has moved all the first chunk allocators into mm/percpu.c, the changes are moved from arch code to mm/percpu.c. Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'arch/mips/kernel/irq-gic.c')
-rw-r--r--arch/mips/kernel/irq-gic.c19
1 files changed, 8 insertions, 11 deletions
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 39000f103f2c..d2072cd38592 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -107,9 +107,7 @@ static unsigned int gic_irq_startup(unsigned int irq)
107{ 107{
108 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 108 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
109 irq -= _irqbase; 109 irq -= _irqbase;
110 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ 110 GIC_SET_INTR_MASK(irq, 1);
111 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
112 1 << (irq % 32));
113 return 0; 111 return 0;
114} 112}
115 113
@@ -120,8 +118,7 @@ static void gic_irq_ack(unsigned int irq)
120#endif 118#endif
121 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 119 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
122 irq -= _irqbase; 120 irq -= _irqbase;
123 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))), 121 GIC_CLR_INTR_MASK(irq, 1);
124 1 << (irq % 32));
125 122
126 if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { 123 if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) {
127 if (!gic_wedgeb2bok) 124 if (!gic_wedgeb2bok)
@@ -138,18 +135,14 @@ static void gic_mask_irq(unsigned int irq)
138{ 135{
139 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 136 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
140 irq -= _irqbase; 137 irq -= _irqbase;
141 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ 138 GIC_CLR_INTR_MASK(irq, 1);
142 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))),
143 1 << (irq % 32));
144} 139}
145 140
146static void gic_unmask_irq(unsigned int irq) 141static void gic_unmask_irq(unsigned int irq)
147{ 142{
148 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 143 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
149 irq -= _irqbase; 144 irq -= _irqbase;
150 /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ 145 GIC_SET_INTR_MASK(irq, 1);
151 GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))),
152 1 << (irq % 32));
153} 146}
154 147
155#ifdef CONFIG_SMP 148#ifdef CONFIG_SMP
@@ -254,6 +247,10 @@ static void __init gic_basic_init(void)
254 if (cpu == X) 247 if (cpu == X)
255 continue; 248 continue;
256 249
250 if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
251 _intrmap[i].ipiflag == 0)
252 continue;
253
257 setup_intr(_intrmap[i].intrnum, 254 setup_intr(_intrmap[i].intrnum,
258 _intrmap[i].cpunum, 255 _intrmap[i].cpunum,
259 _intrmap[i].pin, 256 _intrmap[i].pin,