[MIPS] MT: Improved multithreading support.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 34 insertions, 0 deletions

diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index b1939a486d2c..d101d2fb24ca 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -17,6 +17,9 @@
 #include <asm/isadep.h>
 #include <asm/thread_info.h>
 #include <asm/war.h>
+#ifdef CONFIG_MIPS_MT_SMTC
+#include <asm/mipsmtregs.h>
+#endif
 
 #ifdef CONFIG_PREEMPT
         .macro  preempt_stop
@@ -75,6 +78,37 @@ FEXPORT(syscall_exit)
         bnez    t0, syscall_exit_work
 
 FEXPORT(restore_all)                    # restore full frame
+#ifdef CONFIG_MIPS_MT_SMTC
+/* Detect and execute deferred IPI "interrupts" */
+        move    a0,sp
+        jal     deferred_smtc_ipi
+/* Re-arm any temporarily masked interrupts not explicitly "acked" */
+        mfc0    v0, CP0_TCSTATUS
+        ori     v1, v0, TCSTATUS_IXMT
+        mtc0    v1, CP0_TCSTATUS
+        andi    v0, TCSTATUS_IXMT
+        ehb
+        mfc0    t0, CP0_TCCONTEXT
+        DMT     9                               # dmt t1
+        jal     mips_ihb
+        mfc0    t2, CP0_STATUS
+        andi    t3, t0, 0xff00
+        or      t2, t2, t3
+        mtc0    t2, CP0_STATUS
+        ehb
+        andi    t1, t1, VPECONTROL_TE
+        beqz    t1, 1f
+        EMT
+1:
+        mfc0    v1, CP0_TCSTATUS
+        /* We set IXMT above, XOR should cler it here */
+        xori    v1, v1, TCSTATUS_IXMT
+        or      v1, v0, v1
+        mtc0    v1, CP0_TCSTATUS
+        ehb
+        xor     t0, t0, t3
+        mtc0    t0, CP0_TCCONTEXT
+#endif /* CONFIG_MIPS_MT_SMTC */
         .set    noat
         RESTORE_TEMP
         RESTORE_AT