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authorRalf Baechle <ralf@linux-mips.org>2007-11-24 17:33:28 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-11-26 12:26:14 -0500
commit940f6b48a130e0a33cb8bd397dd0e277166470ad (patch)
tree03bd36fcb9b5c8d77f5de2930ff32d770f5cdf4e /arch/mips/kernel/csrc-r4k.c
parent5aa85c9fc49a6ce44dc10a42e2011bbde9dc445a (diff)
[MIPS] Only build r4k clocksource for systems that work ok with it.
In particular as-is it's not suited for multicore and mutiprocessors systems where there is on guarantee that the counter are synchronized or running from the same clock at all. This broke Sibyte and probably others since the "[MIPS] Handle R4000/R4400 mfc0 from count register." commit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/csrc-r4k.c')
-rw-r--r--arch/mips/kernel/csrc-r4k.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
new file mode 100644
index 000000000000..74c5c62365a8
--- /dev/null
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -0,0 +1,29 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8
9static cycle_t c0_hpt_read(void)
10{
11 return read_c0_count();
12}
13
14static struct clocksource clocksource_mips = {
15 .name = "MIPS",
16 .read = c0_hpt_read,
17 .mask = CLOCKSOURCE_MASK(32),
18 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
19};
20
21static void __init init_mips_clocksource(void)
22{
23 /* Calclate a somewhat reasonable rating value */
24 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
25
26 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
27
28 clocksource_register(&clocksource_mips);
29}