MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip

Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 20 insertions, 0 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd..9b6633171a1f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
         case CPU_BCM6358:
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_JZRISC:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -956,6 +957,22 @@ platform:
         }
 }
 
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+{
+        decode_configs(c);
+        /* JZRISC does not implement the CP0 counter. */
+        c->options &= ~MIPS_CPU_COUNTER;
+        switch (c->processor_id & 0xff00) {
+        case PRID_IMP_JZRISC:
+                c->cputype = CPU_JZRISC;
+                __cpu_name[cpu] = "Ingenic JZRISC";
+                break;
+        default:
+                panic("Unknown Ingenic Processor ID!");
+                break;
+        }
+}
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void)
         case PRID_COMP_CAVIUM:
                 cpu_probe_cavium(c, cpu);
                 break;
+        case PRID_COMP_INGENIC:
+                cpu_probe_ingenic(c, cpu);
+                break;
         }
 
         BUG_ON(!__cpu_name[cpu]);