diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-06-06 12:40:58 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:31:19 -0400 |
commit | d5b6f1db5d5a7ba3f2271e5018db7c8c5c4eeea1 (patch) | |
tree | b5d6c33db67287e91f540d81ff34746839c4bde0 /arch/mips/kernel/cpu-probe.c | |
parent | 81731f79974ffb0a7b4aabd3c3e472f8d46b057c (diff) |
For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style)
TLB, so no need to set it separately for each implementation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1ae7762fd084..2b6db681417d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -422,7 +422,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c) | |||
422 | config0 = read_c0_config(); | 422 | config0 = read_c0_config(); |
423 | 423 | ||
424 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | 424 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) |
425 | c->options |= MIPS_CPU_TLB; | 425 | c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB; |
426 | isa = (config0 & MIPS_CONF_AT) >> 13; | 426 | isa = (config0 & MIPS_CONF_AT) >> 13; |
427 | switch (isa) { | 427 | switch (isa) { |
428 | case 0: | 428 | case 0: |
@@ -510,7 +510,6 @@ static inline void decode_configs(struct cpuinfo_mips *c) | |||
510 | static inline void cpu_probe_mips(struct cpuinfo_mips *c) | 510 | static inline void cpu_probe_mips(struct cpuinfo_mips *c) |
511 | { | 511 | { |
512 | decode_configs(c); | 512 | decode_configs(c); |
513 | c->options |= MIPS_CPU_4KTLB; | ||
514 | switch (c->processor_id & 0xff00) { | 513 | switch (c->processor_id & 0xff00) { |
515 | case PRID_IMP_4KC: | 514 | case PRID_IMP_4KC: |
516 | c->cputype = CPU_4KC; | 515 | c->cputype = CPU_4KC; |
@@ -545,7 +544,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) | |||
545 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) | 544 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) |
546 | { | 545 | { |
547 | decode_configs(c); | 546 | decode_configs(c); |
548 | c->options |= MIPS_CPU_4KTLB; | ||
549 | switch (c->processor_id & 0xff00) { | 547 | switch (c->processor_id & 0xff00) { |
550 | case PRID_IMP_AU1_REV1: | 548 | case PRID_IMP_AU1_REV1: |
551 | case PRID_IMP_AU1_REV2: | 549 | case PRID_IMP_AU1_REV2: |
@@ -576,7 +574,6 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) | |||
576 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) | 574 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) |
577 | { | 575 | { |
578 | decode_configs(c); | 576 | decode_configs(c); |
579 | c->options |= MIPS_CPU_4KTLB; | ||
580 | switch (c->processor_id & 0xff00) { | 577 | switch (c->processor_id & 0xff00) { |
581 | case PRID_IMP_SB1: | 578 | case PRID_IMP_SB1: |
582 | c->cputype = CPU_SB1; | 579 | c->cputype = CPU_SB1; |
@@ -591,7 +588,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) | |||
591 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) | 588 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) |
592 | { | 589 | { |
593 | decode_configs(c); | 590 | decode_configs(c); |
594 | c->options |= MIPS_CPU_4KTLB; | ||
595 | switch (c->processor_id & 0xff00) { | 591 | switch (c->processor_id & 0xff00) { |
596 | case PRID_IMP_SR71000: | 592 | case PRID_IMP_SR71000: |
597 | c->cputype = CPU_SR71000; | 593 | c->cputype = CPU_SR71000; |