aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/cpu-probe.c
diff options
context:
space:
mode:
authorManuel Lauss <manuel.lauss@googlemail.com>2009-08-22 12:09:27 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-09-17 14:07:50 -0400
commit2882b0c63ac6085fd5c18959240b6f7d6ffb8d5b (patch)
treea95571203336aaec43dd505c81ab7dc8e46efa78 /arch/mips/kernel/cpu-probe.c
parent9d24bafb0d1ecf636f71a56f9d6f071f5c7a882d (diff)
MIPS: Alchemy: get rid of allow_au1k_wait
Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1abe9905c9c1..6e4807a19c00 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -91,16 +91,13 @@ static void rm7k_wait_irqoff(void)
91 local_irq_enable(); 91 local_irq_enable();
92} 92}
93 93
94/* The Au1xxx wait is available only if using 32khz counter or 94/*
95 * external timer source, but specifically not CP0 Counter. */ 95 * The Au1xxx wait is available only if using 32khz counter or
96int allow_au1k_wait; 96 * external timer source, but specifically not CP0 Counter.
97 97 * alchemy/common/time.c may override cpu_wait!
98 */
98static void au1k_wait(void) 99static void au1k_wait(void)
99{ 100{
100 if (!allow_au1k_wait)
101 return;
102
103 /* using the wait instruction makes CP0 counter unusable */
104 __asm__(" .set mips3 \n" 101 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n" 102 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n" 103 " cache 0x14, 32(%0) \n"