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authorLinus Torvalds <torvalds@linux-foundation.org>2009-11-03 11:09:57 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-11-03 11:09:57 -0500
commit9ddfd92909ac969758684e309e62198f549786a3 (patch)
treee5799c0bb894a98f8c8948ebb568f336233fc0db /arch/mips/kernel/cpu-probe.c
parent38dc63459f185795b24a39f3f4921a433ea9980b (diff)
parent049a31afe16e733a54f7da7fdf845034758c6ee1 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits) MIPS: O32: Fix ppoll MIPS: Oprofile: Rename cpu_type from godson2 to loongson2 MIPS: Alchemy: Fix hang with high-frequency edge interrupts MIPS: TXx9: Fix spi-baseclk value MIPS: bcm63xx: Set the correct BCM3302 CPU name MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store MIPS: Avoid potential hazard on Context register MIPS: Octeon: Use lockless interrupt controller operations when possible. MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache MIPS: SMTC: Avoid queing multiple reschedule IPIs MIPS: GCMP: Avoid accessing registers when they are not present MIPS: GIC: Random fixes and enhancements. MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands MIPS: SPRAM: Clean up support code a little MIPS: 1004K: Enable SPRAM support. MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4 MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT. MIPS: MTI: Fix accesses to device registers on MIPS boards ...
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f709657e4dcd..7a51866068a4 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,7 +23,7 @@
23#include <asm/mipsregs.h> 23#include <asm/mipsregs.h>
24#include <asm/system.h> 24#include <asm/system.h>
25#include <asm/watch.h> 25#include <asm/watch.h>
26 26#include <asm/spram.h>
27/* 27/*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This 29 * the implementation of the "wait" feature differs between CPU families. This
@@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
711 mips_probe_watch_registers(c); 711 mips_probe_watch_registers(c);
712} 712}
713 713
714#ifdef CONFIG_CPU_MIPSR2
715extern void spram_config(void);
716#else
717static inline void spram_config(void) {}
718#endif
719
720static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 714static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
721{ 715{
722 decode_configs(c); 716 decode_configs(c);