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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/kernel/cpu-probe.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c598
1 files changed, 598 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
new file mode 100644
index 000000000000..4bb849582314
--- /dev/null
+++ b/arch/mips/kernel/cpu-probe.c
@@ -0,0 +1,598 @@
1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/ptrace.h>
18#include <linux/stddef.h>
19
20#include <asm/bugs.h>
21#include <asm/cpu.h>
22#include <asm/fpu.h>
23#include <asm/mipsregs.h>
24#include <asm/system.h>
25
26/*
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
31 * the CPU very much.
32 */
33void (*cpu_wait)(void) = NULL;
34
35static void r3081_wait(void)
36{
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
39}
40
41static void r39xx_wait(void)
42{
43 unsigned long cfg = read_c0_conf();
44 write_c0_conf(cfg | TX39_CONF_HALT);
45}
46
47static void r4k_wait(void)
48{
49 __asm__(".set\tmips3\n\t"
50 "wait\n\t"
51 ".set\tmips0");
52}
53
54/*
55 * The Au1xxx wait is available only if we run CONFIG_PM and
56 * the timer setup found we had a 32KHz counter available.
57 * There are still problems with functions that may call au1k_wait
58 * directly, but that will be discovered pretty quickly.
59 */
60extern void (*au1k_wait_ptr)(void);
61
62void au1k_wait(void)
63{
64#ifdef CONFIG_PM
65 /* using the wait instruction makes CP0 counter unusable */
66 __asm__(".set\tmips3\n\t"
67 "wait\n\t"
68 "nop\n\t"
69 "nop\n\t"
70 "nop\n\t"
71 "nop\n\t"
72 ".set\tmips0");
73#else
74 __asm__("nop\n\t"
75 "nop");
76#endif
77}
78
79static inline void check_wait(void)
80{
81 struct cpuinfo_mips *c = &current_cpu_data;
82
83 printk("Checking for 'wait' instruction... ");
84 switch (c->cputype) {
85 case CPU_R3081:
86 case CPU_R3081E:
87 cpu_wait = r3081_wait;
88 printk(" available.\n");
89 break;
90 case CPU_TX3927:
91 cpu_wait = r39xx_wait;
92 printk(" available.\n");
93 break;
94 case CPU_R4200:
95/* case CPU_R4300: */
96 case CPU_R4600:
97 case CPU_R4640:
98 case CPU_R4650:
99 case CPU_R4700:
100 case CPU_R5000:
101 case CPU_NEVADA:
102 case CPU_RM7000:
103 case CPU_RM9000:
104 case CPU_TX49XX:
105 case CPU_4KC:
106 case CPU_4KEC:
107 case CPU_4KSC:
108 case CPU_5KC:
109/* case CPU_20KC:*/
110 case CPU_24K:
111 case CPU_25KF:
112 cpu_wait = r4k_wait;
113 printk(" available.\n");
114 break;
115#ifdef CONFIG_PM
116 case CPU_AU1000:
117 case CPU_AU1100:
118 case CPU_AU1500:
119 if (au1k_wait_ptr != NULL) {
120 cpu_wait = au1k_wait_ptr;
121 printk(" available.\n");
122 }
123 else {
124 printk(" unavailable.\n");
125 }
126 break;
127#endif
128 default:
129 printk(" unavailable.\n");
130 break;
131 }
132}
133
134void __init check_bugs32(void)
135{
136 check_wait();
137}
138
139/*
140 * Probe whether cpu has config register by trying to play with
141 * alternate cache bit and see whether it matters.
142 * It's used by cpu_probe to distinguish between R3000A and R3081.
143 */
144static inline int cpu_has_confreg(void)
145{
146#ifdef CONFIG_CPU_R3000
147 extern unsigned long r3k_cache_size(unsigned long);
148 unsigned long size1, size2;
149 unsigned long cfg = read_c0_conf();
150
151 size1 = r3k_cache_size(ST0_ISC);
152 write_c0_conf(cfg ^ R30XX_CONF_AC);
153 size2 = r3k_cache_size(ST0_ISC);
154 write_c0_conf(cfg);
155 return size1 != size2;
156#else
157 return 0;
158#endif
159}
160
161/*
162 * Get the FPU Implementation/Revision.
163 */
164static inline unsigned long cpu_get_fpu_id(void)
165{
166 unsigned long tmp, fpu_id;
167
168 tmp = read_c0_status();
169 __enable_fpu();
170 fpu_id = read_32bit_cp1_register(CP1_REVISION);
171 write_c0_status(tmp);
172 return fpu_id;
173}
174
175/*
176 * Check the CPU has an FPU the official way.
177 */
178static inline int __cpu_has_fpu(void)
179{
180 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
181}
182
183#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
184 | MIPS_CPU_COUNTER)
185
186static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
187{
188 switch (c->processor_id & 0xff00) {
189 case PRID_IMP_R2000:
190 c->cputype = CPU_R2000;
191 c->isa_level = MIPS_CPU_ISA_I;
192 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
193 if (__cpu_has_fpu())
194 c->options |= MIPS_CPU_FPU;
195 c->tlbsize = 64;
196 break;
197 case PRID_IMP_R3000:
198 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
199 if (cpu_has_confreg())
200 c->cputype = CPU_R3081E;
201 else
202 c->cputype = CPU_R3000A;
203 else
204 c->cputype = CPU_R3000;
205 c->isa_level = MIPS_CPU_ISA_I;
206 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
207 if (__cpu_has_fpu())
208 c->options |= MIPS_CPU_FPU;
209 c->tlbsize = 64;
210 break;
211 case PRID_IMP_R4000:
212 if (read_c0_config() & CONF_SC) {
213 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
214 c->cputype = CPU_R4400PC;
215 else
216 c->cputype = CPU_R4000PC;
217 } else {
218 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
219 c->cputype = CPU_R4400SC;
220 else
221 c->cputype = CPU_R4000SC;
222 }
223
224 c->isa_level = MIPS_CPU_ISA_III;
225 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
226 MIPS_CPU_WATCH | MIPS_CPU_VCE |
227 MIPS_CPU_LLSC;
228 c->tlbsize = 48;
229 break;
230 case PRID_IMP_VR41XX:
231 switch (c->processor_id & 0xf0) {
232#ifndef CONFIG_VR4181
233 case PRID_REV_VR4111:
234 c->cputype = CPU_VR4111;
235 break;
236#else
237 case PRID_REV_VR4181:
238 c->cputype = CPU_VR4181;
239 break;
240#endif
241 case PRID_REV_VR4121:
242 c->cputype = CPU_VR4121;
243 break;
244 case PRID_REV_VR4122:
245 if ((c->processor_id & 0xf) < 0x3)
246 c->cputype = CPU_VR4122;
247 else
248 c->cputype = CPU_VR4181A;
249 break;
250 case PRID_REV_VR4130:
251 if ((c->processor_id & 0xf) < 0x4)
252 c->cputype = CPU_VR4131;
253 else
254 c->cputype = CPU_VR4133;
255 break;
256 default:
257 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
258 c->cputype = CPU_VR41XX;
259 break;
260 }
261 c->isa_level = MIPS_CPU_ISA_III;
262 c->options = R4K_OPTS;
263 c->tlbsize = 32;
264 break;
265 case PRID_IMP_R4300:
266 c->cputype = CPU_R4300;
267 c->isa_level = MIPS_CPU_ISA_III;
268 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
269 MIPS_CPU_LLSC;
270 c->tlbsize = 32;
271 break;
272 case PRID_IMP_R4600:
273 c->cputype = CPU_R4600;
274 c->isa_level = MIPS_CPU_ISA_III;
275 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
276 c->tlbsize = 48;
277 break;
278 #if 0
279 case PRID_IMP_R4650:
280 /*
281 * This processor doesn't have an MMU, so it's not
282 * "real easy" to run Linux on it. It is left purely
283 * for documentation. Commented out because it shares
284 * it's c0_prid id number with the TX3900.
285 */
286 c->cputype = CPU_R4650;
287 c->isa_level = MIPS_CPU_ISA_III;
288 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
289 c->tlbsize = 48;
290 break;
291 #endif
292 case PRID_IMP_TX39:
293 c->isa_level = MIPS_CPU_ISA_I;
294 c->options = MIPS_CPU_TLB;
295
296 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
297 c->cputype = CPU_TX3927;
298 c->tlbsize = 64;
299 } else {
300 switch (c->processor_id & 0xff) {
301 case PRID_REV_TX3912:
302 c->cputype = CPU_TX3912;
303 c->tlbsize = 32;
304 break;
305 case PRID_REV_TX3922:
306 c->cputype = CPU_TX3922;
307 c->tlbsize = 64;
308 break;
309 default:
310 c->cputype = CPU_UNKNOWN;
311 break;
312 }
313 }
314 break;
315 case PRID_IMP_R4700:
316 c->cputype = CPU_R4700;
317 c->isa_level = MIPS_CPU_ISA_III;
318 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
319 MIPS_CPU_LLSC;
320 c->tlbsize = 48;
321 break;
322 case PRID_IMP_TX49:
323 c->cputype = CPU_TX49XX;
324 c->isa_level = MIPS_CPU_ISA_III;
325 c->options = R4K_OPTS | MIPS_CPU_LLSC;
326 if (!(c->processor_id & 0x08))
327 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
328 c->tlbsize = 48;
329 break;
330 case PRID_IMP_R5000:
331 c->cputype = CPU_R5000;
332 c->isa_level = MIPS_CPU_ISA_IV;
333 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
334 MIPS_CPU_LLSC;
335 c->tlbsize = 48;
336 break;
337 case PRID_IMP_R5432:
338 c->cputype = CPU_R5432;
339 c->isa_level = MIPS_CPU_ISA_IV;
340 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
341 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
342 c->tlbsize = 48;
343 break;
344 case PRID_IMP_R5500:
345 c->cputype = CPU_R5500;
346 c->isa_level = MIPS_CPU_ISA_IV;
347 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
348 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
349 c->tlbsize = 48;
350 break;
351 case PRID_IMP_NEVADA:
352 c->cputype = CPU_NEVADA;
353 c->isa_level = MIPS_CPU_ISA_IV;
354 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
355 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
356 c->tlbsize = 48;
357 break;
358 case PRID_IMP_R6000:
359 c->cputype = CPU_R6000;
360 c->isa_level = MIPS_CPU_ISA_II;
361 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
362 MIPS_CPU_LLSC;
363 c->tlbsize = 32;
364 break;
365 case PRID_IMP_R6000A:
366 c->cputype = CPU_R6000A;
367 c->isa_level = MIPS_CPU_ISA_II;
368 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
369 MIPS_CPU_LLSC;
370 c->tlbsize = 32;
371 break;
372 case PRID_IMP_RM7000:
373 c->cputype = CPU_RM7000;
374 c->isa_level = MIPS_CPU_ISA_IV;
375 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
376 MIPS_CPU_LLSC;
377 /*
378 * Undocumented RM7000: Bit 29 in the info register of
379 * the RM7000 v2.0 indicates if the TLB has 48 or 64
380 * entries.
381 *
382 * 29 1 => 64 entry JTLB
383 * 0 => 48 entry JTLB
384 */
385 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
386 break;
387 case PRID_IMP_RM9000:
388 c->cputype = CPU_RM9000;
389 c->isa_level = MIPS_CPU_ISA_IV;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
391 MIPS_CPU_LLSC;
392 /*
393 * Bit 29 in the info register of the RM9000
394 * indicates if the TLB has 48 or 64 entries.
395 *
396 * 29 1 => 64 entry JTLB
397 * 0 => 48 entry JTLB
398 */
399 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
400 break;
401 case PRID_IMP_R8000:
402 c->cputype = CPU_R8000;
403 c->isa_level = MIPS_CPU_ISA_IV;
404 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
405 MIPS_CPU_FPU | MIPS_CPU_32FPR |
406 MIPS_CPU_LLSC;
407 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
408 break;
409 case PRID_IMP_R10000:
410 c->cputype = CPU_R10000;
411 c->isa_level = MIPS_CPU_ISA_IV;
412 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
413 MIPS_CPU_FPU | MIPS_CPU_32FPR |
414 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
415 MIPS_CPU_LLSC;
416 c->tlbsize = 64;
417 break;
418 case PRID_IMP_R12000:
419 c->cputype = CPU_R12000;
420 c->isa_level = MIPS_CPU_ISA_IV;
421 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
422 MIPS_CPU_FPU | MIPS_CPU_32FPR |
423 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
424 MIPS_CPU_LLSC;
425 c->tlbsize = 64;
426 break;
427 }
428}
429
430static inline void decode_config1(struct cpuinfo_mips *c)
431{
432 unsigned long config0 = read_c0_config();
433 unsigned long config1;
434
435 if ((config0 & (1 << 31)) == 0)
436 return; /* actually wort a panic() */
437
438 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
439 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
440 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
441 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
442 config1 = read_c0_config1();
443 if (config1 & (1 << 3))
444 c->options |= MIPS_CPU_WATCH;
445 if (config1 & (1 << 2))
446 c->options |= MIPS_CPU_MIPS16;
447 if (config1 & (1 << 1))
448 c->options |= MIPS_CPU_EJTAG;
449 if (config1 & 1) {
450 c->options |= MIPS_CPU_FPU;
451 c->options |= MIPS_CPU_32FPR;
452 }
453 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
454
455 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
456}
457
458static inline void cpu_probe_mips(struct cpuinfo_mips *c)
459{
460 decode_config1(c);
461 switch (c->processor_id & 0xff00) {
462 case PRID_IMP_4KC:
463 c->cputype = CPU_4KC;
464 c->isa_level = MIPS_CPU_ISA_M32;
465 break;
466 case PRID_IMP_4KEC:
467 c->cputype = CPU_4KEC;
468 c->isa_level = MIPS_CPU_ISA_M32;
469 break;
470 case PRID_IMP_4KSC:
471 c->cputype = CPU_4KSC;
472 c->isa_level = MIPS_CPU_ISA_M32;
473 break;
474 case PRID_IMP_5KC:
475 c->cputype = CPU_5KC;
476 c->isa_level = MIPS_CPU_ISA_M64;
477 break;
478 case PRID_IMP_20KC:
479 c->cputype = CPU_20KC;
480 c->isa_level = MIPS_CPU_ISA_M64;
481 break;
482 case PRID_IMP_24K:
483 c->cputype = CPU_24K;
484 c->isa_level = MIPS_CPU_ISA_M32;
485 break;
486 case PRID_IMP_25KF:
487 c->cputype = CPU_25KF;
488 c->isa_level = MIPS_CPU_ISA_M64;
489 /* Probe for L2 cache */
490 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
491 break;
492 }
493}
494
495static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
496{
497 decode_config1(c);
498 switch (c->processor_id & 0xff00) {
499 case PRID_IMP_AU1_REV1:
500 case PRID_IMP_AU1_REV2:
501 switch ((c->processor_id >> 24) & 0xff) {
502 case 0:
503 c->cputype = CPU_AU1000;
504 break;
505 case 1:
506 c->cputype = CPU_AU1500;
507 break;
508 case 2:
509 c->cputype = CPU_AU1100;
510 break;
511 case 3:
512 c->cputype = CPU_AU1550;
513 break;
514 default:
515 panic("Unknown Au Core!");
516 break;
517 }
518 c->isa_level = MIPS_CPU_ISA_M32;
519 break;
520 }
521}
522
523static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
524{
525 decode_config1(c);
526 switch (c->processor_id & 0xff00) {
527 case PRID_IMP_SB1:
528 c->cputype = CPU_SB1;
529 c->isa_level = MIPS_CPU_ISA_M64;
530 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
531 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
532 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
533 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
534#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
535 /* FPU in pass1 is known to have issues. */
536 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
537#endif
538 break;
539 }
540}
541
542static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
543{
544 decode_config1(c);
545 switch (c->processor_id & 0xff00) {
546 case PRID_IMP_SR71000:
547 c->cputype = CPU_SR71000;
548 c->isa_level = MIPS_CPU_ISA_M64;
549 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
550 MIPS_CPU_4KTLB | MIPS_CPU_FPU |
551 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
552 c->scache.ways = 8;
553 c->tlbsize = 64;
554 break;
555 }
556}
557
558__init void cpu_probe(void)
559{
560 struct cpuinfo_mips *c = &current_cpu_data;
561
562 c->processor_id = PRID_IMP_UNKNOWN;
563 c->fpu_id = FPIR_IMP_NONE;
564 c->cputype = CPU_UNKNOWN;
565
566 c->processor_id = read_c0_prid();
567 switch (c->processor_id & 0xff0000) {
568 case PRID_COMP_LEGACY:
569 cpu_probe_legacy(c);
570 break;
571 case PRID_COMP_MIPS:
572 cpu_probe_mips(c);
573 break;
574 case PRID_COMP_ALCHEMY:
575 cpu_probe_alchemy(c);
576 break;
577 case PRID_COMP_SIBYTE:
578 cpu_probe_sibyte(c);
579 break;
580
581 case PRID_COMP_SANDCRAFT:
582 cpu_probe_sandcraft(c);
583 break;
584 default:
585 c->cputype = CPU_UNKNOWN;
586 }
587 if (c->options & MIPS_CPU_FPU)
588 c->fpu_id = cpu_get_fpu_id();
589}
590
591__init void cpu_report(void)
592{
593 struct cpuinfo_mips *c = &current_cpu_data;
594
595 printk("CPU revision is: %08x\n", c->processor_id);
596 if (c->options & MIPS_CPU_FPU)
597 printk("FPU revision is: %08x\n", c->fpu_id);
598}
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