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authorThomas Gleixner <tglx@linutronix.de>2011-03-23 17:08:53 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-03-25 13:45:16 -0400
commit42b64f388c171a7a1a8962d93d9bae2c04da7738 (patch)
tree9a5633124bc37814f09e5c60f3a14012fbe1583c /arch/mips/jz4740/irq.c
parentdb00bed4baa8951b579519e90d8d7f215db2827a (diff)
MIPS: JZ4740: Convert to new irq functions
Convert the JZ4740 intc and gpio irq chips to use newstyle irq functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2181/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/jz4740/irq.c')
-rw-r--r--arch/mips/jz4740/irq.c32
1 files changed, 20 insertions, 12 deletions
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index 7d33ff83580f..dcc5593a9389 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -43,32 +43,37 @@ static uint32_t jz_intc_saved;
43 43
44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE) 44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
45 45
46static void intc_irq_unmask(unsigned int irq) 46static inline unsigned long intc_irq_bit(struct irq_data *data)
47{ 47{
48 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK); 48 return (unsigned long)irq_data_get_irq_chip_data(data);
49} 49}
50 50
51static void intc_irq_mask(unsigned int irq) 51static void intc_irq_unmask(struct irq_data *data)
52{ 52{
53 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK); 53 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
54} 54}
55 55
56static int intc_irq_set_wake(unsigned int irq, unsigned int on) 56static void intc_irq_mask(struct irq_data *data)
57{
58 writel(intc_irq_bit(data), jz_intc_base + JZ_REG_INTC_SET_MASK);
59}
60
61static int intc_irq_set_wake(struct irq_data *data, unsigned int on)
57{ 62{
58 if (on) 63 if (on)
59 jz_intc_wakeup |= IRQ_BIT(irq); 64 jz_intc_wakeup |= intc_irq_bit(data);
60 else 65 else
61 jz_intc_wakeup &= ~IRQ_BIT(irq); 66 jz_intc_wakeup &= ~intc_irq_bit(data);
62 67
63 return 0; 68 return 0;
64} 69}
65 70
66static struct irq_chip intc_irq_type = { 71static struct irq_chip intc_irq_type = {
67 .name = "INTC", 72 .name = "INTC",
68 .mask = intc_irq_mask, 73 .irq_mask = intc_irq_mask,
69 .mask_ack = intc_irq_mask, 74 .irq_mask_ack = intc_irq_mask,
70 .unmask = intc_irq_unmask, 75 .irq_unmask = intc_irq_unmask,
71 .set_wake = intc_irq_set_wake, 76 .irq_set_wake = intc_irq_set_wake,
72}; 77};
73 78
74static irqreturn_t jz4740_cascade(int irq, void *data) 79static irqreturn_t jz4740_cascade(int irq, void *data)
@@ -95,8 +100,11 @@ void __init arch_init_irq(void)
95 100
96 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); 101 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
97 102
103 /* Mask all irqs */
104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105
98 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { 106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
99 intc_irq_mask(i); 107 set_irq_chip_data(i, (void *)IRQ_BIT(i));
100 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); 108 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
101 } 109 }
102 110