[MIPS] Rewrite all the assembler interrupt handlers to C.

Saves like 1,600 lines of code, is way easier to debug, compilers
frequently do a better job than the cut and paste type of handlers many
boards had.  And finally having all the stuff done in a single place
also means alot of bug potencial for the MT ASE is gone.

The only surviving handler in assembler is the DECstation one; I hope
Maciej will rewrite it.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 13 insertions, 67 deletions

diff --git a/arch/mips/ite-boards/generic/Makefile b/arch/mips/ite-boards/generic/Makefile
index 0e7853f43983..63431538d0ec 100644
--- a/arch/mips/ite-boards/generic/Makefile
+++ b/arch/mips/ite-boards/generic/Makefile
@@ -6,7 +6,7 @@
 # Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
 #
 
-obj-y                   += it8172_setup.o irq.o int-handler.o pmon_prom.o \
+obj-y                   += it8172_setup.o irq.o pmon_prom.o \
                            time.o lpc.o puts.o reset.o
 
 obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
diff --git a/arch/mips/ite-boards/generic/int-handler.S b/arch/mips/ite-boards/generic/int-handler.S
deleted file mode 100644
index d190d8add9cb..000000000000
--- a/arch/mips/ite-boards/generic/int-handler.S
+++ /dev/null
@@ -1,63 +0,0 @@
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-
-        .text
-        .set    macro
-        .set    noat
-        .align  5
-
-NESTED(it8172_IRQ, PT_SIZE, sp)
-        SAVE_ALL
-        CLI                             # Important: mark KERNEL mode !
-
-        /* We're working with 'reorder' set at this point. */
-        /*
-         * Get pending interrupts
-         */
-
-        mfc0    t0,CP0_CAUSE            # get pending interrupts
-        mfc0    t1,CP0_STATUS           # get enabled interrupts
-        and     t0,t1                   # isolate allowed ones
-
-        andi    t0,0xff00               # isolate pending bits
-        beqz    t0, 3f                  # spurious interrupt
-
-        andi    a0, t0, CAUSEF_IP7
-        beq     a0, zero, 1f
-
-        li      a0, 127                 # MIPS_CPU_TIMER_IRQ = (NR_IRQS-1)
-        move    a1, sp
-        jal     ll_timer_interrupt
-        j       ret_from_irq
-        nop
-
-1:
-        andi    a0, t0, CAUSEF_IP2      # the only int we expect at this time
-        beq     a0, zero, 3f
-        move    a0,sp
-        jal     it8172_hw0_irqdispatch
-
-        mfc0    t0,CP0_STATUS           # disable interrupts
-        ori     t0,1
-        xori    t0,1
-        mtc0    t0,CP0_STATUS
-        nop
-        nop
-        nop
-
-        la      a1, ret_from_irq
-        jr      a1
-        nop
-
-3:
-        move a0, sp
-        jal     mips_spurious_interrupt
-        nop
-        la      a1, ret_from_irq
-        jr      a1
-        nop
-
-END(it8172_IRQ)
-
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
index 8c1cdfcd4284..77be7216bdd0 100644
--- a/arch/mips/ite-boards/generic/irq.c
+++ b/arch/mips/ite-boards/generic/irq.c
@@ -64,7 +64,6 @@
 
 extern void set_debug_traps(void);
 extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
-extern asmlinkage void it8172_IRQ(void);
 
 struct it8172_intc_regs volatile *it8172_hw0_icregs =
         (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
@@ -178,8 +177,6 @@ void __init arch_init_irq(void)
         int i;
         unsigned long flags;
 
-        set_except_vector(0, it8172_IRQ);
-
         /* mask all interrupts */
         it8172_hw0_icregs->lb_mask  = 0xffff;
         it8172_hw0_icregs->lpc_mask = 0xffff;
@@ -279,6 +276,18 @@ void it8172_hw0_irqdispatch(struct pt_regs *regs)
         do_IRQ(irq, regs);
 }
 
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+        if (!pending)
+                mips_spurious_interrupt(regs);
+        else if (pending & CAUSEF_IP7)
+                ll_timer_interrupt(127, regs);
+        else if (pending & CAUSEF_IP2)
+                it8172_hw0_irqdispatch(regs);
+}
+
 void show_pending_irqs(void)
 {
         fputs("intstatus:  ");