MIPS: Emulate the BC1{EQ,NE}Z FPU instructions

MIPS R6 introduced the following two branch instructions for COP1:

BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 5c9e14a903af..19d3bc1e6510 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -115,7 +115,8 @@ enum cop_op {
         mfhc_op       = 0x03, mtc_op        = 0x04,
         dmtc_op       = 0x05, ctc_op        = 0x06,
         mthc0_op      = 0x06, mthc_op       = 0x07,
-        bc_op         = 0x08, cop_op        = 0x10,
+        bc_op         = 0x08, bc1eqz_op     = 0x09,
+        bc1nez_op     = 0x0d, cop_op        = 0x10,
         copm_op       = 0x18
 };