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authorDavid Daney <ddaney@caviumnetworks.com>2010-12-27 21:07:56 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-01-18 13:30:23 -0500
commitbb3d68c30a00918d4c9fa02a5c17a5aacf597977 (patch)
tree6d6db066452de4a2ec28f24bc7b0c287eabd9967 /arch/mips/include
parentcc33ae437975416a1b78f99e2715e91ab643526a (diff)
MIPS: Add LDX and LWX instructions to uasm.
Needed by Octeon II optimized TLB handlers. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Pachwork: https://patchwork.linux-mips.org/patch/1903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/inst.h14
-rw-r--r--arch/mips/include/asm/uasm.h4
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 444ff71aa0e8..7ebfc392e58d 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -72,6 +72,7 @@ enum spec2_op {
72enum spec3_op { 72enum spec3_op {
73 ext_op, dextm_op, dextu_op, dext_op, 73 ext_op, dextm_op, dextu_op, dext_op,
74 ins_op, dinsm_op, dinsu_op, dins_op, 74 ins_op, dinsm_op, dinsu_op, dins_op,
75 lx_op = 0x0a,
75 bshfl_op = 0x20, 76 bshfl_op = 0x20,
76 dbshfl_op = 0x24, 77 dbshfl_op = 0x24,
77 rdhwr_op = 0x3b 78 rdhwr_op = 0x3b
@@ -179,6 +180,19 @@ enum mad_func {
179}; 180};
180 181
181/* 182/*
183 * func field for special3 lx opcodes (Cavium Octeon).
184 */
185enum lx_func {
186 lwx_op = 0x00,
187 lhx_op = 0x04,
188 lbux_op = 0x06,
189 ldx_op = 0x08,
190 lwux_op = 0x10,
191 lhux_op = 0x14,
192 lbx_op = 0x16,
193};
194
195/*
182 * Damn ... bitfields depend from byteorder :-( 196 * Damn ... bitfields depend from byteorder :-(
183 */ 197 */
184#ifdef __MIPSEB__ 198#ifdef __MIPSEB__
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index d361df32eef8..dcbd4bb417ec 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -119,6 +119,8 @@ Ip_u2u1msbu3(_dinsm);
119Ip_u1(_syscall); 119Ip_u1(_syscall);
120Ip_u1u2s3(_bbit0); 120Ip_u1u2s3(_bbit0);
121Ip_u1u2s3(_bbit1); 121Ip_u1u2s3(_bbit1);
122Ip_u3u1u2(_lwx);
123Ip_u3u1u2(_ldx);
122 124
123/* Handle labels. */ 125/* Handle labels. */
124struct uasm_label { 126struct uasm_label {
@@ -156,6 +158,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
156# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd) 158# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
157# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) 159# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
158# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off) 160# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
161# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
159#else 162#else
160# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) 163# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
161# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) 164# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
@@ -170,6 +173,7 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
170# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd) 173# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
171# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) 174# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
172# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off) 175# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
176# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
173#endif 177#endif
174 178
175#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off) 179#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)