diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2011-06-20 15:26:10 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-07 17:02:46 -0500 |
commit | c279b7759602d4ef97d45f3eb2cdf36a713eb99a (patch) | |
tree | 1c399f392565472b4726cc29b71e4d770266d00c /arch/mips/include | |
parent | 9d6b204f93cfeb7ec5e6ec499aca43d2c1d6da3f (diff) |
MIPS: ath79: add AR933X specific USB platform device registration
Also select the USB_ARCH_HAS_EHCI symbol in order to make the
EHCI driver available.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Kathy Giori <kgiori@qca.qualcomm.com>
Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
Patchwork: https://patchwork.linux-mips.org/patch/2527/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r-- | arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h index e65c10dd159b..733bacace778 100644 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h | |||
@@ -56,6 +56,9 @@ | |||
56 | #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) | 56 | #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) |
57 | #define AR933X_UART_SIZE 0x14 | 57 | #define AR933X_UART_SIZE 0x14 |
58 | 58 | ||
59 | #define AR933X_EHCI_BASE 0x1b000000 | ||
60 | #define AR933X_EHCI_SIZE 0x1000 | ||
61 | |||
59 | /* | 62 | /* |
60 | * DDR_CTRL block | 63 | * DDR_CTRL block |
61 | */ | 64 | */ |
@@ -230,6 +233,10 @@ | |||
230 | #define AR913X_RESET_USB_HOST BIT(5) | 233 | #define AR913X_RESET_USB_HOST BIT(5) |
231 | #define AR913X_RESET_USB_PHY BIT(4) | 234 | #define AR913X_RESET_USB_PHY BIT(4) |
232 | 235 | ||
236 | #define AR933X_RESET_USB_HOST BIT(5) | ||
237 | #define AR933X_RESET_USB_PHY BIT(4) | ||
238 | #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) | ||
239 | |||
233 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) | 240 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
234 | 241 | ||
235 | #define REV_ID_MAJOR_MASK 0xfff0 | 242 | #define REV_ID_MAJOR_MASK 0xfff0 |