MIPS: Alchemy: irq code and constant cleanup

replace au_readl/au_writel with __raw_readl/__raw_writel,
and clean up IC-related stuff from the headers.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Patchwork: https://patchwork.linux-mips.org/patch/2354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 5 insertions, 116 deletions

diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index a6976619160a..66cfcdc75e4f 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -630,8 +630,13 @@ enum soc_au1200_ints {
 
 /*
  * Physical base addresses for integrated peripherals
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
  */
 
+#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
+
+
 #ifdef CONFIG_SOC_AU1000
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
@@ -643,8 +648,6 @@ enum soc_au1200_ints {
 #define DMA5_PHYS_ADDR          0x14002500
 #define DMA6_PHYS_ADDR          0x14002600
 #define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
 #define USBD_PHYS_ADDR          0x10200000
@@ -680,8 +683,6 @@ enum soc_au1200_ints {
 #define DMA5_PHYS_ADDR          0x14002500
 #define DMA6_PHYS_ADDR          0x14002600
 #define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
 #define USBD_PHYS_ADDR          0x10200000
@@ -718,10 +719,8 @@ enum soc_au1200_ints {
 #define DMA5_PHYS_ADDR          0x14002500
 #define DMA6_PHYS_ADDR          0x14002600
 #define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
 #define SD0_PHYS_ADDR           0x10600000
 #define SD1_PHYS_ADDR           0x10680000
-#define IC1_PHYS_ADDR           0x11800000
 #define AC97_PHYS_ADDR          0x10000000
 #define USBH_PHYS_ADDR          0x10100000
 #define USBD_PHYS_ADDR          0x10200000
@@ -749,8 +748,6 @@ enum soc_au1200_ints {
 #ifdef CONFIG_SOC_AU1550
 #define MEM_PHYS_ADDR           0x14000000
 #define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBH_PHYS_ADDR          0x14020000
 #define USBD_PHYS_ADDR          0x10200000
 #define PCI_PHYS_ADDR           0x14005000
@@ -786,8 +783,6 @@ enum soc_au1200_ints {
 #define STATIC_MEM_PHYS_ADDR    0x14001000
 #define AES_PHYS_ADDR           0x10300000
 #define CIM_PHYS_ADDR           0x14004000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
 #define USBM_PHYS_ADDR          0x14020000
 #define USBH_PHYS_ADDR          0x14020100
 #define UART0_PHYS_ADDR         0x11100000
@@ -835,112 +830,6 @@ enum soc_au1200_ints {
 #endif
 
 
-/* Interrupt Controller register offsets */
-#define IC_CFG0RD               0x40
-#define IC_CFG0SET              0x40
-#define IC_CFG0CLR              0x44
-#define IC_CFG1RD               0x48
-#define IC_CFG1SET              0x48
-#define IC_CFG1CLR              0x4C
-#define IC_CFG2RD               0x50
-#define IC_CFG2SET              0x50
-#define IC_CFG2CLR              0x54
-#define IC_REQ0INT              0x54
-#define IC_SRCRD                0x58
-#define IC_SRCSET               0x58
-#define IC_SRCCLR               0x5C
-#define IC_REQ1INT              0x5C
-#define IC_ASSIGNRD             0x60
-#define IC_ASSIGNSET            0x60
-#define IC_ASSIGNCLR            0x64
-#define IC_WAKERD               0x68
-#define IC_WAKESET              0x68
-#define IC_WAKECLR              0x6C
-#define IC_MASKRD               0x70
-#define IC_MASKSET              0x70
-#define IC_MASKCLR              0x74
-#define IC_RISINGRD             0x78
-#define IC_RISINGCLR            0x78
-#define IC_FALLINGRD            0x7C
-#define IC_FALLINGCLR           0x7C
-#define IC_TESTBIT              0x80
-
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD              0xB0400040
-#define IC0_CFG0SET             0xB0400040
-#define IC0_CFG0CLR             0xB0400044
-
-#define IC0_CFG1RD              0xB0400048
-#define IC0_CFG1SET             0xB0400048
-#define IC0_CFG1CLR             0xB040004C
-
-#define IC0_CFG2RD              0xB0400050
-#define IC0_CFG2SET             0xB0400050
-#define IC0_CFG2CLR             0xB0400054
-
-#define IC0_REQ0INT             0xB0400054
-#define IC0_SRCRD               0xB0400058
-#define IC0_SRCSET              0xB0400058
-#define IC0_SRCCLR              0xB040005C
-#define IC0_REQ1INT             0xB040005C
-
-#define IC0_ASSIGNRD            0xB0400060
-#define IC0_ASSIGNSET           0xB0400060
-#define IC0_ASSIGNCLR           0xB0400064
-
-#define IC0_WAKERD              0xB0400068
-#define IC0_WAKESET             0xB0400068
-#define IC0_WAKECLR             0xB040006C
-
-#define IC0_MASKRD              0xB0400070
-#define IC0_MASKSET             0xB0400070
-#define IC0_MASKCLR             0xB0400074
-
-#define IC0_RISINGRD            0xB0400078
-#define IC0_RISINGCLR           0xB0400078
-#define IC0_FALLINGRD           0xB040007C
-#define IC0_FALLINGCLR          0xB040007C
-
-#define IC0_TESTBIT             0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD              0xB1800040
-#define IC1_CFG0SET             0xB1800040
-#define IC1_CFG0CLR             0xB1800044
-
-#define IC1_CFG1RD              0xB1800048
-#define IC1_CFG1SET             0xB1800048
-#define IC1_CFG1CLR             0xB180004C
-
-#define IC1_CFG2RD              0xB1800050
-#define IC1_CFG2SET             0xB1800050
-#define IC1_CFG2CLR             0xB1800054
-
-#define IC1_REQ0INT             0xB1800054
-#define IC1_SRCRD               0xB1800058
-#define IC1_SRCSET              0xB1800058
-#define IC1_SRCCLR              0xB180005C
-#define IC1_REQ1INT             0xB180005C
-
-#define IC1_ASSIGNRD            0xB1800060
-#define IC1_ASSIGNSET           0xB1800060
-#define IC1_ASSIGNCLR           0xB1800064
-
-#define IC1_WAKERD              0xB1800068
-#define IC1_WAKESET             0xB1800068
-#define IC1_WAKECLR             0xB180006C
-
-#define IC1_MASKRD              0xB1800070
-#define IC1_MASKSET             0xB1800070
-#define IC1_MASKCLR             0xB1800074
-
-#define IC1_RISINGRD            0xB1800078
-#define IC1_RISINGCLR           0xB1800078
-#define IC1_FALLINGRD           0xB180007C
-#define IC1_FALLINGCLR          0xB180007C
-
-#define IC1_TESTBIT             0xB1800080
 
 
 /* Au1000 */