MIPS: Lantiq: Add PCI controller support.

The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds
the driver that allows us to use the EBU as a PCI controller. In order for
PCI to work the EBU is set to endianess swap all the data. In addition we
need to make use of SWAP_IO_SPACE for device->host DMA to work.

The clock of the PCI works in several modes (internal/external). If this
is not configured correctly the SoC will hang.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2250/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 46 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
new file mode 100644
index 000000000000..1f1dba6d0736
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -0,0 +1,46 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_PLATFORM_H__
+#define _LANTIQ_PLATFORM_H__
+
+#include <linux/mtd/partitions.h>
+
+/* struct used to pass info to the pci core */
+enum {
+        PCI_CLOCK_INT = 0,
+        PCI_CLOCK_EXT
+};
+
+#define PCI_EXIN0       0x0001
+#define PCI_EXIN1       0x0002
+#define PCI_EXIN2       0x0004
+#define PCI_EXIN3       0x0008
+#define PCI_EXIN4       0x0010
+#define PCI_EXIN5       0x0020
+#define PCI_EXIN_MAX    6
+
+#define PCI_GNT1        0x0040
+#define PCI_GNT2        0x0080
+#define PCI_GNT3        0x0100
+#define PCI_GNT4        0x0200
+
+#define PCI_REQ1        0x0400
+#define PCI_REQ2        0x0800
+#define PCI_REQ3        0x1000
+#define PCI_REQ4        0x2000
+#define PCI_REQ_SHIFT   10
+#define PCI_REQ_MASK    0xf
+
+struct ltq_pci_data {
+        int clock;
+        int gpio;
+        int irq[16];
+};
+
+#endif