diff options
author | Shane McDonald <mcdonald.shane@gmail.com> | 2010-05-07 01:26:57 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-05-15 16:59:53 -0400 |
commit | 95e8f634d7a3ea5af40ec3fa42c8a152fd3a0624 (patch) | |
tree | 67da92dd5fa7fc27ebd25a9b524166ef182793ae /arch/mips/include | |
parent | 3f8bf8f0fd79410fbcbf9dd9910dbc9d4882c94f (diff) |
MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
are not currently writeable by the ctc1 instruction. In odd corner cases,
this can cause problems. For example, a case existed where a divide-by-zero
exception was generated by the FPU, and the signal handler attempted to
restore the FPU registers to their state before the exception occurred. In
this particular setup, writing the old value to the FCSR register would
cause another divide-by-zero exception to occur immediately. The solution
is to change the ctc1 instruction emulator code to allow the Cause bits of
the FCSR register to be writeable. This is the behaviour of the hardware
that the code is emulating.
This problem was found by Shane McDonald, but the credit for the fix goes
to Kevin Kissell. In Kevin's words:
I submit that the bug is indeed in that ctc_op: case of the emulator. The
Cause bits (17:12) are supposed to be writable by that instruction, but the
CTC1 emulation won't let them be updated by the instruction. I think that
actually if you just completely removed lines 387-388 [...] things would
work a good deal better. At least, it would be a more accurate emulation of
the architecturally defined FPU. If I wanted to be really, really pedantic
(which I sometimes do), I'd also protect the reserved bits that aren't
necessarily writable.
Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
To: anemo@mba.ocn.ne.jp
To: kevink@paralogos.com
To: sshtylyov@mvista.com
Patchwork: http://patchwork.linux-mips.org/patch/1205/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Diffstat (limited to 'arch/mips/include')
-rw-r--r-- | arch/mips/include/asm/mipsregs.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 49382d5e891a..c6e3c93ce7c7 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
@@ -135,6 +135,12 @@ | |||
135 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ | 135 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ |
136 | 136 | ||
137 | /* | 137 | /* |
138 | * Bits 18 - 20 of the FPU Status Register will be read as 0, | ||
139 | * and should be written as zero. | ||
140 | */ | ||
141 | #define FPU_CSR_RSVD 0x001c0000 | ||
142 | |||
143 | /* | ||
138 | * X the exception cause indicator | 144 | * X the exception cause indicator |
139 | * E the exception enable | 145 | * E the exception enable |
140 | * S the sticky/flag bit | 146 | * S the sticky/flag bit |
@@ -161,7 +167,8 @@ | |||
161 | #define FPU_CSR_UDF_S 0x00000008 | 167 | #define FPU_CSR_UDF_S 0x00000008 |
162 | #define FPU_CSR_INE_S 0x00000004 | 168 | #define FPU_CSR_INE_S 0x00000004 |
163 | 169 | ||
164 | /* rounding mode */ | 170 | /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ |
171 | #define FPU_CSR_RM 0x00000003 | ||
165 | #define FPU_CSR_RN 0x0 /* nearest */ | 172 | #define FPU_CSR_RN 0x0 /* nearest */ |
166 | #define FPU_CSR_RZ 0x1 /* towards zero */ | 173 | #define FPU_CSR_RZ 0x1 /* towards zero */ |
167 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ | 174 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ |