MIPS: ralink: adds support for RT2880 SoC family

Add support code for rt2880 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5176/

1 files changed, 49 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
new file mode 100644
index 000000000000..ad8b42dd2fcc
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -0,0 +1,49 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _RT288X_REGS_H_
+#define _RT288X_REGS_H_
+
+#define RT2880_SYSC_BASE                0x00300000
+
+#define SYSC_REG_CHIP_NAME0             0x00
+#define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_CHIP_ID                0x0c
+#define SYSC_REG_SYSTEM_CONFIG          0x10
+#define SYSC_REG_CLKCFG                 0x30
+
+#define RT2880_CHIP_NAME0               0x38325452
+#define RT2880_CHIP_NAME1               0x20203038
+
+#define CHIP_ID_ID_MASK                 0xff
+#define CHIP_ID_ID_SHIFT                8
+#define CHIP_ID_REV_MASK                0xff
+
+#define SYSTEM_CONFIG_CPUCLK_SHIFT      20
+#define SYSTEM_CONFIG_CPUCLK_MASK       0x3
+#define SYSTEM_CONFIG_CPUCLK_250        0x0
+#define SYSTEM_CONFIG_CPUCLK_266        0x1
+#define SYSTEM_CONFIG_CPUCLK_280        0x2
+#define SYSTEM_CONFIG_CPUCLK_300        0x3
+
+#define RT2880_GPIO_MODE_I2C            BIT(0)
+#define RT2880_GPIO_MODE_UART0          BIT(1)
+#define RT2880_GPIO_MODE_SPI            BIT(2)
+#define RT2880_GPIO_MODE_UART1          BIT(3)
+#define RT2880_GPIO_MODE_JTAG           BIT(4)
+#define RT2880_GPIO_MODE_MDIO           BIT(5)
+#define RT2880_GPIO_MODE_SDRAM          BIT(6)
+#define RT2880_GPIO_MODE_PCI            BIT(7)
+
+#define CLKCFG_SRAM_CS_N_WDT            BIT(9)
+
+#endif