MIPS: Alchemy: more base address cleanup

remove all redundant peripheral base address defines, fix
all affected boards and drivers.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

5 files changed, 37 insertions, 116 deletions

diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 7f610b370382..1bbcb30c4ab9 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -698,114 +698,61 @@ enum soc_au1200_ints {
 #define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
 #define AU1000_USB_OHCI_PHYS_ADDR       0x10100000 /* 012 */
 #define AU1000_USB_UDC_PHYS_ADDR        0x10200000 /* 0123 */
+#define AU1000_IRDA_PHYS_ADDR           0x10300000 /* 02 */
+#define AU1200_AES_PHYS_ADDR            0x10300000 /* 4 */
 #define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
 #define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
 #define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
 #define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
 #define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
 #define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1550_PSC2_PHYS_ADDR           0x10A00000 /* 3 */
+#define AU1550_PSC3_PHYS_ADDR           0x10B00000 /* 3 */
 #define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
 #define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
 #define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
 #define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
 #define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
+#define AU1200_SWCNT_PHYS_ADDR          0x1110010C /* 4 */
 #define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
 #define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
 #define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
+#define AU1000_SSI0_PHYS_ADDR           0x11600000 /* 02 */
+#define AU1000_SSI1_PHYS_ADDR           0x11680000 /* 02 */
 #define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
 #define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
 #define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1550_PSC0_PHYS_ADDR           0x11A00000 /* 34 */
+#define AU1550_PSC1_PHYS_ADDR           0x11B00000 /* 34 */
+#define AU1000_MEM_PHYS_ADDR            0x14000000 /* 01234 */
+#define AU1000_STATIC_MEM_PHYS_ADDR     0x14001000 /* 01234 */
 #define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
 #define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
 #define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
 #define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
 #define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
+#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 4 */
+#define AU1500_PCI_PHYS_ADDR            0x14005000 /* 13 */
+#define AU1550_PE_PHYS_ADDR             0x14008000 /* 3 */
+#define AU1200_MAEBE_PHYS_ADDR          0x14010000 /* 4 */
+#define AU1200_MAEFE_PHYS_ADDR          0x14012000 /* 4 */
 #define AU1550_USB_OHCI_PHYS_ADDR       0x14020000 /* 3 */
 #define AU1200_USB_CTL_PHYS_ADDR        0x14020000 /* 4 */
 #define AU1200_USB_OTG_PHYS_ADDR        0x14020020 /* 4 */
 #define AU1200_USB_OHCI_PHYS_ADDR       0x14020100 /* 4 */
 #define AU1200_USB_EHCI_PHYS_ADDR       0x14020200 /* 4 */
 #define AU1200_USB_UDC_PHYS_ADDR        0x14022000 /* 4 */
+#define AU1100_LCD_PHYS_ADDR            0x15000000 /* 2 */
+#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 4 */
+#define AU1500_PCI_MEM_PHYS_ADDR        0x400000000ULL /* 13 */
+#define AU1500_PCI_IO_PHYS_ADDR         0x500000000ULL /* 13 */
+#define AU1500_PCI_CONFIG0_PHYS_ADDR    0x600000000ULL /* 13 */
+#define AU1500_PCI_CONFIG1_PHYS_ADDR    0x680000000ULL /* 13 */
+#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 01234 */
+#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 01234 */
+#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 01234 */
 
 
-#ifdef CONFIG_SOC_AU1000
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IRDA_PHYS_ADDR          0x10300000
-#define SSI0_PHYS_ADDR          0x11600000
-#define SSI1_PHYS_ADDR          0x11680000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1500
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define PCI_PHYS_ADDR           0x14005000
-#define PCI_MEM_PHYS_ADDR       0x400000000ULL
-#define PCI_IO_PHYS_ADDR        0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1100
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IRDA_PHYS_ADDR          0x10300000
-#define SSI0_PHYS_ADDR          0x11600000
-#define SSI1_PHYS_ADDR          0x11680000
-#define LCD_PHYS_ADDR           0x15000000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1550
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define PCI_PHYS_ADDR           0x14005000
-#define PE_PHYS_ADDR            0x14008000
-#define PSC0_PHYS_ADDR          0x11A00000
-#define PSC1_PHYS_ADDR          0x11B00000
-#define PSC2_PHYS_ADDR          0x10A00000
-#define PSC3_PHYS_ADDR          0x10B00000
-#define PCI_MEM_PHYS_ADDR       0x400000000ULL
-#define PCI_IO_PHYS_ADDR        0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1200
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define AES_PHYS_ADDR           0x10300000
-#define CIM_PHYS_ADDR           0x14004000
-#define PSC0_PHYS_ADDR          0x11A00000
-#define PSC1_PHYS_ADDR          0x11B00000
-#define LCD_PHYS_ADDR           0x15000000
-#define SWCNT_PHYS_ADDR         0x1110010C
-#define MAEFE_PHYS_ADDR         0x14012000
-#define MAEBE_PHYS_ADDR         0x14010000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
 /* Static Bus Controller */
 #define MEM_STCFG0              0xB4001000
 #define MEM_STTIME0             0xB4001004
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f168eb4..8e2fa674be4a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -33,19 +33,6 @@
 #ifndef _AU1000_PSC_H_
 #define _AU1000_PSC_H_
 
-/* The PSC base addresses.  */
-#ifdef CONFIG_SOC_AU1550
-#define PSC0_BASE_ADDR          0xb1a00000
-#define PSC1_BASE_ADDR          0xb1b00000
-#define PSC2_BASE_ADDR          0xb0a00000
-#define PSC3_BASE_ADDR          0xb0b00000
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#define PSC0_BASE_ADDR          0xb1a00000
-#define PSC1_BASE_ADDR          0xb1b00000
-#endif
-
 /*
  * The PSC select and control registers are common to all protocols.
  */
@@ -80,19 +67,6 @@
 #define PSC_AC97GPO_OFFSET      0x00000028
 #define PSC_AC97GPI_OFFSET      0x0000002c
 
-#define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
-#define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
-#define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
-#define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
-#define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
-#define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
-#define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
-#define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
-#define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
-#define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
-#define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
-#define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-
 /* AC97 Config Register. */
 #define PSC_AC97CFG_RT_MASK     (3 << 30)
 #define PSC_AC97CFG_RT_FIFO1    (0 << 30)
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index a919dac525a1..115cc7c44402 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -36,10 +36,10 @@
 #define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
 #define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
 
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
-#define I2S_PSC_BASE            PSC3_BASE_ADDR
+#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
+#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
+#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
+#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
 
 #define NAND_PHYS_ADDR          0x20000000
 
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index fce4332ebb7f..0ecff1cb695a 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -37,14 +37,14 @@
  * SPI and SMB are muxed on the Pb1200 board.
  * Refer to board documentation.
  */
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
+#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
+#define SMBUS_PSC_BASE          AU1550_PSC0_PHYS_ADDR
 /*
  * AC97 and I2S are muxed on the Pb1200 board.
  * Refer to board documentation.
  */
-#define AC97_PSC_BASE       PSC1_BASE_ADDR
-#define I2S_PSC_BASE    PSC1_BASE_ADDR
+#define AC97_PSC_BASE       AU1550_PSC1_PHYS_ADDR
+#define I2S_PSC_BASE    AU1550_PSC1_PHYS_ADDR
 
 
 #define BCSR_SYSTEM_VDDI        0x001F
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index f835c88e9593..0b0f462e4bfb 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -35,10 +35,10 @@
 #define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
 #define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
 
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
-#define I2S_PSC_BASE            PSC3_BASE_ADDR
+#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
+#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
+#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
+#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
 
 /*
  * Timing values as described in databook, * ns value stripped of