diff options
author | Manuel Lauss <manuel.lauss@googlemail.com> | 2009-11-02 15:21:43 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:00 -0500 |
commit | 63323ec54a7e922a232c82070727e44eb1a5b43c (patch) | |
tree | 4f78c66c8db7fdaded28a3eaf76f196bd1c59753 /arch/mips/include | |
parent | 206aa6cdadad8bbedee5649f1346fe47e922a039 (diff) |
MIPS: Alchemy: Extended DB1200 board support.
Create own directory for DB1200 code and update it with new features.
- SPI support:
- tmp121 temperature sensor
- SPI flash on DB1200
- I2C support
- NE1619 sensor
- AT24 eeprom
- I2C/SPI can be selected at boot time via switch S6.8
- Carddetect IRQs for SD cards.
- gen_nand based NAND support.
- hexleds count sleep/wake transitions.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r-- | arch/mips/include/asm/mach-db1x00/db1200.h | 33 |
1 files changed, 5 insertions, 28 deletions
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 52b1d84a92c7..3404248f5094 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h | |||
@@ -28,24 +28,6 @@ | |||
28 | #include <asm/mach-au1x00/au1000.h> | 28 | #include <asm/mach-au1x00/au1000.h> |
29 | #include <asm/mach-au1x00/au1xxx_psc.h> | 29 | #include <asm/mach-au1x00/au1xxx_psc.h> |
30 | 30 | ||
31 | #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX | ||
32 | #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX | ||
33 | #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX | ||
34 | #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX | ||
35 | |||
36 | /* | ||
37 | * SPI and SMB are muxed on the DBAu1200 board. | ||
38 | * Refer to board documentation. | ||
39 | */ | ||
40 | #define SPI_PSC_BASE PSC0_BASE_ADDR | ||
41 | #define SMBUS_PSC_BASE PSC0_BASE_ADDR | ||
42 | /* | ||
43 | * AC'97 and I2S are muxed on the DBAu1200 board. | ||
44 | * Refer to board documentation. | ||
45 | */ | ||
46 | #define AC97_PSC_BASE PSC1_BASE_ADDR | ||
47 | #define I2S_PSC_BASE PSC1_BASE_ADDR | ||
48 | |||
49 | /* Bit positions for the different interrupt sources */ | 31 | /* Bit positions for the different interrupt sources */ |
50 | #define BCSR_INT_IDE 0x0001 | 32 | #define BCSR_INT_IDE 0x0001 |
51 | #define BCSR_INT_ETH 0x0002 | 33 | #define BCSR_INT_ETH 0x0002 |
@@ -62,17 +44,15 @@ | |||
62 | #define BCSR_INT_SD0INSERT 0x1000 | 44 | #define BCSR_INT_SD0INSERT 0x1000 |
63 | #define BCSR_INT_SD0EJECT 0x2000 | 45 | #define BCSR_INT_SD0EJECT 0x2000 |
64 | 46 | ||
65 | #define SMC91C111_PHYS_ADDR 0x19000300 | ||
66 | #define SMC91C111_INT DB1200_ETH_INT | ||
67 | |||
68 | #define IDE_PHYS_ADDR 0x18800000 | 47 | #define IDE_PHYS_ADDR 0x18800000 |
69 | #define IDE_REG_SHIFT 5 | 48 | #define IDE_REG_SHIFT 5 |
70 | #define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) | ||
71 | #define IDE_INT DB1200_IDE_INT | ||
72 | #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 | 49 | #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 |
73 | #define IDE_RQSIZE 128 | 50 | #define IDE_RQSIZE 128 |
74 | 51 | ||
75 | #define NAND_PHYS_ADDR 0x20000000 | 52 | #define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR |
53 | #define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) | ||
54 | #define DB1200_ETH_PHYS_ADDR 0x19000300 | ||
55 | #define DB1200_NAND_PHYS_ADDR 0x20000000 | ||
76 | 56 | ||
77 | /* | 57 | /* |
78 | * External Interrupts for DBAu1200 as of 8/6/2004. | 58 | * External Interrupts for DBAu1200 as of 8/6/2004. |
@@ -82,7 +62,7 @@ | |||
82 | * Example: IDE bis pos is = 64 - 64 | 62 | * Example: IDE bis pos is = 64 - 64 |
83 | * ETH bit pos is = 65 - 64 | 63 | * ETH bit pos is = 65 - 64 |
84 | */ | 64 | */ |
85 | enum external_pb1200_ints { | 65 | enum external_db1200_ints { |
86 | DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, | 66 | DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, |
87 | 67 | ||
88 | DB1200_IDE_INT = DB1200_INT_BEGIN, | 68 | DB1200_IDE_INT = DB1200_INT_BEGIN, |
@@ -103,7 +83,4 @@ enum external_pb1200_ints { | |||
103 | DB1200_INT_END = DB1200_INT_BEGIN + 15, | 83 | DB1200_INT_END = DB1200_INT_BEGIN + 15, |
104 | }; | 84 | }; |
105 | 85 | ||
106 | /* NAND chip select */ | ||
107 | #define NAND_CS 1 | ||
108 | |||
109 | #endif /* __ASM_DB1200_H */ | 86 | #endif /* __ASM_DB1200_H */ |