diff options
author | David Daney <ddaney@caviumnetworks.com> | 2010-02-10 18:12:46 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:25 -0500 |
commit | 32546f38fab839eee6f62b3f06c2774eade4188a (patch) | |
tree | 582cb9fb18c8e741d24a4a27d9c2dee46bfd977f /arch/mips/include | |
parent | 9fe2e9d6f5390d7151a0b9d8c100f0da26eaa2b7 (diff) |
MIPS: Add TLBR and ROTR to uasm.
The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and
ROTR support in uasm. We also add a UASM_i_ROTR macro.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/953/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r-- | arch/mips/include/asm/uasm.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3d153edaa51e..b99bd07e199b 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h | |||
@@ -92,9 +92,11 @@ Ip_u2s3u1(_sd); | |||
92 | Ip_u2u1u3(_sll); | 92 | Ip_u2u1u3(_sll); |
93 | Ip_u2u1u3(_sra); | 93 | Ip_u2u1u3(_sra); |
94 | Ip_u2u1u3(_srl); | 94 | Ip_u2u1u3(_srl); |
95 | Ip_u2u1u3(_rotr); | ||
95 | Ip_u3u1u2(_subu); | 96 | Ip_u3u1u2(_subu); |
96 | Ip_u2s3u1(_sw); | 97 | Ip_u2s3u1(_sw); |
97 | Ip_0(_tlbp); | 98 | Ip_0(_tlbp); |
99 | Ip_0(_tlbr); | ||
98 | Ip_0(_tlbwi); | 100 | Ip_0(_tlbwi); |
99 | Ip_0(_tlbwr); | 101 | Ip_0(_tlbwr); |
100 | Ip_u3u1u2(_xor); | 102 | Ip_u3u1u2(_xor); |
@@ -129,6 +131,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ | |||
129 | # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) | 131 | # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) |
130 | # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) | 132 | # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) |
131 | # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) | 133 | # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) |
134 | # define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh) | ||
132 | # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) | 135 | # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) |
133 | # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) | 136 | # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) |
134 | # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) | 137 | # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) |
@@ -142,6 +145,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ | |||
142 | # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) | 145 | # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) |
143 | # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) | 146 | # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) |
144 | # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) | 147 | # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) |
148 | # define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh) | ||
145 | # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd) | 149 | # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd) |
146 | # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd) | 150 | # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd) |
147 | # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) | 151 | # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) |