aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-10 10:48:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-10 10:48:05 -0400
commitdaf799cca8abbf7f3e253ecf1d41d244070773d7 (patch)
tree6fb27ff60b820ae0eeb906c8a5d8d7f93f89cd8b /arch/mips/include
parent6019958d146a4f127dae727a930f902c92531e6e (diff)
parentb22d1b6a91ca4260f869e349179ae53f18c664db (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: - More work on DT support for various platforms - Various fixes that were to late to make it straight into 3.9 - Improved platform support, in particular the Netlogic XLR and BCM63xx, and the SEAD3 and Malta eval boards. - Support for several Ralink SOC families. - Complete support for the microMIPS ASE which basically reencodes the existing MIPS32/MIPS64 ISA to use non-constant size instructions. - Some fallout from LTO work which remove old cruft and will generally make the MIPS kernel easier to maintain and resistant to compiler optimization, even in absence of LTO. - KVM support. While MIPS has announced hardware virtualization extensions this KVM extension uses trap and emulate mode for virtualization of MIPS32. More KVM work to add support for VZ hardware virtualizaiton extensions and MIPS64 will probably already be merged for 3.11. Most of this has been sitting in -next for a long time. All defconfigs have been build or run time tested except three for which fixes are being sent by other maintainers. Semantic conflict with kvm updates done as per Ralf * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (118 commits) MIPS: Add new GIC clockevent driver. MIPS: Formatting clean-ups for clocksources. MIPS: Refactor GIC clocksource code. MIPS: Move 'gic_frequency' to common location. MIPS: Move 'gic_present' to common location. MIPS: MIPS16e: Add unaligned access support. MIPS: MIPS16e: Support handling of delay slots. MIPS: MIPS16e: Add instruction formats. MIPS: microMIPS: Optimise 'strnlen' core library function. MIPS: microMIPS: Optimise 'strlen' core library function. MIPS: microMIPS: Optimise 'strncpy' core library function. MIPS: microMIPS: Optimise 'memset' core library function. MIPS: microMIPS: Add configuration option for microMIPS kernel. MIPS: microMIPS: Disable LL/SC and fix linker bug. MIPS: microMIPS: Add vdso support. MIPS: microMIPS: Add unaligned access support. MIPS: microMIPS: Support handling of delay slots. MIPS: microMIPS: Add support for exception handling. MIPS: microMIPS: Floating point support. MIPS: microMIPS: Fix macro naming in micro-assembler. ...
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/asm.h2
-rw-r--r--arch/mips/include/asm/bootinfo.h1
-rw-r--r--arch/mips/include/asm/branch.h40
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/dma-coherence.h15
-rw-r--r--arch/mips/include/asm/dma-mapping.h1
-rw-r--r--arch/mips/include/asm/fpu_emulator.h6
-rw-r--r--arch/mips/include/asm/fw/fw.h47
-rw-r--r--arch/mips/include/asm/gic.h16
-rw-r--r--arch/mips/include/asm/hazards.h371
-rw-r--r--arch/mips/include/asm/inst.h12
-rw-r--r--arch/mips/include/asm/irqflags.h153
-rw-r--r--arch/mips/include/asm/kvm.h55
-rw-r--r--arch/mips/include/asm/kvm_host.h667
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h141
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h105
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h1
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h5
-rw-r--r--arch/mips/include/asm/mach-generic/spaces.h9
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h84
-rw-r--r--arch/mips/include/asm/mach-ralink/rt288x.h53
-rw-r--r--arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h56
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x.h27
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h56
-rw-r--r--arch/mips/include/asm/mach-ralink/rt3883.h252
-rw-r--r--arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h55
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h4
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h3
-rw-r--r--arch/mips/include/asm/mips-boards/prom.h47
-rw-r--r--arch/mips/include/asm/mips_machine.h4
-rw-r--r--arch/mips/include/asm/mipsregs.h19
-rw-r--r--arch/mips/include/asm/mmu_context.h116
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h92
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h20
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h53
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/usb.h64
-rw-r--r--arch/mips/include/asm/pgtable.h1
-rw-r--r--arch/mips/include/asm/processor.h5
-rw-r--r--arch/mips/include/asm/prom.h3
-rw-r--r--arch/mips/include/asm/sn/sn_private.h2
-rw-r--r--arch/mips/include/asm/sn/types.h1
-rw-r--r--arch/mips/include/asm/spinlock.h120
-rw-r--r--arch/mips/include/asm/stackframe.h12
-rw-r--r--arch/mips/include/asm/thread_info.h8
-rw-r--r--arch/mips/include/asm/time.h8
-rw-r--r--arch/mips/include/asm/uaccess.h25
-rw-r--r--arch/mips/include/asm/uasm.h84
-rw-r--r--arch/mips/include/uapi/asm/inst.h564
52 files changed, 2850 insertions, 663 deletions
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 164a21e65b42..879691d194af 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -296,6 +296,7 @@ symbol = value
296#define LONG_SUBU subu 296#define LONG_SUBU subu
297#define LONG_L lw 297#define LONG_L lw
298#define LONG_S sw 298#define LONG_S sw
299#define LONG_SP swp
299#define LONG_SLL sll 300#define LONG_SLL sll
300#define LONG_SLLV sllv 301#define LONG_SLLV sllv
301#define LONG_SRL srl 302#define LONG_SRL srl
@@ -318,6 +319,7 @@ symbol = value
318#define LONG_SUBU dsubu 319#define LONG_SUBU dsubu
319#define LONG_L ld 320#define LONG_L ld
320#define LONG_S sd 321#define LONG_S sd
322#define LONG_SP sdp
321#define LONG_SLL dsll 323#define LONG_SLL dsll
322#define LONG_SLLV dsllv 324#define LONG_SLLV dsllv
323#define LONG_SRL dsrl 325#define LONG_SRL dsrl
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index b71dd5b16085..4d2cdea5aa37 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -104,6 +104,7 @@ struct boot_mem_map {
104extern struct boot_mem_map boot_mem_map; 104extern struct boot_mem_map boot_mem_map;
105 105
106extern void add_memory_region(phys_t start, phys_t size, long type); 106extern void add_memory_region(phys_t start, phys_t size, long type);
107extern void detect_memory_region(phys_t start, phys_t sz_min, phys_t sz_max);
107 108
108extern void prom_init(void); 109extern void prom_init(void);
109extern void prom_free_prom_memory(void); 110extern void prom_free_prom_memory(void);
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 888766ae1f85..e28a3e0eb3cb 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -11,6 +11,14 @@
11#include <asm/ptrace.h> 11#include <asm/ptrace.h>
12#include <asm/inst.h> 12#include <asm/inst.h>
13 13
14extern int __isa_exception_epc(struct pt_regs *regs);
15extern int __compute_return_epc(struct pt_regs *regs);
16extern int __compute_return_epc_for_insn(struct pt_regs *regs,
17 union mips_instruction insn);
18extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
19extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
20
21
14static inline int delay_slot(struct pt_regs *regs) 22static inline int delay_slot(struct pt_regs *regs)
15{ 23{
16 return regs->cp0_cause & CAUSEF_BD; 24 return regs->cp0_cause & CAUSEF_BD;
@@ -18,20 +26,27 @@ static inline int delay_slot(struct pt_regs *regs)
18 26
19static inline unsigned long exception_epc(struct pt_regs *regs) 27static inline unsigned long exception_epc(struct pt_regs *regs)
20{ 28{
21 if (!delay_slot(regs)) 29 if (likely(!delay_slot(regs)))
22 return regs->cp0_epc; 30 return regs->cp0_epc;
23 31
32 if (get_isa16_mode(regs->cp0_epc))
33 return __isa_exception_epc(regs);
34
24 return regs->cp0_epc + 4; 35 return regs->cp0_epc + 4;
25} 36}
26 37
27#define BRANCH_LIKELY_TAKEN 0x0001 38#define BRANCH_LIKELY_TAKEN 0x0001
28 39
29extern int __compute_return_epc(struct pt_regs *regs);
30extern int __compute_return_epc_for_insn(struct pt_regs *regs,
31 union mips_instruction insn);
32
33static inline int compute_return_epc(struct pt_regs *regs) 40static inline int compute_return_epc(struct pt_regs *regs)
34{ 41{
42 if (get_isa16_mode(regs->cp0_epc)) {
43 if (cpu_has_mmips)
44 return __microMIPS_compute_return_epc(regs);
45 if (cpu_has_mips16)
46 return __MIPS16e_compute_return_epc(regs);
47 return regs->cp0_epc;
48 }
49
35 if (!delay_slot(regs)) { 50 if (!delay_slot(regs)) {
36 regs->cp0_epc += 4; 51 regs->cp0_epc += 4;
37 return 0; 52 return 0;
@@ -40,4 +55,19 @@ static inline int compute_return_epc(struct pt_regs *regs)
40 return __compute_return_epc(regs); 55 return __compute_return_epc(regs);
41} 56}
42 57
58static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
59 union mips16e_instruction *inst)
60{
61 if (likely(!delay_slot(regs))) {
62 if (inst->ri.opcode == MIPS16e_extend_op) {
63 regs->cp0_epc += 4;
64 return 0;
65 }
66 regs->cp0_epc += 2;
67 return 0;
68 }
69
70 return __MIPS16e_compute_return_epc(regs);
71}
72
43#endif /* _ASM_BRANCH_H */ 73#endif /* _ASM_BRANCH_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1a57e8b4d092..e5ec8fcd8afa 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -113,6 +113,9 @@
113#ifndef cpu_has_pindexed_dcache 113#ifndef cpu_has_pindexed_dcache
114#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 114#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
115#endif 115#endif
116#ifndef cpu_has_local_ebase
117#define cpu_has_local_ebase 1
118#endif
116 119
117/* 120/*
118 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 121 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
new file mode 100644
index 000000000000..242cbb3ca582
--- /dev/null
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -0,0 +1,15 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 */
9#ifndef __ASM_DMA_COHERENCE_H
10#define __ASM_DMA_COHERENCE_H
11
12extern int coherentio;
13extern int hw_coherentio;
14
15#endif
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index f8fc74b6cb47..84238c574d5e 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -2,6 +2,7 @@
2#define _ASM_DMA_MAPPING_H 2#define _ASM_DMA_MAPPING_H
3 3
4#include <asm/scatterlist.h> 4#include <asm/scatterlist.h>
5#include <asm/dma-coherence.h>
5#include <asm/cache.h> 6#include <asm/cache.h>
6#include <asm-generic/dma-coherent.h> 7#include <asm-generic/dma-coherent.h>
7 8
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index 3b4092705567..2abb587d5ab4 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -54,6 +54,12 @@ do { \
54extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 54extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
55 unsigned long cpc); 55 unsigned long cpc);
56extern int do_dsemulret(struct pt_regs *xcp); 56extern int do_dsemulret(struct pt_regs *xcp);
57extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
58 struct mips_fpu_struct *ctx, int has_fpu,
59 void *__user *fault_addr);
60int process_fpemu_return(int sig, void __user *fault_addr);
61int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
62 unsigned long *contpc);
57 63
58/* 64/*
59 * Instruction inserted following the badinst to further tag the sequence 65 * Instruction inserted following the badinst to further tag the sequence
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h
new file mode 100644
index 000000000000..d6c50a7e9ede
--- /dev/null
+++ b/arch/mips/include/asm/fw/fw.h
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc.
7 */
8#ifndef __ASM_FW_H_
9#define __ASM_FW_H_
10
11#include <asm/bootinfo.h> /* For cleaner code... */
12
13enum fw_memtypes {
14 fw_dontuse,
15 fw_code,
16 fw_free,
17};
18
19typedef struct {
20 unsigned long base; /* Within KSEG0 */
21 unsigned int size; /* bytes */
22 enum fw_memtypes type; /* fw_memtypes */
23} fw_memblock_t;
24
25/* Maximum number of memory block descriptors. */
26#define FW_MAX_MEMBLOCKS 32
27
28extern int fw_argc;
29extern int *_fw_argv;
30extern int *_fw_envp;
31
32/*
33 * Most firmware like YAMON, PMON, etc. pass arguments and environment
34 * variables as 32-bit pointers. These take care of sign extension.
35 */
36#define fw_argv(index) ((char *)(long)_fw_argv[(index)])
37#define fw_envp(index) ((char *)(long)_fw_envp[(index)])
38
39extern void fw_init_cmdline(void);
40extern char *fw_getcmdline(void);
41extern fw_memblock_t *fw_getmdesc(void);
42extern void fw_meminit(void);
43extern char *fw_getenv(char *name);
44extern unsigned long fw_getenvl(char *name);
45extern void fw_init_early_console(char port);
46
47#endif /* __ASM_FW_H_ */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index bdc9786ab5a7..7153b32de18e 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -202,7 +202,7 @@
202#define GIC_VPE_WD_COUNT0_OFS 0x0094 202#define GIC_VPE_WD_COUNT0_OFS 0x0094
203#define GIC_VPE_WD_INITIAL0_OFS 0x0098 203#define GIC_VPE_WD_INITIAL0_OFS 0x0098
204#define GIC_VPE_COMPARE_LO_OFS 0x00a0 204#define GIC_VPE_COMPARE_LO_OFS 0x00a0
205#define GIC_VPE_COMPARE_HI 0x00a4 205#define GIC_VPE_COMPARE_HI_OFS 0x00a4
206 206
207#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 207#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
208#define GIC_VPE_EIC_SS(intr) \ 208#define GIC_VPE_EIC_SS(intr) \
@@ -359,7 +359,11 @@ struct gic_shared_intr_map {
359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360#define GIC_PIN_TO_VEC_OFFSET (1) 360#define GIC_PIN_TO_VEC_OFFSET (1)
361 361
362extern int gic_present; 362#include <linux/clocksource.h>
363#include <linux/irq.h>
364
365extern unsigned int gic_present;
366extern unsigned int gic_frequency;
363extern unsigned long _gic_base; 367extern unsigned long _gic_base;
364extern unsigned int gic_irq_base; 368extern unsigned int gic_irq_base;
365extern unsigned int gic_irq_flags[]; 369extern unsigned int gic_irq_flags[];
@@ -368,18 +372,20 @@ extern struct gic_shared_intr_map gic_shared_intr_map[];
368extern void gic_init(unsigned long gic_base_addr, 372extern void gic_init(unsigned long gic_base_addr,
369 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, 373 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
370 unsigned int intrmap_size, unsigned int irqbase); 374 unsigned int intrmap_size, unsigned int irqbase);
371
372extern void gic_clocksource_init(unsigned int); 375extern void gic_clocksource_init(unsigned int);
373extern unsigned int gic_get_int(void); 376extern unsigned int gic_compare_int (void);
377extern cycle_t gic_read_count(void);
378extern cycle_t gic_read_compare(void);
379extern void gic_write_compare(cycle_t cnt);
374extern void gic_send_ipi(unsigned int intr); 380extern void gic_send_ipi(unsigned int intr);
375extern unsigned int plat_ipi_call_int_xlate(unsigned int); 381extern unsigned int plat_ipi_call_int_xlate(unsigned int);
376extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 382extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
377extern void gic_bind_eic_interrupt(int irq, int set); 383extern void gic_bind_eic_interrupt(int irq, int set);
378extern unsigned int gic_get_timer_pending(void); 384extern unsigned int gic_get_timer_pending(void);
385extern unsigned int gic_get_int(void);
379extern void gic_enable_interrupt(int irq_vec); 386extern void gic_enable_interrupt(int irq_vec);
380extern void gic_disable_interrupt(int irq_vec); 387extern void gic_disable_interrupt(int irq_vec);
381extern void gic_irq_ack(struct irq_data *d); 388extern void gic_irq_ack(struct irq_data *d);
382extern void gic_finish_irq(struct irq_data *d); 389extern void gic_finish_irq(struct irq_data *d);
383extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); 390extern void gic_platform_init(int irqs, struct irq_chip *irq_controller);
384
385#endif /* _ASM_GICREGS_H */ 391#endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 44d6a5bde4a1..e3ee92d4dbe7 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -10,34 +10,13 @@
10#ifndef _ASM_HAZARDS_H 10#ifndef _ASM_HAZARDS_H
11#define _ASM_HAZARDS_H 11#define _ASM_HAZARDS_H
12 12
13#ifdef __ASSEMBLY__ 13#include <linux/stringify.h>
14#define ASMMACRO(name, code...) .macro name; code; .endm
15#else
16
17#include <asm/cpu-features.h>
18
19#define ASMMACRO(name, code...) \
20__asm__(".macro " #name "; " #code "; .endm"); \
21 \
22static inline void name(void) \
23{ \
24 __asm__ __volatile__ (#name); \
25}
26
27/*
28 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
29 */
30extern void mips_ihb(void);
31
32#endif
33 14
34ASMMACRO(_ssnop, 15#define ___ssnop \
35 sll $0, $0, 1 16 sll $0, $0, 1
36 )
37 17
38ASMMACRO(_ehb, 18#define ___ehb \
39 sll $0, $0, 3 19 sll $0, $0, 3
40 )
41 20
42/* 21/*
43 * TLB hazards 22 * TLB hazards
@@ -48,24 +27,24 @@ ASMMACRO(_ehb,
48 * MIPSR2 defines ehb for hazard avoidance 27 * MIPSR2 defines ehb for hazard avoidance
49 */ 28 */
50 29
51ASMMACRO(mtc0_tlbw_hazard, 30#define __mtc0_tlbw_hazard \
52 _ehb 31 ___ehb
53 ) 32
54ASMMACRO(tlbw_use_hazard, 33#define __tlbw_use_hazard \
55 _ehb 34 ___ehb
56 ) 35
57ASMMACRO(tlb_probe_hazard, 36#define __tlb_probe_hazard \
58 _ehb 37 ___ehb
59 ) 38
60ASMMACRO(irq_enable_hazard, 39#define __irq_enable_hazard \
61 _ehb 40 ___ehb
62 ) 41
63ASMMACRO(irq_disable_hazard, 42#define __irq_disable_hazard \
64 _ehb 43 ___ehb
65 ) 44
66ASMMACRO(back_to_back_c0_hazard, 45#define __back_to_back_c0_hazard \
67 _ehb 46 ___ehb
68 ) 47
69/* 48/*
70 * gcc has a tradition of misscompiling the previous construct using the 49 * gcc has a tradition of misscompiling the previous construct using the
71 * address of a label as argument to inline assembler. Gas otoh has the 50 * address of a label as argument to inline assembler. Gas otoh has the
@@ -94,24 +73,42 @@ do { \
94 * These are slightly complicated by the fact that we guarantee R1 kernels to 73 * These are slightly complicated by the fact that we guarantee R1 kernels to
95 * run fine on R2 processors. 74 * run fine on R2 processors.
96 */ 75 */
97ASMMACRO(mtc0_tlbw_hazard, 76
98 _ssnop; _ssnop; _ehb 77#define __mtc0_tlbw_hazard \
99 ) 78 ___ssnop; \
100ASMMACRO(tlbw_use_hazard, 79 ___ssnop; \
101 _ssnop; _ssnop; _ssnop; _ehb 80 ___ehb
102 ) 81
103ASMMACRO(tlb_probe_hazard, 82#define __tlbw_use_hazard \
104 _ssnop; _ssnop; _ssnop; _ehb 83 ___ssnop; \
105 ) 84 ___ssnop; \
106ASMMACRO(irq_enable_hazard, 85 ___ssnop; \
107 _ssnop; _ssnop; _ssnop; _ehb 86 ___ehb
108 ) 87
109ASMMACRO(irq_disable_hazard, 88#define __tlb_probe_hazard \
110 _ssnop; _ssnop; _ssnop; _ehb 89 ___ssnop; \
111 ) 90 ___ssnop; \
112ASMMACRO(back_to_back_c0_hazard, 91 ___ssnop; \
113 _ssnop; _ssnop; _ssnop; _ehb 92 ___ehb
114 ) 93
94#define __irq_enable_hazard \
95 ___ssnop; \
96 ___ssnop; \
97 ___ssnop; \
98 ___ehb
99
100#define __irq_disable_hazard \
101 ___ssnop; \
102 ___ssnop; \
103 ___ssnop; \
104 ___ehb
105
106#define __back_to_back_c0_hazard \
107 ___ssnop; \
108 ___ssnop; \
109 ___ssnop; \
110 ___ehb
111
115/* 112/*
116 * gcc has a tradition of misscompiling the previous construct using the 113 * gcc has a tradition of misscompiling the previous construct using the
117 * address of a label as argument to inline assembler. Gas otoh has the 114 * address of a label as argument to inline assembler. Gas otoh has the
@@ -147,18 +144,18 @@ do { \
147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
148 */ 145 */
149 146
150ASMMACRO(mtc0_tlbw_hazard, 147#define __mtc0_tlbw_hazard
151 ) 148
152ASMMACRO(tlbw_use_hazard, 149#define __tlbw_use_hazard
153 ) 150
154ASMMACRO(tlb_probe_hazard, 151#define __tlb_probe_hazard
155 ) 152
156ASMMACRO(irq_enable_hazard, 153#define __irq_enable_hazard
157 ) 154
158ASMMACRO(irq_disable_hazard, 155#define __irq_disable_hazard
159 ) 156
160ASMMACRO(back_to_back_c0_hazard, 157#define __back_to_back_c0_hazard
161 ) 158
162#define instruction_hazard() do { } while (0) 159#define instruction_hazard() do { } while (0)
163 160
164#elif defined(CONFIG_CPU_SB1) 161#elif defined(CONFIG_CPU_SB1)
@@ -166,19 +163,21 @@ ASMMACRO(back_to_back_c0_hazard,
166/* 163/*
167 * Mostly like R4000 for historic reasons 164 * Mostly like R4000 for historic reasons
168 */ 165 */
169ASMMACRO(mtc0_tlbw_hazard, 166#define __mtc0_tlbw_hazard
170 ) 167
171ASMMACRO(tlbw_use_hazard, 168#define __tlbw_use_hazard
172 ) 169
173ASMMACRO(tlb_probe_hazard, 170#define __tlb_probe_hazard
174 ) 171
175ASMMACRO(irq_enable_hazard, 172#define __irq_enable_hazard
176 ) 173
177ASMMACRO(irq_disable_hazard, 174#define __irq_disable_hazard \
178 _ssnop; _ssnop; _ssnop 175 ___ssnop; \
179 ) 176 ___ssnop; \
180ASMMACRO(back_to_back_c0_hazard, 177 ___ssnop
181 ) 178
179#define __back_to_back_c0_hazard
180
182#define instruction_hazard() do { } while (0) 181#define instruction_hazard() do { } while (0)
183 182
184#else 183#else
@@ -192,24 +191,35 @@ ASMMACRO(back_to_back_c0_hazard,
192 * hazard so this is nice trick to have an optimal code for a range of 191 * hazard so this is nice trick to have an optimal code for a range of
193 * processors. 192 * processors.
194 */ 193 */
195ASMMACRO(mtc0_tlbw_hazard, 194#define __mtc0_tlbw_hazard \
196 nop; nop 195 nop; \
197 ) 196 nop
198ASMMACRO(tlbw_use_hazard, 197
199 nop; nop; nop 198#define __tlbw_use_hazard \
200 ) 199 nop; \
201ASMMACRO(tlb_probe_hazard, 200 nop; \
202 nop; nop; nop 201 nop
203 ) 202
204ASMMACRO(irq_enable_hazard, 203#define __tlb_probe_hazard \
205 _ssnop; _ssnop; _ssnop; 204 nop; \
206 ) 205 nop; \
207ASMMACRO(irq_disable_hazard, 206 nop
208 nop; nop; nop 207
209 ) 208#define __irq_enable_hazard \
210ASMMACRO(back_to_back_c0_hazard, 209 ___ssnop; \
211 _ssnop; _ssnop; _ssnop; 210 ___ssnop; \
212 ) 211 ___ssnop
212
213#define __irq_disable_hazard \
214 nop; \
215 nop; \
216 nop
217
218#define __back_to_back_c0_hazard \
219 ___ssnop; \
220 ___ssnop; \
221 ___ssnop
222
213#define instruction_hazard() do { } while (0) 223#define instruction_hazard() do { } while (0)
214 224
215#endif 225#endif
@@ -218,32 +228,137 @@ ASMMACRO(back_to_back_c0_hazard,
218/* FPU hazards */ 228/* FPU hazards */
219 229
220#if defined(CONFIG_CPU_SB1) 230#if defined(CONFIG_CPU_SB1)
221ASMMACRO(enable_fpu_hazard, 231
222 .set push; 232#define __enable_fpu_hazard \
223 .set mips64; 233 .set push; \
224 .set noreorder; 234 .set mips64; \
225 _ssnop; 235 .set noreorder; \
226 bnezl $0, .+4; 236 ___ssnop; \
227 _ssnop; 237 bnezl $0, .+4; \
228 .set pop 238 ___ssnop; \
229) 239 .set pop
230ASMMACRO(disable_fpu_hazard, 240
231) 241#define __disable_fpu_hazard
232 242
233#elif defined(CONFIG_CPU_MIPSR2) 243#elif defined(CONFIG_CPU_MIPSR2)
234ASMMACRO(enable_fpu_hazard, 244
235 _ehb 245#define __enable_fpu_hazard \
236) 246 ___ehb
237ASMMACRO(disable_fpu_hazard, 247
238 _ehb 248#define __disable_fpu_hazard \
239) 249 ___ehb
250
240#else 251#else
241ASMMACRO(enable_fpu_hazard, 252
242 nop; nop; nop; nop 253#define __enable_fpu_hazard \
243) 254 nop; \
244ASMMACRO(disable_fpu_hazard, 255 nop; \
245 _ehb 256 nop; \
246) 257 nop
258
259#define __disable_fpu_hazard \
260 ___ehb
261
247#endif 262#endif
248 263
264#ifdef __ASSEMBLY__
265
266#define _ssnop ___ssnop
267#define _ehb ___ehb
268#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
269#define tlbw_use_hazard __tlbw_use_hazard
270#define tlb_probe_hazard __tlb_probe_hazard
271#define irq_enable_hazard __irq_enable_hazard
272#define irq_disable_hazard __irq_disable_hazard
273#define back_to_back_c0_hazard __back_to_back_c0_hazard
274#define enable_fpu_hazard __enable_fpu_hazard
275#define disable_fpu_hazard __disable_fpu_hazard
276
277#else
278
279#define _ssnop() \
280do { \
281 __asm__ __volatile__( \
282 __stringify(___ssnop) \
283 ); \
284} while (0)
285
286#define _ehb() \
287do { \
288 __asm__ __volatile__( \
289 __stringify(___ehb) \
290 ); \
291} while (0)
292
293
294#define mtc0_tlbw_hazard() \
295do { \
296 __asm__ __volatile__( \
297 __stringify(__mtc0_tlbw_hazard) \
298 ); \
299} while (0)
300
301
302#define tlbw_use_hazard() \
303do { \
304 __asm__ __volatile__( \
305 __stringify(__tlbw_use_hazard) \
306 ); \
307} while (0)
308
309
310#define tlb_probe_hazard() \
311do { \
312 __asm__ __volatile__( \
313 __stringify(__tlb_probe_hazard) \
314 ); \
315} while (0)
316
317
318#define irq_enable_hazard() \
319do { \
320 __asm__ __volatile__( \
321 __stringify(__irq_enable_hazard) \
322 ); \
323} while (0)
324
325
326#define irq_disable_hazard() \
327do { \
328 __asm__ __volatile__( \
329 __stringify(__irq_disable_hazard) \
330 ); \
331} while (0)
332
333
334#define back_to_back_c0_hazard() \
335do { \
336 __asm__ __volatile__( \
337 __stringify(__back_to_back_c0_hazard) \
338 ); \
339} while (0)
340
341
342#define enable_fpu_hazard() \
343do { \
344 __asm__ __volatile__( \
345 __stringify(__enable_fpu_hazard) \
346 ); \
347} while (0)
348
349
350#define disable_fpu_hazard() \
351do { \
352 __asm__ __volatile__( \
353 __stringify(__disable_fpu_hazard) \
354 ); \
355} while (0)
356
357/*
358 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
359 */
360extern void mips_ihb(void);
361
362#endif /* __ASSEMBLY__ */
363
249#endif /* _ASM_HAZARDS_H */ 364#endif /* _ASM_HAZARDS_H */
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index f1eadf764071..22912f78401c 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -73,4 +73,16 @@
73 73
74typedef unsigned int mips_instruction; 74typedef unsigned int mips_instruction;
75 75
76/* microMIPS instruction decode structure. Do NOT export!!! */
77struct mm_decoded_insn {
78 mips_instruction insn;
79 mips_instruction next_insn;
80 int pc_inc;
81 int next_pc_inc;
82 int micro_mips_mode;
83};
84
85/* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
86extern const int reg16to32[];
87
76#endif /* _ASM_INST_H */ 88#endif /* _ASM_INST_H */
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9f3384c789d7..45c00951888b 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -14,53 +14,48 @@
14#ifndef __ASSEMBLY__ 14#ifndef __ASSEMBLY__
15 15
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/stringify.h>
17#include <asm/hazards.h> 18#include <asm/hazards.h>
18 19
19#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) 20#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
20 21
21__asm__( 22static inline void arch_local_irq_disable(void)
22 " .macro arch_local_irq_disable\n" 23{
24 __asm__ __volatile__(
23 " .set push \n" 25 " .set push \n"
24 " .set noat \n" 26 " .set noat \n"
25 " di \n" 27 " di \n"
26 " irq_disable_hazard \n" 28 " " __stringify(__irq_disable_hazard) " \n"
27 " .set pop \n" 29 " .set pop \n"
28 " .endm \n"); 30 : /* no outputs */
29 31 : /* no inputs */
30static inline void arch_local_irq_disable(void) 32 : "memory");
31{
32 __asm__ __volatile__(
33 "arch_local_irq_disable"
34 : /* no outputs */
35 : /* no inputs */
36 : "memory");
37} 33}
38 34
35static inline unsigned long arch_local_irq_save(void)
36{
37 unsigned long flags;
39 38
40__asm__( 39 asm __volatile__(
41 " .macro arch_local_irq_save result \n"
42 " .set push \n" 40 " .set push \n"
43 " .set reorder \n" 41 " .set reorder \n"
44 " .set noat \n" 42 " .set noat \n"
45 " di \\result \n" 43 " di %[flags] \n"
46 " andi \\result, 1 \n" 44 " andi %[flags], 1 \n"
47 " irq_disable_hazard \n" 45 " " __stringify(__irq_disable_hazard) " \n"
48 " .set pop \n" 46 " .set pop \n"
49 " .endm \n"); 47 : [flags] "=r" (flags)
48 : /* no inputs */
49 : "memory");
50 50
51static inline unsigned long arch_local_irq_save(void)
52{
53 unsigned long flags;
54 asm volatile("arch_local_irq_save\t%0"
55 : "=r" (flags)
56 : /* no inputs */
57 : "memory");
58 return flags; 51 return flags;
59} 52}
60 53
54static inline void arch_local_irq_restore(unsigned long flags)
55{
56 unsigned long __tmp1;
61 57
62__asm__( 58 __asm__ __volatile__(
63 " .macro arch_local_irq_restore flags \n"
64 " .set push \n" 59 " .set push \n"
65 " .set noreorder \n" 60 " .set noreorder \n"
66 " .set noat \n" 61 " .set noat \n"
@@ -69,7 +64,7 @@ __asm__(
69 * Slow, but doesn't suffer from a relatively unlikely race 64 * Slow, but doesn't suffer from a relatively unlikely race
70 * condition we're having since days 1. 65 * condition we're having since days 1.
71 */ 66 */
72 " beqz \\flags, 1f \n" 67 " beqz %[flags], 1f \n"
73 " di \n" 68 " di \n"
74 " ei \n" 69 " ei \n"
75 "1: \n" 70 "1: \n"
@@ -78,33 +73,44 @@ __asm__(
78 * Fast, dangerous. Life is fun, life is good. 73 * Fast, dangerous. Life is fun, life is good.
79 */ 74 */
80 " mfc0 $1, $12 \n" 75 " mfc0 $1, $12 \n"
81 " ins $1, \\flags, 0, 1 \n" 76 " ins $1, %[flags], 0, 1 \n"
82 " mtc0 $1, $12 \n" 77 " mtc0 $1, $12 \n"
83#endif 78#endif
84 " irq_disable_hazard \n" 79 " " __stringify(__irq_disable_hazard) " \n"
85 " .set pop \n" 80 " .set pop \n"
86 " .endm \n"); 81 : [flags] "=r" (__tmp1)
87 82 : "0" (flags)
88static inline void arch_local_irq_restore(unsigned long flags) 83 : "memory");
89{
90 unsigned long __tmp1;
91
92 __asm__ __volatile__(
93 "arch_local_irq_restore\t%0"
94 : "=r" (__tmp1)
95 : "0" (flags)
96 : "memory");
97} 84}
98 85
99static inline void __arch_local_irq_restore(unsigned long flags) 86static inline void __arch_local_irq_restore(unsigned long flags)
100{ 87{
101 unsigned long __tmp1;
102
103 __asm__ __volatile__( 88 __asm__ __volatile__(
104 "arch_local_irq_restore\t%0" 89 " .set push \n"
105 : "=r" (__tmp1) 90 " .set noreorder \n"
106 : "0" (flags) 91 " .set noat \n"
107 : "memory"); 92#if defined(CONFIG_IRQ_CPU)
93 /*
94 * Slow, but doesn't suffer from a relatively unlikely race
95 * condition we're having since days 1.
96 */
97 " beqz %[flags], 1f \n"
98 " di \n"
99 " ei \n"
100 "1: \n"
101#else
102 /*
103 * Fast, dangerous. Life is fun, life is good.
104 */
105 " mfc0 $1, $12 \n"
106 " ins $1, %[flags], 0, 1 \n"
107 " mtc0 $1, $12 \n"
108#endif
109 " " __stringify(__irq_disable_hazard) " \n"
110 " .set pop \n"
111 : [flags] "=r" (flags)
112 : "0" (flags)
113 : "memory");
108} 114}
109#else 115#else
110/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */ 116/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
@@ -115,8 +121,18 @@ void __arch_local_irq_restore(unsigned long flags);
115#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */ 121#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
116 122
117 123
118__asm__( 124extern void smtc_ipi_replay(void);
119 " .macro arch_local_irq_enable \n" 125
126static inline void arch_local_irq_enable(void)
127{
128#ifdef CONFIG_MIPS_MT_SMTC
129 /*
130 * SMTC kernel needs to do a software replay of queued
131 * IPIs, at the cost of call overhead on each local_irq_enable()
132 */
133 smtc_ipi_replay();
134#endif
135 __asm__ __volatile__(
120 " .set push \n" 136 " .set push \n"
121 " .set reorder \n" 137 " .set reorder \n"
122 " .set noat \n" 138 " .set noat \n"
@@ -133,45 +149,28 @@ __asm__(
133 " xori $1,0x1e \n" 149 " xori $1,0x1e \n"
134 " mtc0 $1,$12 \n" 150 " mtc0 $1,$12 \n"
135#endif 151#endif
136 " irq_enable_hazard \n" 152 " " __stringify(__irq_enable_hazard) " \n"
137 " .set pop \n" 153 " .set pop \n"
138 " .endm"); 154 : /* no outputs */
139 155 : /* no inputs */
140extern void smtc_ipi_replay(void); 156 : "memory");
141
142static inline void arch_local_irq_enable(void)
143{
144#ifdef CONFIG_MIPS_MT_SMTC
145 /*
146 * SMTC kernel needs to do a software replay of queued
147 * IPIs, at the cost of call overhead on each local_irq_enable()
148 */
149 smtc_ipi_replay();
150#endif
151 __asm__ __volatile__(
152 "arch_local_irq_enable"
153 : /* no outputs */
154 : /* no inputs */
155 : "memory");
156} 157}
157 158
159static inline unsigned long arch_local_save_flags(void)
160{
161 unsigned long flags;
158 162
159__asm__( 163 asm __volatile__(
160 " .macro arch_local_save_flags flags \n"
161 " .set push \n" 164 " .set push \n"
162 " .set reorder \n" 165 " .set reorder \n"
163#ifdef CONFIG_MIPS_MT_SMTC 166#ifdef CONFIG_MIPS_MT_SMTC
164 " mfc0 \\flags, $2, 1 \n" 167 " mfc0 %[flags], $2, 1 \n"
165#else 168#else
166 " mfc0 \\flags, $12 \n" 169 " mfc0 %[flags], $12 \n"
167#endif 170#endif
168 " .set pop \n" 171 " .set pop \n"
169 " .endm \n"); 172 : [flags] "=r" (flags));
170 173
171static inline unsigned long arch_local_save_flags(void)
172{
173 unsigned long flags;
174 asm volatile("arch_local_save_flags %0" : "=r" (flags));
175 return flags; 174 return flags;
176} 175}
177 176
diff --git a/arch/mips/include/asm/kvm.h b/arch/mips/include/asm/kvm.h
new file mode 100644
index 000000000000..85789eacbf18
--- /dev/null
+++ b/arch/mips/include/asm/kvm.h
@@ -0,0 +1,55 @@
1/*
2* This file is subject to the terms and conditions of the GNU General Public
3* License. See the file "COPYING" in the main directory of this archive
4* for more details.
5*
6* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7* Authors: Sanjay Lal <sanjayl@kymasys.com>
8*/
9
10#ifndef __LINUX_KVM_MIPS_H
11#define __LINUX_KVM_MIPS_H
12
13#include <linux/types.h>
14
15#define __KVM_MIPS
16
17#define N_MIPS_COPROC_REGS 32
18#define N_MIPS_COPROC_SEL 8
19
20/* for KVM_GET_REGS and KVM_SET_REGS */
21struct kvm_regs {
22 __u32 gprs[32];
23 __u32 hi;
24 __u32 lo;
25 __u32 pc;
26
27 __u32 cp0reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
28};
29
30/* for KVM_GET_SREGS and KVM_SET_SREGS */
31struct kvm_sregs {
32};
33
34/* for KVM_GET_FPU and KVM_SET_FPU */
35struct kvm_fpu {
36};
37
38struct kvm_debug_exit_arch {
39};
40
41/* for KVM_SET_GUEST_DEBUG */
42struct kvm_guest_debug_arch {
43};
44
45struct kvm_mips_interrupt {
46 /* in */
47 __u32 cpu;
48 __u32 irq;
49};
50
51/* definition of registers in kvm_run */
52struct kvm_sync_regs {
53};
54
55#endif /* __LINUX_KVM_MIPS_H */
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
new file mode 100644
index 000000000000..e68781e18387
--- /dev/null
+++ b/arch/mips/include/asm/kvm_host.h
@@ -0,0 +1,667 @@
1/*
2* This file is subject to the terms and conditions of the GNU General Public
3* License. See the file "COPYING" in the main directory of this archive
4* for more details.
5*
6* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7* Authors: Sanjay Lal <sanjayl@kymasys.com>
8*/
9
10#ifndef __MIPS_KVM_HOST_H__
11#define __MIPS_KVM_HOST_H__
12
13#include <linux/mutex.h>
14#include <linux/hrtimer.h>
15#include <linux/interrupt.h>
16#include <linux/types.h>
17#include <linux/kvm.h>
18#include <linux/kvm_types.h>
19#include <linux/threads.h>
20#include <linux/spinlock.h>
21
22
23#define KVM_MAX_VCPUS 1
24#define KVM_USER_MEM_SLOTS 8
25/* memory slots that does not exposed to userspace */
26#define KVM_PRIVATE_MEM_SLOTS 0
27
28#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
29
30/* Don't support huge pages */
31#define KVM_HPAGE_GFN_SHIFT(x) 0
32
33/* We don't currently support large pages. */
34#define KVM_NR_PAGE_SIZES 1
35#define KVM_PAGES_PER_HPAGE(x) 1
36
37
38
39/* Special address that contains the comm page, used for reducing # of traps */
40#define KVM_GUEST_COMMPAGE_ADDR 0x0
41
42#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
43 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
44
45#define KVM_GUEST_KUSEG 0x00000000UL
46#define KVM_GUEST_KSEG0 0x40000000UL
47#define KVM_GUEST_KSEG23 0x60000000UL
48#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
49#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
50
51#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
52#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
53#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
54
55/*
56 * Map an address to a certain kernel segment
57 */
58#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
59#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
60#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
61
62#define KVM_INVALID_PAGE 0xdeadbeef
63#define KVM_INVALID_INST 0xdeadbeef
64#define KVM_INVALID_ADDR 0xdeadbeef
65
66#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
67
68#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
69#define MS_TO_NS(x) (x * 1E6L)
70
71#define CAUSEB_DC 27
72#define CAUSEF_DC (_ULCAST_(1) << 27)
73
74struct kvm;
75struct kvm_run;
76struct kvm_vcpu;
77struct kvm_interrupt;
78
79extern atomic_t kvm_mips_instance;
80extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
81extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
82extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
83
84struct kvm_vm_stat {
85 u32 remote_tlb_flush;
86};
87
88struct kvm_vcpu_stat {
89 u32 wait_exits;
90 u32 cache_exits;
91 u32 signal_exits;
92 u32 int_exits;
93 u32 cop_unusable_exits;
94 u32 tlbmod_exits;
95 u32 tlbmiss_ld_exits;
96 u32 tlbmiss_st_exits;
97 u32 addrerr_st_exits;
98 u32 addrerr_ld_exits;
99 u32 syscall_exits;
100 u32 resvd_inst_exits;
101 u32 break_inst_exits;
102 u32 flush_dcache_exits;
103 u32 halt_wakeup;
104};
105
106enum kvm_mips_exit_types {
107 WAIT_EXITS,
108 CACHE_EXITS,
109 SIGNAL_EXITS,
110 INT_EXITS,
111 COP_UNUSABLE_EXITS,
112 TLBMOD_EXITS,
113 TLBMISS_LD_EXITS,
114 TLBMISS_ST_EXITS,
115 ADDRERR_ST_EXITS,
116 ADDRERR_LD_EXITS,
117 SYSCALL_EXITS,
118 RESVD_INST_EXITS,
119 BREAK_INST_EXITS,
120 FLUSH_DCACHE_EXITS,
121 MAX_KVM_MIPS_EXIT_TYPES
122};
123
124struct kvm_arch_memory_slot {
125};
126
127struct kvm_arch {
128 /* Guest GVA->HPA page table */
129 unsigned long *guest_pmap;
130 unsigned long guest_pmap_npages;
131
132 /* Wired host TLB used for the commpage */
133 int commpage_tlb;
134};
135
136#define N_MIPS_COPROC_REGS 32
137#define N_MIPS_COPROC_SEL 8
138
139struct mips_coproc {
140 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
141#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
142 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
143#endif
144};
145
146/*
147 * Coprocessor 0 register names
148 */
149#define MIPS_CP0_TLB_INDEX 0
150#define MIPS_CP0_TLB_RANDOM 1
151#define MIPS_CP0_TLB_LOW 2
152#define MIPS_CP0_TLB_LO0 2
153#define MIPS_CP0_TLB_LO1 3
154#define MIPS_CP0_TLB_CONTEXT 4
155#define MIPS_CP0_TLB_PG_MASK 5
156#define MIPS_CP0_TLB_WIRED 6
157#define MIPS_CP0_HWRENA 7
158#define MIPS_CP0_BAD_VADDR 8
159#define MIPS_CP0_COUNT 9
160#define MIPS_CP0_TLB_HI 10
161#define MIPS_CP0_COMPARE 11
162#define MIPS_CP0_STATUS 12
163#define MIPS_CP0_CAUSE 13
164#define MIPS_CP0_EXC_PC 14
165#define MIPS_CP0_PRID 15
166#define MIPS_CP0_CONFIG 16
167#define MIPS_CP0_LLADDR 17
168#define MIPS_CP0_WATCH_LO 18
169#define MIPS_CP0_WATCH_HI 19
170#define MIPS_CP0_TLB_XCONTEXT 20
171#define MIPS_CP0_ECC 26
172#define MIPS_CP0_CACHE_ERR 27
173#define MIPS_CP0_TAG_LO 28
174#define MIPS_CP0_TAG_HI 29
175#define MIPS_CP0_ERROR_PC 30
176#define MIPS_CP0_DEBUG 23
177#define MIPS_CP0_DEPC 24
178#define MIPS_CP0_PERFCNT 25
179#define MIPS_CP0_ERRCTL 26
180#define MIPS_CP0_DATA_LO 28
181#define MIPS_CP0_DATA_HI 29
182#define MIPS_CP0_DESAVE 31
183
184#define MIPS_CP0_CONFIG_SEL 0
185#define MIPS_CP0_CONFIG1_SEL 1
186#define MIPS_CP0_CONFIG2_SEL 2
187#define MIPS_CP0_CONFIG3_SEL 3
188
189/* Config0 register bits */
190#define CP0C0_M 31
191#define CP0C0_K23 28
192#define CP0C0_KU 25
193#define CP0C0_MDU 20
194#define CP0C0_MM 17
195#define CP0C0_BM 16
196#define CP0C0_BE 15
197#define CP0C0_AT 13
198#define CP0C0_AR 10
199#define CP0C0_MT 7
200#define CP0C0_VI 3
201#define CP0C0_K0 0
202
203/* Config1 register bits */
204#define CP0C1_M 31
205#define CP0C1_MMU 25
206#define CP0C1_IS 22
207#define CP0C1_IL 19
208#define CP0C1_IA 16
209#define CP0C1_DS 13
210#define CP0C1_DL 10
211#define CP0C1_DA 7
212#define CP0C1_C2 6
213#define CP0C1_MD 5
214#define CP0C1_PC 4
215#define CP0C1_WR 3
216#define CP0C1_CA 2
217#define CP0C1_EP 1
218#define CP0C1_FP 0
219
220/* Config2 Register bits */
221#define CP0C2_M 31
222#define CP0C2_TU 28
223#define CP0C2_TS 24
224#define CP0C2_TL 20
225#define CP0C2_TA 16
226#define CP0C2_SU 12
227#define CP0C2_SS 8
228#define CP0C2_SL 4
229#define CP0C2_SA 0
230
231/* Config3 Register bits */
232#define CP0C3_M 31
233#define CP0C3_ISA_ON_EXC 16
234#define CP0C3_ULRI 13
235#define CP0C3_DSPP 10
236#define CP0C3_LPA 7
237#define CP0C3_VEIC 6
238#define CP0C3_VInt 5
239#define CP0C3_SP 4
240#define CP0C3_MT 2
241#define CP0C3_SM 1
242#define CP0C3_TL 0
243
244/* Have config1, Cacheable, noncoherent, write-back, write allocate*/
245#define MIPS_CONFIG0 \
246 ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
247
248/* Have config2, no coprocessor2 attached, no MDMX support attached,
249 no performance counters, watch registers present,
250 no code compression, EJTAG present, no FPU, no watch registers */
251#define MIPS_CONFIG1 \
252((1 << CP0C1_M) | \
253 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
254 (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
255 (0 << CP0C1_FP))
256
257/* Have config3, no tertiary/secondary caches implemented */
258#define MIPS_CONFIG2 \
259((1 << CP0C2_M))
260
261/* No config4, no DSP ASE, no large physaddr (PABITS),
262 no external interrupt controller, no vectored interrupts,
263 no 1kb pages, no SmartMIPS ASE, no trace logic */
264#define MIPS_CONFIG3 \
265((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
266 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
267 (0 << CP0C3_SM) | (0 << CP0C3_TL))
268
269/* MMU types, the first four entries have the same layout as the
270 CP0C0_MT field. */
271enum mips_mmu_types {
272 MMU_TYPE_NONE,
273 MMU_TYPE_R4000,
274 MMU_TYPE_RESERVED,
275 MMU_TYPE_FMT,
276 MMU_TYPE_R3000,
277 MMU_TYPE_R6000,
278 MMU_TYPE_R8000
279};
280
281/*
282 * Trap codes
283 */
284#define T_INT 0 /* Interrupt pending */
285#define T_TLB_MOD 1 /* TLB modified fault */
286#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
287#define T_TLB_ST_MISS 3 /* TLB miss on a store */
288#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
289#define T_ADDR_ERR_ST 5 /* Address error on a store */
290#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
291#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
292#define T_SYSCALL 8 /* System call */
293#define T_BREAK 9 /* Breakpoint */
294#define T_RES_INST 10 /* Reserved instruction exception */
295#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
296#define T_OVFLOW 12 /* Arithmetic overflow */
297
298/*
299 * Trap definitions added for r4000 port.
300 */
301#define T_TRAP 13 /* Trap instruction */
302#define T_VCEI 14 /* Virtual coherency exception */
303#define T_FPE 15 /* Floating point exception */
304#define T_WATCH 23 /* Watch address reference */
305#define T_VCED 31 /* Virtual coherency data */
306
307/* Resume Flags */
308#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
309#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
310
311#define RESUME_GUEST 0
312#define RESUME_GUEST_DR RESUME_FLAG_DR
313#define RESUME_HOST RESUME_FLAG_HOST
314
315enum emulation_result {
316 EMULATE_DONE, /* no further processing */
317 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
318 EMULATE_FAIL, /* can't emulate this instruction */
319 EMULATE_WAIT, /* WAIT instruction */
320 EMULATE_PRIV_FAIL,
321};
322
323#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
324#define MIPS3_PG_V 0x00000002 /* Valid */
325#define MIPS3_PG_NV 0x00000000
326#define MIPS3_PG_D 0x00000004 /* Dirty */
327
328#define mips3_paddr_to_tlbpfn(x) \
329 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
330#define mips3_tlbpfn_to_paddr(x) \
331 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
332
333#define MIPS3_PG_SHIFT 6
334#define MIPS3_PG_FRAME 0x3fffffc0
335
336#define VPN2_MASK 0xffffe000
337#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
338#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
339#define TLB_ASID(x) (ASID_MASK((x).tlb_hi))
340#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
341
342struct kvm_mips_tlb {
343 long tlb_mask;
344 long tlb_hi;
345 long tlb_lo0;
346 long tlb_lo1;
347};
348
349#define KVM_MIPS_GUEST_TLB_SIZE 64
350struct kvm_vcpu_arch {
351 void *host_ebase, *guest_ebase;
352 unsigned long host_stack;
353 unsigned long host_gp;
354
355 /* Host CP0 registers used when handling exits from guest */
356 unsigned long host_cp0_badvaddr;
357 unsigned long host_cp0_cause;
358 unsigned long host_cp0_epc;
359 unsigned long host_cp0_entryhi;
360 uint32_t guest_inst;
361
362 /* GPRS */
363 unsigned long gprs[32];
364 unsigned long hi;
365 unsigned long lo;
366 unsigned long pc;
367
368 /* FPU State */
369 struct mips_fpu_struct fpu;
370
371 /* COP0 State */
372 struct mips_coproc *cop0;
373
374 /* Host KSEG0 address of the EI/DI offset */
375 void *kseg0_commpage;
376
377 u32 io_gpr; /* GPR used as IO source/target */
378
379 /* Used to calibrate the virutal count register for the guest */
380 int32_t host_cp0_count;
381
382 /* Bitmask of exceptions that are pending */
383 unsigned long pending_exceptions;
384
385 /* Bitmask of pending exceptions to be cleared */
386 unsigned long pending_exceptions_clr;
387
388 unsigned long pending_load_cause;
389
390 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
391 unsigned long preempt_entryhi;
392
393 /* S/W Based TLB for guest */
394 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
395
396 /* Cached guest kernel/user ASIDs */
397 uint32_t guest_user_asid[NR_CPUS];
398 uint32_t guest_kernel_asid[NR_CPUS];
399 struct mm_struct guest_kernel_mm, guest_user_mm;
400
401 struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
402
403
404 struct hrtimer comparecount_timer;
405
406 int last_sched_cpu;
407
408 /* WAIT executed */
409 int wait;
410};
411
412
413#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
414#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
415#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
416#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
417#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
418#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
419#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
420#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
421#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
422#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
423#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
424#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
425#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
426#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
427#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
428#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
429#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
430#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
431#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
432#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
433#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
434#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
435#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
436#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
437#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
438#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
439#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
440#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
441#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
442#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
443#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
444#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
445#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
446#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
447#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
448#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
449#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
450#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
451#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
452#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
453#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
454#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
455#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
456
457#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
458#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
459#define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
460#define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
461#define kvm_change_c0_guest_cause(cop0, change, val) \
462{ \
463 kvm_clear_c0_guest_cause(cop0, change); \
464 kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
465}
466#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
467#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
468#define kvm_change_c0_guest_ebase(cop0, change, val) \
469{ \
470 kvm_clear_c0_guest_ebase(cop0, change); \
471 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
472}
473
474
475struct kvm_mips_callbacks {
476 int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
477 int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
478 int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
479 int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
480 int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
481 int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
482 int (*handle_syscall) (struct kvm_vcpu *vcpu);
483 int (*handle_res_inst) (struct kvm_vcpu *vcpu);
484 int (*handle_break) (struct kvm_vcpu *vcpu);
485 int (*vm_init) (struct kvm *kvm);
486 int (*vcpu_init) (struct kvm_vcpu *vcpu);
487 int (*vcpu_setup) (struct kvm_vcpu *vcpu);
488 gpa_t(*gva_to_gpa) (gva_t gva);
489 void (*queue_timer_int) (struct kvm_vcpu *vcpu);
490 void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
491 void (*queue_io_int) (struct kvm_vcpu *vcpu,
492 struct kvm_mips_interrupt *irq);
493 void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
494 struct kvm_mips_interrupt *irq);
495 int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
496 uint32_t cause);
497 int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
498 uint32_t cause);
499 int (*vcpu_ioctl_get_regs) (struct kvm_vcpu *vcpu,
500 struct kvm_regs *regs);
501 int (*vcpu_ioctl_set_regs) (struct kvm_vcpu *vcpu,
502 struct kvm_regs *regs);
503};
504extern struct kvm_mips_callbacks *kvm_mips_callbacks;
505int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
506
507/* Debug: dump vcpu state */
508int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
509
510/* Trampoline ASM routine to start running in "Guest" context */
511extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
512
513/* TLB handling */
514uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
515
516uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
517
518uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
519
520extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
521 struct kvm_vcpu *vcpu);
522
523extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
524 struct kvm_vcpu *vcpu);
525
526extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
527 struct kvm_mips_tlb *tlb,
528 unsigned long *hpa0,
529 unsigned long *hpa1);
530
531extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
532 uint32_t *opc,
533 struct kvm_run *run,
534 struct kvm_vcpu *vcpu);
535
536extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
537 uint32_t *opc,
538 struct kvm_run *run,
539 struct kvm_vcpu *vcpu);
540
541extern void kvm_mips_dump_host_tlbs(void);
542extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
543extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
544extern void kvm_mips_flush_host_tlb(int skip_kseg0);
545extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
546extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
547
548extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
549 unsigned long entryhi);
550extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
551extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
552 unsigned long gva);
553extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
554 struct kvm_vcpu *vcpu);
555extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
556extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
557extern void kvm_local_flush_tlb_all(void);
558extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
559extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
560extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
561extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
562
563/* Emulation */
564uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
565enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
566
567extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
568 uint32_t *opc,
569 struct kvm_run *run,
570 struct kvm_vcpu *vcpu);
571
572extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
573 uint32_t *opc,
574 struct kvm_run *run,
575 struct kvm_vcpu *vcpu);
576
577extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
578 uint32_t *opc,
579 struct kvm_run *run,
580 struct kvm_vcpu *vcpu);
581
582extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
583 uint32_t *opc,
584 struct kvm_run *run,
585 struct kvm_vcpu *vcpu);
586
587extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
588 uint32_t *opc,
589 struct kvm_run *run,
590 struct kvm_vcpu *vcpu);
591
592extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
593 uint32_t *opc,
594 struct kvm_run *run,
595 struct kvm_vcpu *vcpu);
596
597extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
598 uint32_t *opc,
599 struct kvm_run *run,
600 struct kvm_vcpu *vcpu);
601
602extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
603 uint32_t *opc,
604 struct kvm_run *run,
605 struct kvm_vcpu *vcpu);
606
607extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
608 uint32_t *opc,
609 struct kvm_run *run,
610 struct kvm_vcpu *vcpu);
611
612extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
613 uint32_t *opc,
614 struct kvm_run *run,
615 struct kvm_vcpu *vcpu);
616
617extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
618 uint32_t *opc,
619 struct kvm_run *run,
620 struct kvm_vcpu *vcpu);
621
622extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
623 struct kvm_run *run);
624
625enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
626
627enum emulation_result kvm_mips_check_privilege(unsigned long cause,
628 uint32_t *opc,
629 struct kvm_run *run,
630 struct kvm_vcpu *vcpu);
631
632enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
633 uint32_t *opc,
634 uint32_t cause,
635 struct kvm_run *run,
636 struct kvm_vcpu *vcpu);
637enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
638 uint32_t *opc,
639 uint32_t cause,
640 struct kvm_run *run,
641 struct kvm_vcpu *vcpu);
642enum emulation_result kvm_mips_emulate_store(uint32_t inst,
643 uint32_t cause,
644 struct kvm_run *run,
645 struct kvm_vcpu *vcpu);
646enum emulation_result kvm_mips_emulate_load(uint32_t inst,
647 uint32_t cause,
648 struct kvm_run *run,
649 struct kvm_vcpu *vcpu);
650
651/* Dynamic binary translation */
652extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
653 struct kvm_vcpu *vcpu);
654extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
655 struct kvm_vcpu *vcpu);
656extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
657 struct kvm_vcpu *vcpu);
658extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
659 struct kvm_vcpu *vcpu);
660
661/* Misc */
662extern void mips32_SyncICache(unsigned long addr, unsigned long size);
663extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
664extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
665
666
667#endif /* __MIPS_KVM_HOST_H__ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
deleted file mode 100644
index 8fcf8df4418a..000000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef BCM63XX_CLK_H_
2#define BCM63XX_CLK_H_
3
4struct clk {
5 void (*set)(struct clk *, int);
6 unsigned int rate;
7 unsigned int usage;
8 int id;
9};
10
11#endif /* ! BCM63XX_CLK_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index cb922b9cb0e9..336228990808 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -14,11 +14,12 @@
14#define BCM6345_CPU_ID 0x6345 14#define BCM6345_CPU_ID 0x6345
15#define BCM6348_CPU_ID 0x6348 15#define BCM6348_CPU_ID 0x6348
16#define BCM6358_CPU_ID 0x6358 16#define BCM6358_CPU_ID 0x6358
17#define BCM6362_CPU_ID 0x6362
17#define BCM6368_CPU_ID 0x6368 18#define BCM6368_CPU_ID 0x6368
18 19
19void __init bcm63xx_cpu_init(void); 20void __init bcm63xx_cpu_init(void);
20u16 __bcm63xx_get_cpu_id(void); 21u16 __bcm63xx_get_cpu_id(void);
21u16 bcm63xx_get_cpu_rev(void); 22u8 bcm63xx_get_cpu_rev(void);
22unsigned int bcm63xx_get_cpu_freq(void); 23unsigned int bcm63xx_get_cpu_freq(void);
23 24
24#ifdef CONFIG_BCM63XX_CPU_6328 25#ifdef CONFIG_BCM63XX_CPU_6328
@@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
86# define BCMCPU_IS_6358() (0) 87# define BCMCPU_IS_6358() (0)
87#endif 88#endif
88 89
90#ifdef CONFIG_BCM63XX_CPU_6362
91# ifdef bcm63xx_get_cpu_id
92# undef bcm63xx_get_cpu_id
93# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
94# define BCMCPU_RUNTIME_DETECT
95# else
96# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
97# endif
98# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
99#else
100# define BCMCPU_IS_6362() (0)
101#endif
102
103
89#ifdef CONFIG_BCM63XX_CPU_6368 104#ifdef CONFIG_BCM63XX_CPU_6368
90# ifdef bcm63xx_get_cpu_id 105# ifdef bcm63xx_get_cpu_id
91# undef bcm63xx_get_cpu_id 106# undef bcm63xx_get_cpu_id
@@ -406,6 +421,62 @@ enum bcm63xx_regs_set {
406 421
407 422
408/* 423/*
424 * 6362 register sets base address
425 */
426#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
427#define BCM_6362_PERF_BASE (0xb0000000)
428#define BCM_6362_TIMER_BASE (0xb0000040)
429#define BCM_6362_WDT_BASE (0xb000005c)
430#define BCM_6362_UART0_BASE (0xb0000100)
431#define BCM_6362_UART1_BASE (0xb0000120)
432#define BCM_6362_GPIO_BASE (0xb0000080)
433#define BCM_6362_SPI_BASE (0xb0000800)
434#define BCM_6362_HSSPI_BASE (0xb0001000)
435#define BCM_6362_UDC0_BASE (0xdeadbeef)
436#define BCM_6362_USBDMA_BASE (0xb000c000)
437#define BCM_6362_OHCI0_BASE (0xb0002600)
438#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
439#define BCM_6362_USBH_PRIV_BASE (0xb0002700)
440#define BCM_6362_USBD_BASE (0xb0002400)
441#define BCM_6362_MPI_BASE (0xdeadbeef)
442#define BCM_6362_PCMCIA_BASE (0xdeadbeef)
443#define BCM_6362_PCIE_BASE (0xb0e40000)
444#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
445#define BCM_6362_DSL_BASE (0xdeadbeef)
446#define BCM_6362_UBUS_BASE (0xdeadbeef)
447#define BCM_6362_ENET0_BASE (0xdeadbeef)
448#define BCM_6362_ENET1_BASE (0xdeadbeef)
449#define BCM_6362_ENETDMA_BASE (0xb000d800)
450#define BCM_6362_ENETDMAC_BASE (0xb000da00)
451#define BCM_6362_ENETDMAS_BASE (0xb000dc00)
452#define BCM_6362_ENETSW_BASE (0xb0e00000)
453#define BCM_6362_EHCI0_BASE (0xb0002500)
454#define BCM_6362_SDRAM_BASE (0xdeadbeef)
455#define BCM_6362_MEMC_BASE (0xdeadbeef)
456#define BCM_6362_DDR_BASE (0xb0003000)
457#define BCM_6362_M2M_BASE (0xdeadbeef)
458#define BCM_6362_ATM_BASE (0xdeadbeef)
459#define BCM_6362_XTM_BASE (0xb0007800)
460#define BCM_6362_XTMDMA_BASE (0xb000b800)
461#define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
462#define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
463#define BCM_6362_PCM_BASE (0xb000a800)
464#define BCM_6362_PCMDMA_BASE (0xdeadbeef)
465#define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
466#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
467#define BCM_6362_RNG_BASE (0xdeadbeef)
468#define BCM_6362_MISC_BASE (0xb0001800)
469
470#define BCM_6362_NAND_REG_BASE (0xb0000200)
471#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
472#define BCM_6362_LED_BASE (0xb0001900)
473#define BCM_6362_IPSEC_BASE (0xb0002800)
474#define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
475#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
476#define BCM_6362_WLAN_D11_BASE (0xb0005000)
477#define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
478
479/*
409 * 6368 register sets base address 480 * 6368 register sets base address
410 */ 481 */
411#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) 482#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
@@ -564,6 +635,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
564#ifdef CONFIG_BCM63XX_CPU_6358 635#ifdef CONFIG_BCM63XX_CPU_6358
565 __GEN_RSET(6358) 636 __GEN_RSET(6358)
566#endif 637#endif
638#ifdef CONFIG_BCM63XX_CPU_6362
639 __GEN_RSET(6362)
640#endif
567#ifdef CONFIG_BCM63XX_CPU_6368 641#ifdef CONFIG_BCM63XX_CPU_6368
568 __GEN_RSET(6368) 642 __GEN_RSET(6368)
569#endif 643#endif
@@ -820,6 +894,71 @@ enum bcm63xx_irq {
820#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 894#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
821 895
822/* 896/*
897 * 6362 irqs
898 */
899#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
900
901#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
902#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
903#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
904#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
905#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
906#define BCM_6362_UDC0_IRQ 0
907#define BCM_6362_ENET0_IRQ 0
908#define BCM_6362_ENET1_IRQ 0
909#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
910#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
911#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
912#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
913#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
914#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
915#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
916#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
917#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
918#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
919#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
920#define BCM_6362_PCMCIA_IRQ 0
921#define BCM_6362_ENET0_RXDMA_IRQ 0
922#define BCM_6362_ENET0_TXDMA_IRQ 0
923#define BCM_6362_ENET1_RXDMA_IRQ 0
924#define BCM_6362_ENET1_TXDMA_IRQ 0
925#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
926#define BCM_6362_ATM_IRQ 0
927#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
928#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1)
929#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2)
930#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3)
931#define BCM_6362_ENETSW_TXDMA0_IRQ 0
932#define BCM_6362_ENETSW_TXDMA1_IRQ 0
933#define BCM_6362_ENETSW_TXDMA2_IRQ 0
934#define BCM_6362_ENETSW_TXDMA3_IRQ 0
935#define BCM_6362_XTM_IRQ 0
936#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12)
937
938#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
939#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
940#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
941#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
942#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
943#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
944#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
945#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
946#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
947#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
948#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
949#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
950#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
951#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
952#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4)
953#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5)
954#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6)
955#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7)
956#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8)
957#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9)
958#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10)
959#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11)
960
961/*
823 * 6368 irqs 962 * 6368 irqs
824 */ 963 */
825#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 964#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
index b0184cf02575..c426cabc620a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -71,18 +71,13 @@ static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
71 71
72 return bcm63xx_regs_spi[reg]; 72 return bcm63xx_regs_spi[reg];
73#else 73#else
74#ifdef CONFIG_BCM63XX_CPU_6338 74#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
75 __GEN_SPI_RSET(6338)
76#endif
77#ifdef CONFIG_BCM63XX_CPU_6348
78 __GEN_SPI_RSET(6348) 75 __GEN_SPI_RSET(6348)
79#endif 76#endif
80#ifdef CONFIG_BCM63XX_CPU_6358 77#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
78 defined(CONFIG_BCM63XX_CPU_6368)
81 __GEN_SPI_RSET(6358) 79 __GEN_SPI_RSET(6358)
82#endif 80#endif
83#ifdef CONFIG_BCM63XX_CPU_6368
84 __GEN_SPI_RSET(6368)
85#endif
86#endif 81#endif
87 return 0; 82 return 0;
88} 83}
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 0a9891f7580d..35baa1a60a64 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
17 return 8; 17 return 8;
18 case BCM6345_CPU_ID: 18 case BCM6345_CPU_ID:
19 return 16; 19 return 16;
20 case BCM6362_CPU_ID:
21 return 48;
20 case BCM6368_CPU_ID: 22 case BCM6368_CPU_ID:
21 return 38; 23 return 38;
22 case BCM6348_CPU_ID: 24 case BCM6348_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 81b4702f792a..3203fe49b34d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -10,7 +10,7 @@
10#define REV_CHIPID_SHIFT 16 10#define REV_CHIPID_SHIFT 16
11#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 11#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12#define REV_REVID_SHIFT 0 12#define REV_REVID_SHIFT 0
13#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) 13#define REV_REVID_MASK (0xff << REV_REVID_SHIFT)
14 14
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
@@ -112,6 +112,39 @@
112 CKCTL_6358_USBSU_EN | \ 112 CKCTL_6358_USBSU_EN | \
113 CKCTL_6358_EPHY_EN) 113 CKCTL_6358_EPHY_EN)
114 114
115#define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
116#define CKCTL_6362_ADSL_AFE_EN (1 << 2)
117#define CKCTL_6362_ADSL_EN (1 << 3)
118#define CKCTL_6362_MIPS_EN (1 << 4)
119#define CKCTL_6362_WLAN_OCP_EN (1 << 5)
120#define CKCTL_6362_SWPKT_USB_EN (1 << 7)
121#define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
122#define CKCTL_6362_SAR_EN (1 << 9)
123#define CKCTL_6362_ROBOSW_EN (1 << 10)
124#define CKCTL_6362_PCM_EN (1 << 11)
125#define CKCTL_6362_USBD_EN (1 << 12)
126#define CKCTL_6362_USBH_EN (1 << 13)
127#define CKCTL_6362_IPSEC_EN (1 << 14)
128#define CKCTL_6362_SPI_EN (1 << 15)
129#define CKCTL_6362_HSSPI_EN (1 << 16)
130#define CKCTL_6362_PCIE_EN (1 << 17)
131#define CKCTL_6362_FAP_EN (1 << 18)
132#define CKCTL_6362_PHYMIPS_EN (1 << 19)
133#define CKCTL_6362_NAND_EN (1 << 20)
134
135#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
136 CKCTL_6362_ADSL_QPROC_EN | \
137 CKCTL_6362_ADSL_AFE_EN | \
138 CKCTL_6362_ADSL_EN | \
139 CKCTL_6362_SAR_EN | \
140 CKCTL_6362_PCM_EN | \
141 CKCTL_6362_IPSEC_EN | \
142 CKCTL_6362_USBD_EN | \
143 CKCTL_6362_USBH_EN | \
144 CKCTL_6362_ROBOSW_EN | \
145 CKCTL_6362_PCIE_EN)
146
147
115#define CKCTL_6368_VDSL_QPROC_EN (1 << 2) 148#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
116#define CKCTL_6368_VDSL_AFE_EN (1 << 3) 149#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
117#define CKCTL_6368_VDSL_BONDING_EN (1 << 4) 150#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
@@ -153,6 +186,7 @@
153#define PERF_IRQMASK_6345_REG 0xc 186#define PERF_IRQMASK_6345_REG 0xc
154#define PERF_IRQMASK_6348_REG 0xc 187#define PERF_IRQMASK_6348_REG 0xc
155#define PERF_IRQMASK_6358_REG 0xc 188#define PERF_IRQMASK_6358_REG 0xc
189#define PERF_IRQMASK_6362_REG 0x20
156#define PERF_IRQMASK_6368_REG 0x20 190#define PERF_IRQMASK_6368_REG 0x20
157 191
158/* Interrupt Status register */ 192/* Interrupt Status register */
@@ -161,6 +195,7 @@
161#define PERF_IRQSTAT_6345_REG 0x10 195#define PERF_IRQSTAT_6345_REG 0x10
162#define PERF_IRQSTAT_6348_REG 0x10 196#define PERF_IRQSTAT_6348_REG 0x10
163#define PERF_IRQSTAT_6358_REG 0x10 197#define PERF_IRQSTAT_6358_REG 0x10
198#define PERF_IRQSTAT_6362_REG 0x28
164#define PERF_IRQSTAT_6368_REG 0x28 199#define PERF_IRQSTAT_6368_REG 0x28
165 200
166/* External Interrupt Configuration register */ 201/* External Interrupt Configuration register */
@@ -169,6 +204,7 @@
169#define PERF_EXTIRQ_CFG_REG_6345 0x14 204#define PERF_EXTIRQ_CFG_REG_6345 0x14
170#define PERF_EXTIRQ_CFG_REG_6348 0x14 205#define PERF_EXTIRQ_CFG_REG_6348 0x14
171#define PERF_EXTIRQ_CFG_REG_6358 0x14 206#define PERF_EXTIRQ_CFG_REG_6358 0x14
207#define PERF_EXTIRQ_CFG_REG_6362 0x18
172#define PERF_EXTIRQ_CFG_REG_6368 0x18 208#define PERF_EXTIRQ_CFG_REG_6368 0x18
173 209
174#define PERF_EXTIRQ_CFG_REG2_6368 0x1c 210#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
@@ -197,6 +233,7 @@
197#define PERF_SOFTRESET_REG 0x28 233#define PERF_SOFTRESET_REG 0x28
198#define PERF_SOFTRESET_6328_REG 0x10 234#define PERF_SOFTRESET_6328_REG 0x10
199#define PERF_SOFTRESET_6358_REG 0x34 235#define PERF_SOFTRESET_6358_REG 0x34
236#define PERF_SOFTRESET_6362_REG 0x10
200#define PERF_SOFTRESET_6368_REG 0x10 237#define PERF_SOFTRESET_6368_REG 0x10
201 238
202#define SOFTRESET_6328_SPI_MASK (1 << 0) 239#define SOFTRESET_6328_SPI_MASK (1 << 0)
@@ -259,6 +296,22 @@
259#define SOFTRESET_6358_PCM_MASK (1 << 13) 296#define SOFTRESET_6358_PCM_MASK (1 << 13)
260#define SOFTRESET_6358_ADSL_MASK (1 << 14) 297#define SOFTRESET_6358_ADSL_MASK (1 << 14)
261 298
299#define SOFTRESET_6362_SPI_MASK (1 << 0)
300#define SOFTRESET_6362_IPSEC_MASK (1 << 1)
301#define SOFTRESET_6362_EPHY_MASK (1 << 2)
302#define SOFTRESET_6362_SAR_MASK (1 << 3)
303#define SOFTRESET_6362_ENETSW_MASK (1 << 4)
304#define SOFTRESET_6362_USBS_MASK (1 << 5)
305#define SOFTRESET_6362_USBH_MASK (1 << 6)
306#define SOFTRESET_6362_PCM_MASK (1 << 7)
307#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
308#define SOFTRESET_6362_PCIE_MASK (1 << 9)
309#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
310#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
311#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
312#define SOFTRESET_6362_FAP_MASK (1 << 13)
313#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
314
262#define SOFTRESET_6368_SPI_MASK (1 << 0) 315#define SOFTRESET_6368_SPI_MASK (1 << 0)
263#define SOFTRESET_6368_MPI_MASK (1 << 3) 316#define SOFTRESET_6368_MPI_MASK (1 << 3)
264#define SOFTRESET_6368_EPHY_MASK (1 << 6) 317#define SOFTRESET_6368_EPHY_MASK (1 << 6)
@@ -1223,24 +1276,7 @@
1223 * _REG relative to RSET_SPI 1276 * _REG relative to RSET_SPI
1224 *************************************************************************/ 1277 *************************************************************************/
1225 1278
1226/* BCM 6338 SPI core */ 1279/* BCM 6338/6348 SPI core */
1227#define SPI_6338_CMD 0x00 /* 16-bits register */
1228#define SPI_6338_INT_STATUS 0x02
1229#define SPI_6338_INT_MASK_ST 0x03
1230#define SPI_6338_INT_MASK 0x04
1231#define SPI_6338_ST 0x05
1232#define SPI_6338_CLK_CFG 0x06
1233#define SPI_6338_FILL_BYTE 0x07
1234#define SPI_6338_MSG_TAIL 0x09
1235#define SPI_6338_RX_TAIL 0x0b
1236#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1237#define SPI_6338_MSG_CTL_WIDTH 8
1238#define SPI_6338_MSG_DATA 0x41
1239#define SPI_6338_MSG_DATA_SIZE 0x3f
1240#define SPI_6338_RX_DATA 0x80
1241#define SPI_6338_RX_DATA_SIZE 0x3f
1242
1243/* BCM 6348 SPI core */
1244#define SPI_6348_CMD 0x00 /* 16-bits register */ 1280#define SPI_6348_CMD 0x00 /* 16-bits register */
1245#define SPI_6348_INT_STATUS 0x02 1281#define SPI_6348_INT_STATUS 0x02
1246#define SPI_6348_INT_MASK_ST 0x03 1282#define SPI_6348_INT_MASK_ST 0x03
@@ -1257,7 +1293,7 @@
1257#define SPI_6348_RX_DATA 0x80 1293#define SPI_6348_RX_DATA 0x80
1258#define SPI_6348_RX_DATA_SIZE 0x3f 1294#define SPI_6348_RX_DATA_SIZE 0x3f
1259 1295
1260/* BCM 6358 SPI core */ 1296/* BCM 6358/6262/6368 SPI core */
1261#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1297#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1262#define SPI_6358_MSG_CTL_WIDTH 16 1298#define SPI_6358_MSG_CTL_WIDTH 16
1263#define SPI_6358_MSG_DATA 0x02 1299#define SPI_6358_MSG_DATA 0x02
@@ -1274,23 +1310,6 @@
1274#define SPI_6358_MSG_TAIL 0x709 1310#define SPI_6358_MSG_TAIL 0x709
1275#define SPI_6358_RX_TAIL 0x70B 1311#define SPI_6358_RX_TAIL 0x70B
1276 1312
1277/* BCM 6358 SPI core */
1278#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1279#define SPI_6368_MSG_CTL_WIDTH 16
1280#define SPI_6368_MSG_DATA 0x02
1281#define SPI_6368_MSG_DATA_SIZE 0x21e
1282#define SPI_6368_RX_DATA 0x400
1283#define SPI_6368_RX_DATA_SIZE 0x220
1284#define SPI_6368_CMD 0x700 /* 16-bits register */
1285#define SPI_6368_INT_STATUS 0x702
1286#define SPI_6368_INT_MASK_ST 0x703
1287#define SPI_6368_INT_MASK 0x704
1288#define SPI_6368_ST 0x705
1289#define SPI_6368_CLK_CFG 0x706
1290#define SPI_6368_FILL_BYTE 0x707
1291#define SPI_6368_MSG_TAIL 0x709
1292#define SPI_6368_RX_TAIL 0x70B
1293
1294/* Shared SPI definitions */ 1313/* Shared SPI definitions */
1295 1314
1296/* Message configuration */ 1315/* Message configuration */
@@ -1298,10 +1317,8 @@
1298#define SPI_HD_W 0x01 1317#define SPI_HD_W 0x01
1299#define SPI_HD_R 0x02 1318#define SPI_HD_R 0x02
1300#define SPI_BYTE_CNT_SHIFT 0 1319#define SPI_BYTE_CNT_SHIFT 0
1301#define SPI_6338_MSG_TYPE_SHIFT 6
1302#define SPI_6348_MSG_TYPE_SHIFT 6 1320#define SPI_6348_MSG_TYPE_SHIFT 6
1303#define SPI_6358_MSG_TYPE_SHIFT 14 1321#define SPI_6358_MSG_TYPE_SHIFT 14
1304#define SPI_6368_MSG_TYPE_SHIFT 14
1305 1322
1306/* Command */ 1323/* Command */
1307#define SPI_CMD_NOOP 0x00 1324#define SPI_CMD_NOOP 0x00
@@ -1348,10 +1365,18 @@
1348/************************************************************************* 1365/*************************************************************************
1349 * _REG relative to RSET_MISC 1366 * _REG relative to RSET_MISC
1350 *************************************************************************/ 1367 *************************************************************************/
1351#define MISC_SERDES_CTRL_REG 0x0 1368#define MISC_SERDES_CTRL_6328_REG 0x0
1369#define MISC_SERDES_CTRL_6362_REG 0x4
1352#define SERDES_PCIE_EN (1 << 0) 1370#define SERDES_PCIE_EN (1 << 0)
1353#define SERDES_PCIE_EXD_EN (1 << 15) 1371#define SERDES_PCIE_EXD_EN (1 << 15)
1354 1372
1373#define MISC_STRAPBUS_6362_REG 0x14
1374#define STRAPBUS_6362_FCVO_SHIFT 1
1375#define STRAPBUS_6362_HSSPI_CLK_FAST (1 << 13)
1376#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
1377#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
1378#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
1379
1355#define MISC_STRAPBUS_6328_REG 0x240 1380#define MISC_STRAPBUS_6328_REG 0x240
1356#define STRAPBUS_6328_FCVO_SHIFT 7 1381#define STRAPBUS_6328_FCVO_SHIFT 7
1357#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) 1382#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 30931c42379d..94e3011ba7df 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
19 return 1; 19 return 1;
20 break; 20 break;
21 case BCM6328_CPU_ID: 21 case BCM6328_CPU_ID:
22 case BCM6362_CPU_ID:
22 case BCM6368_CPU_ID: 23 case BCM6368_CPU_ID:
23 if (offset >= 0xb0000000 && offset < 0xb1000000) 24 if (offset >= 0xb0000000 && offset < 0xb1000000)
24 return 1; 25 return 1;
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 9c95177f7a7e..fe23034aaf72 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -61,9 +61,8 @@ static inline int plat_device_is_coherent(struct device *dev)
61{ 61{
62#ifdef CONFIG_DMA_COHERENT 62#ifdef CONFIG_DMA_COHERENT
63 return 1; 63 return 1;
64#endif 64#else
65#ifdef CONFIG_DMA_NONCOHERENT 65 return coherentio;
66 return 0;
67#endif 66#endif
68} 67}
69 68
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 73d717a75cb0..5b2f2e68e57f 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -20,14 +20,21 @@
20#endif 20#endif
21 21
22#ifdef CONFIG_32BIT 22#ifdef CONFIG_32BIT
23 23#ifdef CONFIG_KVM_GUEST
24#define CAC_BASE _AC(0x40000000, UL)
25#else
24#define CAC_BASE _AC(0x80000000, UL) 26#define CAC_BASE _AC(0x80000000, UL)
27#endif
25#define IO_BASE _AC(0xa0000000, UL) 28#define IO_BASE _AC(0xa0000000, UL)
26#define UNCAC_BASE _AC(0xa0000000, UL) 29#define UNCAC_BASE _AC(0xa0000000, UL)
27 30
28#ifndef MAP_BASE 31#ifndef MAP_BASE
32#ifdef CONFIG_KVM_GUEST
33#define MAP_BASE _AC(0x60000000, UL)
34#else
29#define MAP_BASE _AC(0xc0000000, UL) 35#define MAP_BASE _AC(0xc0000000, UL)
30#endif 36#endif
37#endif
31 38
32/* 39/*
33 * Memory above this physical address will be considered highmem. 40 * Memory above this physical address will be considered highmem.
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 75fd8c0f986e..c0f3ef45c2c1 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -57,5 +57,6 @@
57#define cpu_has_vint 0 57#define cpu_has_vint 0
58#define cpu_has_vtag_icache 0 58#define cpu_has_vtag_icache 0
59#define cpu_has_watch 1 59#define cpu_has_watch 1
60#define cpu_has_local_ebase 0
60 61
61#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ 62#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
new file mode 100644
index 000000000000..9809972ea882
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -0,0 +1,84 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#ifndef _MT7620_REGS_H_
14#define _MT7620_REGS_H_
15
16#define MT7620_SYSC_BASE 0x10000000
17
18#define SYSC_REG_CHIP_NAME0 0x00
19#define SYSC_REG_CHIP_NAME1 0x04
20#define SYSC_REG_CHIP_REV 0x0c
21#define SYSC_REG_SYSTEM_CONFIG0 0x10
22#define SYSC_REG_SYSTEM_CONFIG1 0x14
23#define SYSC_REG_CPLL_CONFIG0 0x54
24#define SYSC_REG_CPLL_CONFIG1 0x58
25
26#define MT7620N_CHIP_NAME0 0x33365452
27#define MT7620N_CHIP_NAME1 0x20203235
28
29#define MT7620A_CHIP_NAME0 0x3637544d
30#define MT7620A_CHIP_NAME1 0x20203032
31
32#define CHIP_REV_PKG_MASK 0x1
33#define CHIP_REV_PKG_SHIFT 16
34#define CHIP_REV_VER_MASK 0xf
35#define CHIP_REV_VER_SHIFT 8
36#define CHIP_REV_ECO_MASK 0xf
37
38#define CPLL_SW_CONFIG_SHIFT 31
39#define CPLL_SW_CONFIG_MASK 0x1
40#define CPLL_CPU_CLK_SHIFT 24
41#define CPLL_CPU_CLK_MASK 0x1
42#define CPLL_MULT_RATIO_SHIFT 16
43#define CPLL_MULT_RATIO 0x7
44#define CPLL_DIV_RATIO_SHIFT 10
45#define CPLL_DIV_RATIO 0x3
46
47#define SYSCFG0_DRAM_TYPE_MASK 0x3
48#define SYSCFG0_DRAM_TYPE_SHIFT 4
49#define SYSCFG0_DRAM_TYPE_SDRAM 0
50#define SYSCFG0_DRAM_TYPE_DDR1 1
51#define SYSCFG0_DRAM_TYPE_DDR2 2
52
53#define MT7620_DRAM_BASE 0x0
54#define MT7620_SDRAM_SIZE_MIN 2
55#define MT7620_SDRAM_SIZE_MAX 64
56#define MT7620_DDR1_SIZE_MIN 32
57#define MT7620_DDR1_SIZE_MAX 128
58#define MT7620_DDR2_SIZE_MIN 32
59#define MT7620_DDR2_SIZE_MAX 256
60
61#define MT7620_GPIO_MODE_I2C BIT(0)
62#define MT7620_GPIO_MODE_UART0_SHIFT 2
63#define MT7620_GPIO_MODE_UART0_MASK 0x7
64#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
65#define MT7620_GPIO_MODE_UARTF 0x0
66#define MT7620_GPIO_MODE_PCM_UARTF 0x1
67#define MT7620_GPIO_MODE_PCM_I2S 0x2
68#define MT7620_GPIO_MODE_I2S_UARTF 0x3
69#define MT7620_GPIO_MODE_PCM_GPIO 0x4
70#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
71#define MT7620_GPIO_MODE_GPIO_I2S 0x6
72#define MT7620_GPIO_MODE_GPIO 0x7
73#define MT7620_GPIO_MODE_UART1 BIT(5)
74#define MT7620_GPIO_MODE_MDIO BIT(8)
75#define MT7620_GPIO_MODE_RGMII1 BIT(9)
76#define MT7620_GPIO_MODE_RGMII2 BIT(10)
77#define MT7620_GPIO_MODE_SPI BIT(11)
78#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
79#define MT7620_GPIO_MODE_WLED BIT(13)
80#define MT7620_GPIO_MODE_JTAG BIT(15)
81#define MT7620_GPIO_MODE_EPHY BIT(15)
82#define MT7620_GPIO_MODE_WDT BIT(22)
83
84#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
new file mode 100644
index 000000000000..03ad716acb42
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -0,0 +1,53 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#ifndef _RT288X_REGS_H_
14#define _RT288X_REGS_H_
15
16#define RT2880_SYSC_BASE 0x00300000
17
18#define SYSC_REG_CHIP_NAME0 0x00
19#define SYSC_REG_CHIP_NAME1 0x04
20#define SYSC_REG_CHIP_ID 0x0c
21#define SYSC_REG_SYSTEM_CONFIG 0x10
22#define SYSC_REG_CLKCFG 0x30
23
24#define RT2880_CHIP_NAME0 0x38325452
25#define RT2880_CHIP_NAME1 0x20203038
26
27#define CHIP_ID_ID_MASK 0xff
28#define CHIP_ID_ID_SHIFT 8
29#define CHIP_ID_REV_MASK 0xff
30
31#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
32#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
33#define SYSTEM_CONFIG_CPUCLK_250 0x0
34#define SYSTEM_CONFIG_CPUCLK_266 0x1
35#define SYSTEM_CONFIG_CPUCLK_280 0x2
36#define SYSTEM_CONFIG_CPUCLK_300 0x3
37
38#define RT2880_GPIO_MODE_I2C BIT(0)
39#define RT2880_GPIO_MODE_UART0 BIT(1)
40#define RT2880_GPIO_MODE_SPI BIT(2)
41#define RT2880_GPIO_MODE_UART1 BIT(3)
42#define RT2880_GPIO_MODE_JTAG BIT(4)
43#define RT2880_GPIO_MODE_MDIO BIT(5)
44#define RT2880_GPIO_MODE_SDRAM BIT(6)
45#define RT2880_GPIO_MODE_PCI BIT(7)
46
47#define CLKCFG_SRAM_CS_N_WDT BIT(9)
48
49#define RT2880_SDRAM_BASE 0x08000000
50#define RT2880_MEM_SIZE_MIN 2
51#define RT2880_MEM_SIZE_MAX 128
52
53#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
new file mode 100644
index 000000000000..72fc10669199
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
1/*
2 * Ralink RT288x specific CPU feature overrides
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This file was derived from: include/asm-mips/cpu-features.h
8 * Copyright (C) 2003, 2004 Ralf Baechle
9 * Copyright (C) 2004 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 *
15 */
16#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
17#define _RT288X_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_has_tlb 1
20#define cpu_has_4kex 1
21#define cpu_has_3k_cache 0
22#define cpu_has_4k_cache 1
23#define cpu_has_tx39_cache 0
24#define cpu_has_sb1_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_32fpr 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30
31#define cpu_has_prefetch 1
32#define cpu_has_ejtag 1
33#define cpu_has_llsc 1
34
35#define cpu_has_mips16 1
36#define cpu_has_mdmx 0
37#define cpu_has_mips3d 0
38#define cpu_has_smartmips 0
39
40#define cpu_has_mips32r1 1
41#define cpu_has_mips32r2 1
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
45#define cpu_has_dsp 0
46#define cpu_has_mipsmt 0
47
48#define cpu_has_64bits 0
49#define cpu_has_64bit_zero_reg 0
50#define cpu_has_64bit_gp_regs 0
51#define cpu_has_64bit_addresses 0
52
53#define cpu_dcache_line_size() 16
54#define cpu_icache_line_size() 16
55
56#endif /* _RT288X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 7d344f2d7d0a..069bf37a6010 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -97,6 +97,14 @@ static inline int soc_is_rt5350(void)
97#define RT5350_SYSCFG0_CPUCLK_320 0x2 97#define RT5350_SYSCFG0_CPUCLK_320 0x2
98#define RT5350_SYSCFG0_CPUCLK_300 0x3 98#define RT5350_SYSCFG0_CPUCLK_300 0x3
99 99
100#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
101#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
102#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
103#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
104#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
105#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
106#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
107
100/* multi function gpio pins */ 108/* multi function gpio pins */
101#define RT305X_GPIO_I2C_SD 1 109#define RT305X_GPIO_I2C_SD 1
102#define RT305X_GPIO_I2C_SCLK 2 110#define RT305X_GPIO_I2C_SCLK 2
@@ -136,4 +144,23 @@ static inline int soc_is_rt5350(void)
136#define RT305X_GPIO_MODE_SDRAM BIT(8) 144#define RT305X_GPIO_MODE_SDRAM BIT(8)
137#define RT305X_GPIO_MODE_RGMII BIT(9) 145#define RT305X_GPIO_MODE_RGMII BIT(9)
138 146
147#define RT3352_SYSC_REG_SYSCFG0 0x010
148#define RT3352_SYSC_REG_SYSCFG1 0x014
149#define RT3352_SYSC_REG_CLKCFG1 0x030
150#define RT3352_SYSC_REG_RSTCTRL 0x034
151#define RT3352_SYSC_REG_USB_PS 0x05c
152
153#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
154#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
155#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
156#define RT3352_RSTCTRL_UHST BIT(22)
157#define RT3352_RSTCTRL_UDEV BIT(25)
158#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
159
160#define RT305X_SDRAM_BASE 0x00000000
161#define RT305X_MEM_SIZE_MIN 2
162#define RT305X_MEM_SIZE_MAX 64
163#define RT3352_MEM_SIZE_MIN 2
164#define RT3352_MEM_SIZE_MAX 256
165
139#endif 166#endif
diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
new file mode 100644
index 000000000000..917c28654552
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
@@ -0,0 +1,56 @@
1/*
2 * Ralink RT305x specific CPU feature overrides
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This file was derived from: include/asm-mips/cpu-features.h
8 * Copyright (C) 2003, 2004 Ralf Baechle
9 * Copyright (C) 2004 Maciej W. Rozycki
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 *
15 */
16#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
17#define _RT305X_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_has_tlb 1
20#define cpu_has_4kex 1
21#define cpu_has_3k_cache 0
22#define cpu_has_4k_cache 1
23#define cpu_has_tx39_cache 0
24#define cpu_has_sb1_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_32fpr 0
27#define cpu_has_counter 1
28#define cpu_has_watch 1
29#define cpu_has_divec 1
30
31#define cpu_has_prefetch 1
32#define cpu_has_ejtag 1
33#define cpu_has_llsc 1
34
35#define cpu_has_mips16 1
36#define cpu_has_mdmx 0
37#define cpu_has_mips3d 0
38#define cpu_has_smartmips 0
39
40#define cpu_has_mips32r1 1
41#define cpu_has_mips32r2 1
42#define cpu_has_mips64r1 0
43#define cpu_has_mips64r2 0
44
45#define cpu_has_dsp 1
46#define cpu_has_mipsmt 0
47
48#define cpu_has_64bits 0
49#define cpu_has_64bit_zero_reg 0
50#define cpu_has_64bit_gp_regs 0
51#define cpu_has_64bit_addresses 0
52
53#define cpu_dcache_line_size() 32
54#define cpu_icache_line_size() 32
55
56#endif /* _RT305X_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
new file mode 100644
index 000000000000..058382f37f92
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -0,0 +1,252 @@
1/*
2 * Ralink RT3662/RT3883 SoC register definitions
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _RT3883_REGS_H_
12#define _RT3883_REGS_H_
13
14#include <linux/bitops.h>
15
16#define RT3883_SDRAM_BASE 0x00000000
17#define RT3883_SYSC_BASE 0x10000000
18#define RT3883_TIMER_BASE 0x10000100
19#define RT3883_INTC_BASE 0x10000200
20#define RT3883_MEMC_BASE 0x10000300
21#define RT3883_UART0_BASE 0x10000500
22#define RT3883_PIO_BASE 0x10000600
23#define RT3883_FSCC_BASE 0x10000700
24#define RT3883_NANDC_BASE 0x10000810
25#define RT3883_I2C_BASE 0x10000900
26#define RT3883_I2S_BASE 0x10000a00
27#define RT3883_SPI_BASE 0x10000b00
28#define RT3883_UART1_BASE 0x10000c00
29#define RT3883_PCM_BASE 0x10002000
30#define RT3883_GDMA_BASE 0x10002800
31#define RT3883_CODEC1_BASE 0x10003000
32#define RT3883_CODEC2_BASE 0x10003800
33#define RT3883_FE_BASE 0x10100000
34#define RT3883_ROM_BASE 0x10118000
35#define RT3883_USBDEV_BASE 0x10112000
36#define RT3883_PCI_BASE 0x10140000
37#define RT3883_WLAN_BASE 0x10180000
38#define RT3883_USBHOST_BASE 0x101c0000
39#define RT3883_BOOT_BASE 0x1c000000
40#define RT3883_SRAM_BASE 0x1e000000
41#define RT3883_PCIMEM_BASE 0x20000000
42
43#define RT3883_EHCI_BASE (RT3883_USBHOST_BASE)
44#define RT3883_OHCI_BASE (RT3883_USBHOST_BASE + 0x1000)
45
46#define RT3883_SYSC_SIZE 0x100
47#define RT3883_TIMER_SIZE 0x100
48#define RT3883_INTC_SIZE 0x100
49#define RT3883_MEMC_SIZE 0x100
50#define RT3883_UART0_SIZE 0x100
51#define RT3883_UART1_SIZE 0x100
52#define RT3883_PIO_SIZE 0x100
53#define RT3883_FSCC_SIZE 0x100
54#define RT3883_NANDC_SIZE 0x0f0
55#define RT3883_I2C_SIZE 0x100
56#define RT3883_I2S_SIZE 0x100
57#define RT3883_SPI_SIZE 0x100
58#define RT3883_PCM_SIZE 0x800
59#define RT3883_GDMA_SIZE 0x800
60#define RT3883_CODEC1_SIZE 0x800
61#define RT3883_CODEC2_SIZE 0x800
62#define RT3883_FE_SIZE 0x10000
63#define RT3883_ROM_SIZE 0x4000
64#define RT3883_USBDEV_SIZE 0x4000
65#define RT3883_PCI_SIZE 0x40000
66#define RT3883_WLAN_SIZE 0x40000
67#define RT3883_USBHOST_SIZE 0x40000
68#define RT3883_BOOT_SIZE (32 * 1024 * 1024)
69#define RT3883_SRAM_SIZE (32 * 1024 * 1024)
70
71/* SYSC registers */
72#define RT3883_SYSC_REG_CHIPID0_3 0x00 /* Chip ID 0 */
73#define RT3883_SYSC_REG_CHIPID4_7 0x04 /* Chip ID 1 */
74#define RT3883_SYSC_REG_REVID 0x0c /* Chip Revision Identification */
75#define RT3883_SYSC_REG_SYSCFG0 0x10 /* System Configuration 0 */
76#define RT3883_SYSC_REG_SYSCFG1 0x14 /* System Configuration 1 */
77#define RT3883_SYSC_REG_CLKCFG0 0x2c /* Clock Configuration 0 */
78#define RT3883_SYSC_REG_CLKCFG1 0x30 /* Clock Configuration 1 */
79#define RT3883_SYSC_REG_RSTCTRL 0x34 /* Reset Control*/
80#define RT3883_SYSC_REG_RSTSTAT 0x38 /* Reset Status*/
81#define RT3883_SYSC_REG_USB_PS 0x5c /* USB Power saving control */
82#define RT3883_SYSC_REG_GPIO_MODE 0x60 /* GPIO Purpose Select */
83#define RT3883_SYSC_REG_PCIE_CLK_GEN0 0x7c
84#define RT3883_SYSC_REG_PCIE_CLK_GEN1 0x80
85#define RT3883_SYSC_REG_PCIE_CLK_GEN2 0x84
86#define RT3883_SYSC_REG_PMU 0x88
87#define RT3883_SYSC_REG_PMU1 0x8c
88
89#define RT3883_CHIP_NAME0 0x38335452
90#define RT3883_CHIP_NAME1 0x20203338
91
92#define RT3883_REVID_VER_ID_MASK 0x0f
93#define RT3883_REVID_VER_ID_SHIFT 8
94#define RT3883_REVID_ECO_ID_MASK 0x0f
95
96#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
97#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
98#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
99#define RT3883_SYSCFG0_CPUCLK_250 0x0
100#define RT3883_SYSCFG0_CPUCLK_384 0x1
101#define RT3883_SYSCFG0_CPUCLK_480 0x2
102#define RT3883_SYSCFG0_CPUCLK_500 0x3
103
104#define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
105#define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
106#define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
107#define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
108#define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
109
110#define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
111#define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
112#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
113#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
114
115#define RT3883_GPIO_MODE_I2C BIT(0)
116#define RT3883_GPIO_MODE_SPI BIT(1)
117#define RT3883_GPIO_MODE_UART0_SHIFT 2
118#define RT3883_GPIO_MODE_UART0_MASK 0x7
119#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
120#define RT3883_GPIO_MODE_UARTF 0x0
121#define RT3883_GPIO_MODE_PCM_UARTF 0x1
122#define RT3883_GPIO_MODE_PCM_I2S 0x2
123#define RT3883_GPIO_MODE_I2S_UARTF 0x3
124#define RT3883_GPIO_MODE_PCM_GPIO 0x4
125#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
126#define RT3883_GPIO_MODE_GPIO_I2S 0x6
127#define RT3883_GPIO_MODE_GPIO 0x7
128#define RT3883_GPIO_MODE_UART1 BIT(5)
129#define RT3883_GPIO_MODE_JTAG BIT(6)
130#define RT3883_GPIO_MODE_MDIO BIT(7)
131#define RT3883_GPIO_MODE_GE1 BIT(9)
132#define RT3883_GPIO_MODE_GE2 BIT(10)
133#define RT3883_GPIO_MODE_PCI_SHIFT 11
134#define RT3883_GPIO_MODE_PCI_MASK 0x7
135#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
136#define RT3883_GPIO_MODE_LNA_A_SHIFT 16
137#define RT3883_GPIO_MODE_LNA_A_MASK 0x3
138#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
139#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3
140#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
141#define RT3883_GPIO_MODE_LNA_G_SHIFT 18
142#define RT3883_GPIO_MODE_LNA_G_MASK 0x3
143#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
144#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3
145#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
146
147#define RT3883_GPIO_I2C_SD 1
148#define RT3883_GPIO_I2C_SCLK 2
149#define RT3883_GPIO_SPI_CS0 3
150#define RT3883_GPIO_SPI_CLK 4
151#define RT3883_GPIO_SPI_MOSI 5
152#define RT3883_GPIO_SPI_MISO 6
153#define RT3883_GPIO_7 7
154#define RT3883_GPIO_10 10
155#define RT3883_GPIO_11 11
156#define RT3883_GPIO_14 14
157#define RT3883_GPIO_UART1_TXD 15
158#define RT3883_GPIO_UART1_RXD 16
159#define RT3883_GPIO_JTAG_TDO 17
160#define RT3883_GPIO_JTAG_TDI 18
161#define RT3883_GPIO_JTAG_TMS 19
162#define RT3883_GPIO_JTAG_TCLK 20
163#define RT3883_GPIO_JTAG_TRST_N 21
164#define RT3883_GPIO_MDIO_MDC 22
165#define RT3883_GPIO_MDIO_MDIO 23
166#define RT3883_GPIO_LNA_PE_A0 32
167#define RT3883_GPIO_LNA_PE_A1 33
168#define RT3883_GPIO_LNA_PE_A2 34
169#define RT3883_GPIO_LNA_PE_G0 35
170#define RT3883_GPIO_LNA_PE_G1 36
171#define RT3883_GPIO_LNA_PE_G2 37
172#define RT3883_GPIO_PCI_AD0 40
173#define RT3883_GPIO_PCI_AD31 71
174#define RT3883_GPIO_GE2_TXD0 72
175#define RT3883_GPIO_GE2_TXD1 73
176#define RT3883_GPIO_GE2_TXD2 74
177#define RT3883_GPIO_GE2_TXD3 75
178#define RT3883_GPIO_GE2_TXEN 76
179#define RT3883_GPIO_GE2_TXCLK 77
180#define RT3883_GPIO_GE2_RXD0 78
181#define RT3883_GPIO_GE2_RXD1 79
182#define RT3883_GPIO_GE2_RXD2 80
183#define RT3883_GPIO_GE2_RXD3 81
184#define RT3883_GPIO_GE2_RXDV 82
185#define RT3883_GPIO_GE2_RXCLK 83
186#define RT3883_GPIO_GE1_TXD0 84
187#define RT3883_GPIO_GE1_TXD1 85
188#define RT3883_GPIO_GE1_TXD2 86
189#define RT3883_GPIO_GE1_TXD3 87
190#define RT3883_GPIO_GE1_TXEN 88
191#define RT3883_GPIO_GE1_TXCLK 89
192#define RT3883_GPIO_GE1_RXD0 90
193#define RT3883_GPIO_GE1_RXD1 91
194#define RT3883_GPIO_GE1_RXD2 92
195#define RT3883_GPIO_GE1_RXD3 93
196#define RT3883_GPIO_GE1_RXDV 94
197#define RT3883_GPIO_GE1_RXCLK 95
198
199#define RT3883_RSTCTRL_PCIE_PCI_PDM BIT(27)
200#define RT3883_RSTCTRL_FLASH BIT(26)
201#define RT3883_RSTCTRL_UDEV BIT(25)
202#define RT3883_RSTCTRL_PCI BIT(24)
203#define RT3883_RSTCTRL_PCIE BIT(23)
204#define RT3883_RSTCTRL_UHST BIT(22)
205#define RT3883_RSTCTRL_FE BIT(21)
206#define RT3883_RSTCTRL_WLAN BIT(20)
207#define RT3883_RSTCTRL_UART1 BIT(29)
208#define RT3883_RSTCTRL_SPI BIT(18)
209#define RT3883_RSTCTRL_I2S BIT(17)
210#define RT3883_RSTCTRL_I2C BIT(16)
211#define RT3883_RSTCTRL_NAND BIT(15)
212#define RT3883_RSTCTRL_DMA BIT(14)
213#define RT3883_RSTCTRL_PIO BIT(13)
214#define RT3883_RSTCTRL_UART BIT(12)
215#define RT3883_RSTCTRL_PCM BIT(11)
216#define RT3883_RSTCTRL_MC BIT(10)
217#define RT3883_RSTCTRL_INTC BIT(9)
218#define RT3883_RSTCTRL_TIMER BIT(8)
219#define RT3883_RSTCTRL_SYS BIT(0)
220
221#define RT3883_INTC_INT_SYSCTL BIT(0)
222#define RT3883_INTC_INT_TIMER0 BIT(1)
223#define RT3883_INTC_INT_TIMER1 BIT(2)
224#define RT3883_INTC_INT_IA BIT(3)
225#define RT3883_INTC_INT_PCM BIT(4)
226#define RT3883_INTC_INT_UART0 BIT(5)
227#define RT3883_INTC_INT_PIO BIT(6)
228#define RT3883_INTC_INT_DMA BIT(7)
229#define RT3883_INTC_INT_NAND BIT(8)
230#define RT3883_INTC_INT_PERFC BIT(9)
231#define RT3883_INTC_INT_I2S BIT(10)
232#define RT3883_INTC_INT_UART1 BIT(12)
233#define RT3883_INTC_INT_UHST BIT(18)
234#define RT3883_INTC_INT_UDEV BIT(19)
235
236/* FLASH/SRAM/Codec Controller registers */
237#define RT3883_FSCC_REG_FLASH_CFG0 0x00
238#define RT3883_FSCC_REG_FLASH_CFG1 0x04
239#define RT3883_FSCC_REG_CODEC_CFG0 0x40
240#define RT3883_FSCC_REG_CODEC_CFG1 0x44
241
242#define RT3883_FLASH_CFG_WIDTH_SHIFT 26
243#define RT3883_FLASH_CFG_WIDTH_MASK 0x3
244#define RT3883_FLASH_CFG_WIDTH_8BIT 0x0
245#define RT3883_FLASH_CFG_WIDTH_16BIT 0x1
246#define RT3883_FLASH_CFG_WIDTH_32BIT 0x2
247
248#define RT3883_SDRAM_BASE 0x00000000
249#define RT3883_MEM_SIZE_MIN 2
250#define RT3883_MEM_SIZE_MAX 256
251
252#endif /* _RT3883_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
new file mode 100644
index 000000000000..181fbf4c976f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
@@ -0,0 +1,55 @@
1/*
2 * Ralink RT3662/RT3883 specific CPU feature overrides
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was derived from: include/asm-mips/cpu-features.h
7 * Copyright (C) 2003, 2004 Ralf Baechle
8 * Copyright (C) 2004 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
16#define _RT3883_CPU_FEATURE_OVERRIDES_H
17
18#define cpu_has_tlb 1
19#define cpu_has_4kex 1
20#define cpu_has_3k_cache 0
21#define cpu_has_4k_cache 1
22#define cpu_has_tx39_cache 0
23#define cpu_has_sb1_cache 0
24#define cpu_has_fpu 0
25#define cpu_has_32fpr 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29
30#define cpu_has_prefetch 1
31#define cpu_has_ejtag 1
32#define cpu_has_llsc 1
33
34#define cpu_has_mips16 1
35#define cpu_has_mdmx 0
36#define cpu_has_mips3d 0
37#define cpu_has_smartmips 0
38
39#define cpu_has_mips32r1 1
40#define cpu_has_mips32r2 1
41#define cpu_has_mips64r1 0
42#define cpu_has_mips64r2 0
43
44#define cpu_has_dsp 1
45#define cpu_has_mipsmt 0
46
47#define cpu_has_64bits 0
48#define cpu_has_64bit_zero_reg 0
49#define cpu_has_64bit_gp_regs 0
50#define cpu_has_64bit_addresses 0
51
52#define cpu_dcache_line_size() 32
53#define cpu_icache_line_size() 32
54
55#endif /* _RT3883_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index 193c0912d38e..bfbd7035d4c5 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,7 +28,11 @@
28/* #define cpu_has_prefetch ? */ 28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1 29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */ 30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_MICROMIPS
32#define cpu_has_llsc 0
33#else
31#define cpu_has_llsc 1 34#define cpu_has_llsc 1
35#endif
32/* #define cpu_has_vtag_icache ? */ 36/* #define cpu_has_vtag_icache ? */
33/* #define cpu_has_dc_aliases ? */ 37/* #define cpu_has_dc_aliases ? */
34/* #define cpu_has_ic_fills_f_dc ? */ 38/* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 44a09a64160a..bd9746fbe4af 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -83,4 +83,7 @@ extern void mips_pcibios_init(void);
83#define mips_pcibios_init() do { } while (0) 83#define mips_pcibios_init() do { } while (0)
84#endif 84#endif
85 85
86extern void mips_scroll_message(void);
87extern void mips_display_message(const char *str);
88
86#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 89#endif /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h
deleted file mode 100644
index e7aed3e4ff58..000000000000
--- a/arch/mips/include/asm/mips-boards/prom.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * MIPS boards bootprom interface for the Linux kernel.
23 *
24 */
25
26#ifndef _MIPS_PROM_H
27#define _MIPS_PROM_H
28
29extern char *prom_getcmdline(void);
30extern char *prom_getenv(char *name);
31extern void prom_init_cmdline(void);
32extern void prom_meminit(void);
33extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
34extern void mips_display_message(const char *str);
35extern void mips_display_word(unsigned int num);
36extern void mips_scroll_message(void);
37extern int get_ethernet_addr(char *ethernet_addr);
38
39/* Memory descriptor management. */
40#define PROM_MAX_PMEMBLOCKS 32
41struct prom_pmemblock {
42 unsigned long base; /* Within KSEG0. */
43 unsigned int size; /* In bytes. */
44 unsigned int type; /* free or prom memory */
45};
46
47#endif /* !(_MIPS_PROM_H) */
diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h
index 363bb352c7f7..9d00aebe9842 100644
--- a/arch/mips/include/asm/mips_machine.h
+++ b/arch/mips/include/asm/mips_machine.h
@@ -42,13 +42,9 @@ extern long __mips_machines_end;
42#ifdef CONFIG_MIPS_MACHINE 42#ifdef CONFIG_MIPS_MACHINE
43int mips_machtype_setup(char *id) __init; 43int mips_machtype_setup(char *id) __init;
44void mips_machine_setup(void) __init; 44void mips_machine_setup(void) __init;
45void mips_set_machine_name(const char *name) __init;
46char *mips_get_machine_name(void);
47#else 45#else
48static inline int mips_machtype_setup(char *id) { return 1; } 46static inline int mips_machtype_setup(char *id) { return 1; }
49static inline void mips_machine_setup(void) { } 47static inline void mips_machine_setup(void) { }
50static inline void mips_set_machine_name(const char *name) { }
51static inline char *mips_get_machine_name(void) { return NULL; }
52#endif /* CONFIG_MIPS_MACHINE */ 48#endif /* CONFIG_MIPS_MACHINE */
53 49
54#endif /* __ASM_MIPS_MACHINE_H */ 50#endif /* __ASM_MIPS_MACHINE_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0da44d422f5b..87e6207b05e4 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -596,6 +596,7 @@
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16)
599#define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 600#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
600 601
601#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 602#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
@@ -623,6 +624,24 @@
623#ifndef __ASSEMBLY__ 624#ifndef __ASSEMBLY__
624 625
625/* 626/*
627 * Macros for handling the ISA mode bit for microMIPS.
628 */
629#define get_isa16_mode(x) ((x) & 0x1)
630#define msk_isa16_mode(x) ((x) & ~0x1)
631#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
632
633/*
634 * microMIPS instructions can be 16-bit or 32-bit in length. This
635 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
636 */
637static inline int mm_insn_16bit(u16 insn)
638{
639 u16 opcode = (insn >> 10) & 0x7;
640
641 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
642}
643
644/*
626 * Functions to access the R10000 performance counters. These are basically 645 * Functions to access the R10000 performance counters. These are basically
627 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 646 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
628 * performance counter number encoded into bits 1 ... 5 of the instruction. 647 * performance counter number encoded into bits 1 ... 5 of the instruction.
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index e81d719efcd1..1554721e4808 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -26,10 +26,15 @@
26 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28 28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)) 30do { \
31 31 void (*tlbmiss_handler_setup_pgd)(unsigned long); \
32extern void tlbmiss_handler_setup_pgd(unsigned long pgd); 32 extern u32 tlbmiss_handler_setup_pgd_array[16]; \
33 \
34 tlbmiss_handler_setup_pgd = \
35 (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \
36 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
37} while (0)
33 38
34#define TLBMISS_HANDLER_SETUP() \ 39#define TLBMISS_HANDLER_SETUP() \
35 do { \ 40 do { \
@@ -62,59 +67,88 @@ extern unsigned long pgd_current[];
62 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 67 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
63#endif 68#endif
64#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 69#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
65#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
66
67#define ASID_INC 0x40
68#define ASID_MASK 0xfc0
69
70#elif defined(CONFIG_CPU_R8000)
71
72#define ASID_INC 0x10
73#define ASID_MASK 0xff0
74 70
75#elif defined(CONFIG_MIPS_MT_SMTC) 71#define ASID_INC(asid) \
76 72({ \
77#define ASID_INC 0x1 73 unsigned long __asid = asid; \
78extern unsigned long smtc_asid_mask; 74 __asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \
79#define ASID_MASK (smtc_asid_mask) 75 ".section\t__asid_inc,\"a\"\n\t" \
80#define HW_ASID_MASK 0xff 76 ".word\t1b\n\t" \
81/* End SMTC/34K debug hack */ 77 ".previous" \
82#else /* FIXME: not correct for R6000 */ 78 :"=r" (__asid) \
83 79 :"0" (__asid)); \
84#define ASID_INC 0x1 80 __asid; \
85#define ASID_MASK 0xff 81})
82#define ASID_MASK(asid) \
83({ \
84 unsigned long __asid = asid; \
85 __asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \
86 ".section\t__asid_mask,\"a\"\n\t" \
87 ".word\t1b\n\t" \
88 ".previous" \
89 :"=r" (__asid) \
90 :"r" (__asid)); \
91 __asid; \
92})
93#define ASID_VERSION_MASK \
94({ \
95 unsigned long __asid; \
96 __asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \
97 ".section\t__asid_version_mask,\"a\"\n\t" \
98 ".word\t1b\n\t" \
99 ".previous" \
100 :"=r" (__asid)); \
101 __asid; \
102})
103#define ASID_FIRST_VERSION \
104({ \
105 unsigned long __asid = asid; \
106 __asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \
107 ".section\t__asid_first_version,\"a\"\n\t" \
108 ".word\t1b\n\t" \
109 ".previous" \
110 :"=r" (__asid)); \
111 __asid; \
112})
113
114#define ASID_FIRST_VERSION_R3000 0x1000
115#define ASID_FIRST_VERSION_R4000 0x100
116#define ASID_FIRST_VERSION_R8000 0x1000
117#define ASID_FIRST_VERSION_RM9000 0x1000
86 118
119#ifdef CONFIG_MIPS_MT_SMTC
120#define SMTC_HW_ASID_MASK 0xff
121extern unsigned int smtc_asid_mask;
87#endif 122#endif
88 123
89#define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 124#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
90#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 125#define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm)))
91#define asid_cache(cpu) (cpu_data[cpu].asid_cache) 126#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
92 127
93static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 128static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
94{ 129{
95} 130}
96 131
97/*
98 * All unused by hardware upper bits will be considered
99 * as a software asid extension.
100 */
101#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
102#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
103
104#ifndef CONFIG_MIPS_MT_SMTC 132#ifndef CONFIG_MIPS_MT_SMTC
105/* Normal, classic MIPS get_new_mmu_context */ 133/* Normal, classic MIPS get_new_mmu_context */
106static inline void 134static inline void
107get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 135get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
108{ 136{
137 extern void kvm_local_flush_tlb_all(void);
109 unsigned long asid = asid_cache(cpu); 138 unsigned long asid = asid_cache(cpu);
110 139
111 if (! ((asid += ASID_INC) & ASID_MASK) ) { 140 if (!ASID_MASK((asid = ASID_INC(asid)))) {
112 if (cpu_has_vtag_icache) 141 if (cpu_has_vtag_icache)
113 flush_icache_all(); 142 flush_icache_all();
143#ifdef CONFIG_VIRTUALIZATION
144 kvm_local_flush_tlb_all(); /* start new asid cycle */
145#else
114 local_flush_tlb_all(); /* start new asid cycle */ 146 local_flush_tlb_all(); /* start new asid cycle */
147#endif
115 if (!asid) /* fix version if needed */ 148 if (!asid) /* fix version if needed */
116 asid = ASID_FIRST_VERSION; 149 asid = ASID_FIRST_VERSION;
117 } 150 }
151
118 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 152 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
119} 153}
120 154
@@ -133,7 +167,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
133{ 167{
134 int i; 168 int i;
135 169
136 for_each_online_cpu(i) 170 for_each_possible_cpu(i)
137 cpu_context(i, mm) = 0; 171 cpu_context(i, mm) = 0;
138 172
139 return 0; 173 return 0;
@@ -166,7 +200,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
166 * free up the ASID value for use and flush any old 200 * free up the ASID value for use and flush any old
167 * instances of it from the TLB. 201 * instances of it from the TLB.
168 */ 202 */
169 oldasid = (read_c0_entryhi() & ASID_MASK); 203 oldasid = ASID_MASK(read_c0_entryhi());
170 if(smtc_live_asid[mytlb][oldasid]) { 204 if(smtc_live_asid[mytlb][oldasid]) {
171 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 205 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
172 if(smtc_live_asid[mytlb][oldasid] == 0) 206 if(smtc_live_asid[mytlb][oldasid] == 0)
@@ -177,7 +211,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
177 * having ASID_MASK smaller than the hardware maximum, 211 * having ASID_MASK smaller than the hardware maximum,
178 * make sure no "soft" bits become "hard"... 212 * make sure no "soft" bits become "hard"...
179 */ 213 */
180 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 214 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
181 cpu_asid(cpu, next)); 215 cpu_asid(cpu, next));
182 ehb(); /* Make sure it propagates to TCStatus */ 216 ehb(); /* Make sure it propagates to TCStatus */
183 evpe(mtflags); 217 evpe(mtflags);
@@ -230,15 +264,15 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
230#ifdef CONFIG_MIPS_MT_SMTC 264#ifdef CONFIG_MIPS_MT_SMTC
231 /* See comments for similar code above */ 265 /* See comments for similar code above */
232 mtflags = dvpe(); 266 mtflags = dvpe();
233 oldasid = read_c0_entryhi() & ASID_MASK; 267 oldasid = ASID_MASK(read_c0_entryhi());
234 if(smtc_live_asid[mytlb][oldasid]) { 268 if(smtc_live_asid[mytlb][oldasid]) {
235 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 269 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
236 if(smtc_live_asid[mytlb][oldasid] == 0) 270 if(smtc_live_asid[mytlb][oldasid] == 0)
237 smtc_flush_tlb_asid(oldasid); 271 smtc_flush_tlb_asid(oldasid);
238 } 272 }
239 /* See comments for similar code above */ 273 /* See comments for similar code above */
240 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 274 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
241 cpu_asid(cpu, next)); 275 cpu_asid(cpu, next));
242 ehb(); /* Make sure it propagates to TCStatus */ 276 ehb(); /* Make sure it propagates to TCStatus */
243 evpe(mtflags); 277 evpe(mtflags);
244#else 278#else
@@ -275,14 +309,14 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
275#ifdef CONFIG_MIPS_MT_SMTC 309#ifdef CONFIG_MIPS_MT_SMTC
276 /* See comments for similar code above */ 310 /* See comments for similar code above */
277 prevvpe = dvpe(); 311 prevvpe = dvpe();
278 oldasid = (read_c0_entryhi() & ASID_MASK); 312 oldasid = ASID_MASK(read_c0_entryhi());
279 if (smtc_live_asid[mytlb][oldasid]) { 313 if (smtc_live_asid[mytlb][oldasid]) {
280 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 314 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
281 if(smtc_live_asid[mytlb][oldasid] == 0) 315 if(smtc_live_asid[mytlb][oldasid] == 0)
282 smtc_flush_tlb_asid(oldasid); 316 smtc_flush_tlb_asid(oldasid);
283 } 317 }
284 /* See comments for similar code above */ 318 /* See comments for similar code above */
285 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 319 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK)
286 | cpu_asid(cpu, mm)); 320 | cpu_asid(cpu, mm));
287 ehb(); /* Make sure it propagates to TCStatus */ 321 ehb(); /* Make sure it propagates to TCStatus */
288 evpe(prevvpe); 322 evpe(prevvpe);
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
index 419d8aef8569..79c7cccdc22c 100644
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -35,42 +35,13 @@
35#ifndef __NLM_HAL_HALDEFS_H__ 35#ifndef __NLM_HAL_HALDEFS_H__
36#define __NLM_HAL_HALDEFS_H__ 36#define __NLM_HAL_HALDEFS_H__
37 37
38#include <linux/irqflags.h> /* for local_irq_disable */
39
38/* 40/*
39 * This file contains platform specific memory mapped IO implementation 41 * This file contains platform specific memory mapped IO implementation
40 * and will provide a way to read 32/64 bit memory mapped registers in 42 * and will provide a way to read 32/64 bit memory mapped registers in
41 * all ABIs 43 * all ABIs
42 */ 44 */
43#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
44#error "o32 compile not supported on XLP yet"
45#endif
46/*
47 * For o32 compilation, we have to disable interrupts and enable KX bit to
48 * access 64 bit addresses or data.
49 *
50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose.
53 */
54static inline uint32_t nlm_save_flags_kx(void)
55{
56 return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
57}
58
59static inline uint32_t nlm_save_flags_cop2(void)
60{
61 return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
62}
63
64static inline void nlm_restore_flags(uint32_t sr)
65{
66 write_c0_status(sr);
67}
68
69/*
70 * The n64 implementations are simple, the o32 implementations when they
71 * are added, will have to disable interrupts and enable KX before doing
72 * 64 bit ops.
73 */
74static inline uint32_t 45static inline uint32_t
75nlm_read_reg(uint64_t base, uint32_t reg) 46nlm_read_reg(uint64_t base, uint32_t reg)
76{ 47{
@@ -87,13 +58,40 @@ nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
87 *addr = val; 58 *addr = val;
88} 59}
89 60
61/*
62 * For o32 compilation, we have to disable interrupts to access 64 bit
63 * registers
64 *
65 * We need to disable interrupts because we save just the lower 32 bits of
66 * registers in interrupt handling. So if we get hit by an interrupt while
67 * using the upper 32 bits of a register, we lose.
68 */
69
90static inline uint64_t 70static inline uint64_t
91nlm_read_reg64(uint64_t base, uint32_t reg) 71nlm_read_reg64(uint64_t base, uint32_t reg)
92{ 72{
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); 73 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
94 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; 74 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
95 75 uint64_t val;
96 return *ptr; 76
77 if (sizeof(unsigned long) == 4) {
78 unsigned long flags;
79
80 local_irq_save(flags);
81 __asm__ __volatile__(
82 ".set push" "\n\t"
83 ".set mips64" "\n\t"
84 "ld %L0, %1" "\n\t"
85 "dsra32 %M0, %L0, 0" "\n\t"
86 "sll %L0, %L0, 0" "\n\t"
87 ".set pop" "\n"
88 : "=r" (val)
89 : "m" (*ptr));
90 local_irq_restore(flags);
91 } else
92 val = *ptr;
93
94 return val;
97} 95}
98 96
99static inline void 97static inline void
@@ -102,7 +100,25 @@ nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); 100 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
103 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; 101 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
104 102
105 *ptr = val; 103 if (sizeof(unsigned long) == 4) {
104 unsigned long flags;
105 uint64_t tmp;
106
107 local_irq_save(flags);
108 __asm__ __volatile__(
109 ".set push" "\n\t"
110 ".set mips64" "\n\t"
111 "dsll32 %L0, %L0, 0" "\n\t"
112 "dsrl32 %L0, %L0, 0" "\n\t"
113 "dsll32 %M0, %M0, 0" "\n\t"
114 "or %L0, %L0, %M0" "\n\t"
115 "sd %L0, %2" "\n\t"
116 ".set pop" "\n"
117 : "=r" (tmp)
118 : "0" (val), "m" (*ptr));
119 local_irq_restore(flags);
120 } else
121 *ptr = val;
106} 122}
107 123
108/* 124/*
@@ -143,14 +159,6 @@ nlm_pcicfg_base(uint32_t devoffset)
143 return nlm_io_base + devoffset; 159 return nlm_io_base + devoffset;
144} 160}
145 161
146static inline uint64_t
147nlm_xkphys_map_pcibar0(uint64_t pcibase)
148{
149 uint64_t paddr;
150
151 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
152 return (uint64_t)0x9000000000000000 | paddr;
153}
154#elif defined(CONFIG_CPU_XLR) 162#elif defined(CONFIG_CPU_XLR)
155 163
156static inline uint64_t 164static inline uint64_t
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 8ad2e0f81719..f299d31d7c1a 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -38,21 +38,16 @@
38/* 38/*
39 * XLR and XLP interrupt request and interrupt mask registers 39 * XLR and XLP interrupt request and interrupt mask registers
40 */ 40 */
41#define read_c0_eirr() __read_64bit_c0_register($9, 6)
42#define read_c0_eimr() __read_64bit_c0_register($9, 7)
43#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
44
45/* 41/*
46 * Writing EIMR in 32 bit is a special case, the lower 8 bit of the 42 * NOTE: Do not save/restore flags around write_c0_eimr().
47 * EIMR is shadowed in the status register, so we cannot save and 43 * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
48 * restore status register for split read. 44 * register. Restoring flags will overwrite the lower 8 bits of EIMR.
45 *
46 * Call with interrupts disabled.
49 */ 47 */
50#define write_c0_eimr(val) \ 48#define write_c0_eimr(val) \
51do { \ 49do { \
52 if (sizeof(unsigned long) == 4) { \ 50 if (sizeof(unsigned long) == 4) { \
53 unsigned long __flags; \
54 \
55 local_irq_save(__flags); \
56 __asm__ __volatile__( \ 51 __asm__ __volatile__( \
57 ".set\tmips64\n\t" \ 52 ".set\tmips64\n\t" \
58 "dsll\t%L0, %L0, 32\n\t" \ 53 "dsll\t%L0, %L0, 32\n\t" \
@@ -62,8 +57,6 @@ do { \
62 "dmtc0\t%L0, $9, 7\n\t" \ 57 "dmtc0\t%L0, $9, 7\n\t" \
63 ".set\tmips0" \ 58 ".set\tmips0" \
64 : : "r" (val)); \ 59 : : "r" (val)); \
65 __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
66 local_irq_restore(__flags); \
67 } else \ 60 } else \
68 __write_64bit_c0_register($9, 7, (val)); \ 61 __write_64bit_c0_register($9, 7, (val)); \
69} while (0) 62} while (0)
@@ -128,7 +121,7 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
128 uint64_t val; 121 uint64_t val;
129 122
130#ifdef CONFIG_64BIT 123#ifdef CONFIG_64BIT
131 val = read_c0_eimr() & read_c0_eirr(); 124 val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
132#else 125#else
133 __asm__ __volatile__( 126 __asm__ __volatile__(
134 ".set push\n\t" 127 ".set push\n\t"
@@ -143,7 +136,6 @@ static inline uint64_t read_c0_eirr_and_eimr(void)
143 ".set pop" 136 ".set pop"
144 : "=r" (val)); 137 : "=r" (val));
145#endif 138#endif
146
147 return val; 139 return val;
148} 140}
149 141
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 3df53017fe51..a981f4681a15 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -191,59 +191,6 @@
191#define PIC_IRT_PCIE_LINK_2_INDEX 80 191#define PIC_IRT_PCIE_LINK_2_INDEX 80
192#define PIC_IRT_PCIE_LINK_3_INDEX 81 192#define PIC_IRT_PCIE_LINK_3_INDEX 81
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194/* 78 to 81 */
195#define PIC_NUM_NA_IRTS 32
196/* 82 to 113 */
197#define PIC_IRT_NA_0_INDEX 82
198#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199#define PIC_IRT_POE_INDEX 114
200
201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_OHCI_0_INDEX 116
205#define PIC_IRT_OHCI_1_INDEX 117
206#define PIC_IRT_EHCI_1_INDEX 118
207#define PIC_IRT_OHCI_2_INDEX 119
208#define PIC_IRT_OHCI_3_INDEX 120
209#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
210/* 115 to 120 */
211#define PIC_IRT_GDX_INDEX 121
212#define PIC_IRT_SEC_INDEX 122
213#define PIC_IRT_RSA_INDEX 123
214
215#define PIC_NUM_COMP_IRTS 4
216#define PIC_IRT_COMP_0_INDEX 124
217#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
218/* 124 to 127 */
219#define PIC_IRT_GBU_INDEX 128
220#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
221#define PIC_IRT_ICC_1_INDEX 130
222#define PIC_IRT_ICC_2_INDEX 131
223#define PIC_IRT_CAM_INDEX 132
224#define PIC_IRT_UART_0_INDEX 133
225#define PIC_IRT_UART_1_INDEX 134
226#define PIC_IRT_I2C_0_INDEX 135
227#define PIC_IRT_I2C_1_INDEX 136
228#define PIC_IRT_SYS_0_INDEX 137
229#define PIC_IRT_SYS_1_INDEX 138
230#define PIC_IRT_JTAG_INDEX 139
231#define PIC_IRT_PIC_INDEX 140
232#define PIC_IRT_NBU_INDEX 141
233#define PIC_IRT_TCU_INDEX 142
234#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
235#define PIC_IRT_DMC_0_INDEX 144
236#define PIC_IRT_DMC_1_INDEX 145
237
238#define PIC_NUM_GPIO_IRTS 4
239#define PIC_IRT_GPIO_0_INDEX 146
240#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
241
242/* 146 to 149 */
243#define PIC_IRT_NOR_INDEX 150
244#define PIC_IRT_NAND_INDEX 151
245#define PIC_IRT_SPI_INDEX 152
246#define PIC_IRT_MMC_INDEX 153
247 194
248#define PIC_CLOCK_TIMER 7 195#define PIC_CLOCK_TIMER 7
249#define PIC_IRQ_BASE 8 196#define PIC_IRQ_BASE 8
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
deleted file mode 100644
index a9cd350dfb6c..000000000000
--- a/arch/mips/include/asm/netlogic/xlp-hal/usb.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_USB_H__
36#define __NLM_HAL_USB_H__
37
38#define USB_CTL_0 0x01
39#define USB_PHY_0 0x0A
40#define USB_PHY_RESET 0x01
41#define USB_PHY_PORT_RESET_0 0x10
42#define USB_PHY_PORT_RESET_1 0x20
43#define USB_CONTROLLER_RESET 0x01
44#define USB_INT_STATUS 0x0E
45#define USB_INT_EN 0x0F
46#define USB_PHY_INTERRUPT_EN 0x01
47#define USB_OHCI_INTERRUPT_EN 0x02
48#define USB_OHCI_INTERRUPT1_EN 0x04
49#define USB_OHCI_INTERRUPT2_EN 0x08
50#define USB_CTRL_INTERRUPT_EN 0x10
51
52#ifndef __ASSEMBLY__
53
54#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
55#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
56#define nlm_get_usb_pcibase(node, inst) \
57 nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
58#define nlm_get_usb_hcd_base(node, inst) \
59 nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
60#define nlm_get_usb_regbase(node, inst) \
61 (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
62
63#endif
64#endif /* __NLM_HAL_USB_H__ */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index fdc62fb5630d..8b8f6b393363 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -8,6 +8,7 @@
8#ifndef _ASM_PGTABLE_H 8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H 9#define _ASM_PGTABLE_H
10 10
11#include <linux/mm_types.h>
11#include <linux/mmzone.h> 12#include <linux/mmzone.h>
12#ifdef CONFIG_32BIT 13#ifdef CONFIG_32BIT
13#include <asm/pgtable-32.h> 14#include <asm/pgtable-32.h>
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 2a5fa7abb346..71686c897dea 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -44,11 +44,16 @@ extern unsigned int vced_count, vcei_count;
44#define SPECIAL_PAGES_SIZE PAGE_SIZE 44#define SPECIAL_PAGES_SIZE PAGE_SIZE
45 45
46#ifdef CONFIG_32BIT 46#ifdef CONFIG_32BIT
47#ifdef CONFIG_KVM_GUEST
48/* User space process size is limited to 1GB in KVM Guest Mode */
49#define TASK_SIZE 0x3fff8000UL
50#else
47/* 51/*
48 * User space process size: 2GB. This is hardcoded into a few places, 52 * User space process size: 2GB. This is hardcoded into a few places,
49 * so don't change it unless you know what you are doing. 53 * so don't change it unless you know what you are doing.
50 */ 54 */
51#define TASK_SIZE 0x7fff8000UL 55#define TASK_SIZE 0x7fff8000UL
56#endif
52 57
53#ifdef __KERNEL__ 58#ifdef __KERNEL__
54#define STACK_TOP_MAX TASK_SIZE 59#define STACK_TOP_MAX TASK_SIZE
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 8808bf548b99..1e7e0961064b 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -48,4 +48,7 @@ extern void __dt_setup_arch(struct boot_param_header *bph);
48static inline void device_tree_init(void) { } 48static inline void device_tree_init(void) { }
49#endif /* CONFIG_OF */ 49#endif /* CONFIG_OF */
50 50
51extern char *mips_get_machine_name(void);
52extern void mips_set_machine_name(const char *name);
53
51#endif /* __ASM_PROM_H */ 54#endif /* __ASM_PROM_H */
diff --git a/arch/mips/include/asm/sn/sn_private.h b/arch/mips/include/asm/sn/sn_private.h
index 1a2c3025bf28..fdfae43d8b99 100644
--- a/arch/mips/include/asm/sn/sn_private.h
+++ b/arch/mips/include/asm/sn/sn_private.h
@@ -14,6 +14,6 @@ extern void install_cpu_nmi_handler(int slice);
14extern void install_ipi(void); 14extern void install_ipi(void);
15extern void setup_replication_mask(void); 15extern void setup_replication_mask(void);
16extern void replicate_kernel_text(void); 16extern void replicate_kernel_text(void);
17extern pfn_t node_getfirstfree(cnodeid_t); 17extern unsigned long node_getfirstfree(cnodeid_t);
18 18
19#endif /* __ASM_SN_SN_PRIVATE_H */ 19#endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
index c4813d67aec3..6d24d4e8b9ed 100644
--- a/arch/mips/include/asm/sn/types.h
+++ b/arch/mips/include/asm/sn/types.h
@@ -19,7 +19,6 @@ typedef signed char partid_t; /* partition ID type */
19typedef signed short moduleid_t; /* user-visible module number type */ 19typedef signed short moduleid_t; /* user-visible module number type */
20typedef signed short cmoduleid_t; /* kernel compact module id type */ 20typedef signed short cmoduleid_t; /* kernel compact module id type */
21typedef unsigned char clusterid_t; /* Clusterid of the cell */ 21typedef unsigned char clusterid_t; /* Clusterid of the cell */
22typedef unsigned long pfn_t;
23 22
24typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */ 23typedef dev_t vertex_hdl_t; /* hardware graph vertex handle */
25 24
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 5130c88d6420..78d201fb6c87 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -71,7 +71,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
71 " nop \n" 71 " nop \n"
72 " srl %[my_ticket], %[ticket], 16 \n" 72 " srl %[my_ticket], %[ticket], 16 \n"
73 " andi %[ticket], %[ticket], 0xffff \n" 73 " andi %[ticket], %[ticket], 0xffff \n"
74 " andi %[my_ticket], %[my_ticket], 0xffff \n"
75 " bne %[ticket], %[my_ticket], 4f \n" 74 " bne %[ticket], %[my_ticket], 4f \n"
76 " subu %[ticket], %[my_ticket], %[ticket] \n" 75 " subu %[ticket], %[my_ticket], %[ticket] \n"
77 "2: \n" 76 "2: \n"
@@ -105,7 +104,6 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
105 " beqz %[my_ticket], 1b \n" 104 " beqz %[my_ticket], 1b \n"
106 " srl %[my_ticket], %[ticket], 16 \n" 105 " srl %[my_ticket], %[ticket], 16 \n"
107 " andi %[ticket], %[ticket], 0xffff \n" 106 " andi %[ticket], %[ticket], 0xffff \n"
108 " andi %[my_ticket], %[my_ticket], 0xffff \n"
109 " bne %[ticket], %[my_ticket], 4f \n" 107 " bne %[ticket], %[my_ticket], 4f \n"
110 " subu %[ticket], %[my_ticket], %[ticket] \n" 108 " subu %[ticket], %[my_ticket], %[ticket] \n"
111 "2: \n" 109 "2: \n"
@@ -153,7 +151,6 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
153 " \n" 151 " \n"
154 "1: ll %[ticket], %[ticket_ptr] \n" 152 "1: ll %[ticket], %[ticket_ptr] \n"
155 " srl %[my_ticket], %[ticket], 16 \n" 153 " srl %[my_ticket], %[ticket], 16 \n"
156 " andi %[my_ticket], %[my_ticket], 0xffff \n"
157 " andi %[now_serving], %[ticket], 0xffff \n" 154 " andi %[now_serving], %[ticket], 0xffff \n"
158 " bne %[my_ticket], %[now_serving], 3f \n" 155 " bne %[my_ticket], %[now_serving], 3f \n"
159 " addu %[ticket], %[ticket], %[inc] \n" 156 " addu %[ticket], %[ticket], %[inc] \n"
@@ -178,7 +175,6 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
178 " \n" 175 " \n"
179 "1: ll %[ticket], %[ticket_ptr] \n" 176 "1: ll %[ticket], %[ticket_ptr] \n"
180 " srl %[my_ticket], %[ticket], 16 \n" 177 " srl %[my_ticket], %[ticket], 16 \n"
181 " andi %[my_ticket], %[my_ticket], 0xffff \n"
182 " andi %[now_serving], %[ticket], 0xffff \n" 178 " andi %[now_serving], %[ticket], 0xffff \n"
183 " bne %[my_ticket], %[now_serving], 3f \n" 179 " bne %[my_ticket], %[now_serving], 3f \n"
184 " addu %[ticket], %[ticket], %[inc] \n" 180 " addu %[ticket], %[ticket], %[inc] \n"
@@ -242,25 +238,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
242 : "m" (rw->lock) 238 : "m" (rw->lock)
243 : "memory"); 239 : "memory");
244 } else { 240 } else {
245 __asm__ __volatile__( 241 do {
246 " .set noreorder # arch_read_lock \n" 242 __asm__ __volatile__(
247 "1: ll %1, %2 \n" 243 "1: ll %1, %2 # arch_read_lock \n"
248 " bltz %1, 3f \n" 244 " bltz %1, 1b \n"
249 " addu %1, 1 \n" 245 " addu %1, 1 \n"
250 "2: sc %1, %0 \n" 246 "2: sc %1, %0 \n"
251 " beqz %1, 1b \n" 247 : "=m" (rw->lock), "=&r" (tmp)
252 " nop \n" 248 : "m" (rw->lock)
253 " .subsection 2 \n" 249 : "memory");
254 "3: ll %1, %2 \n" 250 } while (unlikely(!tmp));
255 " bltz %1, 3b \n"
256 " addu %1, 1 \n"
257 " b 2b \n"
258 " nop \n"
259 " .previous \n"
260 " .set reorder \n"
261 : "=m" (rw->lock), "=&r" (tmp)
262 : "m" (rw->lock)
263 : "memory");
264 } 251 }
265 252
266 smp_llsc_mb(); 253 smp_llsc_mb();
@@ -285,21 +272,15 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
285 : "m" (rw->lock) 272 : "m" (rw->lock)
286 : "memory"); 273 : "memory");
287 } else { 274 } else {
288 __asm__ __volatile__( 275 do {
289 " .set noreorder # arch_read_unlock \n" 276 __asm__ __volatile__(
290 "1: ll %1, %2 \n" 277 "1: ll %1, %2 # arch_read_unlock \n"
291 " sub %1, 1 \n" 278 " sub %1, 1 \n"
292 " sc %1, %0 \n" 279 " sc %1, %0 \n"
293 " beqz %1, 2f \n" 280 : "=m" (rw->lock), "=&r" (tmp)
294 " nop \n" 281 : "m" (rw->lock)
295 " .subsection 2 \n" 282 : "memory");
296 "2: b 1b \n" 283 } while (unlikely(!tmp));
297 " nop \n"
298 " .previous \n"
299 " .set reorder \n"
300 : "=m" (rw->lock), "=&r" (tmp)
301 : "m" (rw->lock)
302 : "memory");
303 } 284 }
304} 285}
305 286
@@ -321,25 +302,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
321 : "m" (rw->lock) 302 : "m" (rw->lock)
322 : "memory"); 303 : "memory");
323 } else { 304 } else {
324 __asm__ __volatile__( 305 do {
325 " .set noreorder # arch_write_lock \n" 306 __asm__ __volatile__(
326 "1: ll %1, %2 \n" 307 "1: ll %1, %2 # arch_write_lock \n"
327 " bnez %1, 3f \n" 308 " bnez %1, 1b \n"
328 " lui %1, 0x8000 \n" 309 " lui %1, 0x8000 \n"
329 "2: sc %1, %0 \n" 310 "2: sc %1, %0 \n"
330 " beqz %1, 3f \n" 311 : "=m" (rw->lock), "=&r" (tmp)
331 " nop \n" 312 : "m" (rw->lock)
332 " .subsection 2 \n" 313 : "memory");
333 "3: ll %1, %2 \n" 314 } while (unlikely(!tmp));
334 " bnez %1, 3b \n"
335 " lui %1, 0x8000 \n"
336 " b 2b \n"
337 " nop \n"
338 " .previous \n"
339 " .set reorder \n"
340 : "=m" (rw->lock), "=&r" (tmp)
341 : "m" (rw->lock)
342 : "memory");
343 } 315 }
344 316
345 smp_llsc_mb(); 317 smp_llsc_mb();
@@ -424,25 +396,21 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
424 : "m" (rw->lock) 396 : "m" (rw->lock)
425 : "memory"); 397 : "memory");
426 } else { 398 } else {
427 __asm__ __volatile__( 399 do {
428 " .set noreorder # arch_write_trylock \n" 400 __asm__ __volatile__(
429 " li %2, 0 \n" 401 " ll %1, %3 # arch_write_trylock \n"
430 "1: ll %1, %3 \n" 402 " li %2, 0 \n"
431 " bnez %1, 2f \n" 403 " bnez %1, 2f \n"
432 " lui %1, 0x8000 \n" 404 " lui %1, 0x8000 \n"
433 " sc %1, %0 \n" 405 " sc %1, %0 \n"
434 " beqz %1, 3f \n" 406 " li %2, 1 \n"
435 " li %2, 1 \n" 407 "2: \n"
436 "2: \n" 408 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
437 __WEAK_LLSC_MB 409 : "m" (rw->lock)
438 " .subsection 2 \n" 410 : "memory");
439 "3: b 1b \n" 411 } while (unlikely(!tmp));
440 " li %2, 0 \n" 412
441 " .previous \n" 413 smp_llsc_mb();
442 " .set reorder \n"
443 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
444 : "m" (rw->lock)
445 : "memory");
446 } 414 }
447 415
448 return ret; 416 return ret;
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index c99384018161..a89d1b10d027 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -139,7 +139,7 @@
1391: move ra, k0 1391: move ra, k0
140 li k0, 3 140 li k0, 3
141 mtc0 k0, $22 141 mtc0 k0, $22
142#endif /* CONFIG_CPU_LOONGSON2F */ 142#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
143#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 143#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
144 lui k1, %hi(kernelsp) 144 lui k1, %hi(kernelsp)
145#else 145#else
@@ -189,6 +189,7 @@
189 LONG_S $0, PT_R0(sp) 189 LONG_S $0, PT_R0(sp)
190 mfc0 v1, CP0_STATUS 190 mfc0 v1, CP0_STATUS
191 LONG_S $2, PT_R2(sp) 191 LONG_S $2, PT_R2(sp)
192 LONG_S v1, PT_STATUS(sp)
192#ifdef CONFIG_MIPS_MT_SMTC 193#ifdef CONFIG_MIPS_MT_SMTC
193 /* 194 /*
194 * Ideally, these instructions would be shuffled in 195 * Ideally, these instructions would be shuffled in
@@ -200,21 +201,20 @@
200 LONG_S k0, PT_TCSTATUS(sp) 201 LONG_S k0, PT_TCSTATUS(sp)
201#endif /* CONFIG_MIPS_MT_SMTC */ 202#endif /* CONFIG_MIPS_MT_SMTC */
202 LONG_S $4, PT_R4(sp) 203 LONG_S $4, PT_R4(sp)
203 LONG_S $5, PT_R5(sp)
204 LONG_S v1, PT_STATUS(sp)
205 mfc0 v1, CP0_CAUSE 204 mfc0 v1, CP0_CAUSE
206 LONG_S $6, PT_R6(sp) 205 LONG_S $5, PT_R5(sp)
207 LONG_S $7, PT_R7(sp)
208 LONG_S v1, PT_CAUSE(sp) 206 LONG_S v1, PT_CAUSE(sp)
207 LONG_S $6, PT_R6(sp)
209 MFC0 v1, CP0_EPC 208 MFC0 v1, CP0_EPC
209 LONG_S $7, PT_R7(sp)
210#ifdef CONFIG_64BIT 210#ifdef CONFIG_64BIT
211 LONG_S $8, PT_R8(sp) 211 LONG_S $8, PT_R8(sp)
212 LONG_S $9, PT_R9(sp) 212 LONG_S $9, PT_R9(sp)
213#endif 213#endif
214 LONG_S v1, PT_EPC(sp)
214 LONG_S $25, PT_R25(sp) 215 LONG_S $25, PT_R25(sp)
215 LONG_S $28, PT_R28(sp) 216 LONG_S $28, PT_R28(sp)
216 LONG_S $31, PT_R31(sp) 217 LONG_S $31, PT_R31(sp)
217 LONG_S v1, PT_EPC(sp)
218 ori $28, sp, _THREAD_MASK 218 ori $28, sp, _THREAD_MASK
219 xori $28, _THREAD_MASK 219 xori $28, _THREAD_MASK
220#ifdef CONFIG_CPU_CAVIUM_OCTEON 220#ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 178f7924149a..895320e25662 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -58,8 +58,12 @@ struct thread_info {
58#define init_stack (init_thread_union.stack) 58#define init_stack (init_thread_union.stack)
59 59
60/* How to get the thread information struct from C. */ 60/* How to get the thread information struct from C. */
61register struct thread_info *__current_thread_info __asm__("$28"); 61static inline struct thread_info *current_thread_info(void)
62#define current_thread_info() __current_thread_info 62{
63 register struct thread_info *__current_thread_info __asm__("$28");
64
65 return __current_thread_info;
66}
63 67
64#endif /* !__ASSEMBLY__ */ 68#endif /* !__ASSEMBLY__ */
65 69
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index debc8009bd58..2d7b9df4542d 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -52,13 +52,15 @@ extern int (*perf_irq)(void);
52 */ 52 */
53extern unsigned int __weak get_c0_compare_int(void); 53extern unsigned int __weak get_c0_compare_int(void);
54extern int r4k_clockevent_init(void); 54extern int r4k_clockevent_init(void);
55extern int smtc_clockevent_init(void);
56extern int gic_clockevent_init(void);
55 57
56static inline int mips_clockevent_init(void) 58static inline int mips_clockevent_init(void)
57{ 59{
58#ifdef CONFIG_MIPS_MT_SMTC 60#ifdef CONFIG_MIPS_MT_SMTC
59 extern int smtc_clockevent_init(void);
60
61 return smtc_clockevent_init(); 61 return smtc_clockevent_init();
62#elif defined(CONFIG_CEVT_GIC)
63 return (gic_clockevent_init() | r4k_clockevent_init());
62#elif defined(CONFIG_CEVT_R4K) 64#elif defined(CONFIG_CEVT_R4K)
63 return r4k_clockevent_init(); 65 return r4k_clockevent_init();
64#else 66#else
@@ -69,9 +71,7 @@ static inline int mips_clockevent_init(void)
69/* 71/*
70 * Initialize the count register as a clocksource 72 * Initialize the count register as a clocksource
71 */ 73 */
72#ifdef CONFIG_CSRC_R4K
73extern int init_r4k_clocksource(void); 74extern int init_r4k_clocksource(void);
74#endif
75 75
76static inline int init_mips_clocksource(void) 76static inline int init_mips_clocksource(void)
77{ 77{
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index bd87e36bf26a..f3fa3750f577 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -23,7 +23,11 @@
23 */ 23 */
24#ifdef CONFIG_32BIT 24#ifdef CONFIG_32BIT
25 25
26#define __UA_LIMIT 0x80000000UL 26#ifdef CONFIG_KVM_GUEST
27#define __UA_LIMIT 0x40000000UL
28#else
29#define __UA_LIMIT 0x80000000UL
30#endif
27 31
28#define __UA_ADDR ".word" 32#define __UA_ADDR ".word"
29#define __UA_LA "la" 33#define __UA_LA "la"
@@ -55,8 +59,13 @@ extern u64 __ua_limit;
55 * address in this range it's the process's problem, not ours :-) 59 * address in this range it's the process's problem, not ours :-)
56 */ 60 */
57 61
62#ifdef CONFIG_KVM_GUEST
63#define KERNEL_DS ((mm_segment_t) { 0x80000000UL })
64#define USER_DS ((mm_segment_t) { 0xC0000000UL })
65#else
58#define KERNEL_DS ((mm_segment_t) { 0UL }) 66#define KERNEL_DS ((mm_segment_t) { 0UL })
59#define USER_DS ((mm_segment_t) { __UA_LIMIT }) 67#define USER_DS ((mm_segment_t) { __UA_LIMIT })
68#endif
60 69
61#define VERIFY_READ 0 70#define VERIFY_READ 0
62#define VERIFY_WRITE 1 71#define VERIFY_WRITE 1
@@ -261,6 +270,7 @@ do { \
261 __asm__ __volatile__( \ 270 __asm__ __volatile__( \
262 "1: " insn " %1, %3 \n" \ 271 "1: " insn " %1, %3 \n" \
263 "2: \n" \ 272 "2: \n" \
273 " .insn \n" \
264 " .section .fixup,\"ax\" \n" \ 274 " .section .fixup,\"ax\" \n" \
265 "3: li %0, %4 \n" \ 275 "3: li %0, %4 \n" \
266 " j 2b \n" \ 276 " j 2b \n" \
@@ -287,7 +297,9 @@ do { \
287 __asm__ __volatile__( \ 297 __asm__ __volatile__( \
288 "1: lw %1, (%3) \n" \ 298 "1: lw %1, (%3) \n" \
289 "2: lw %D1, 4(%3) \n" \ 299 "2: lw %D1, 4(%3) \n" \
290 "3: .section .fixup,\"ax\" \n" \ 300 "3: \n" \
301 " .insn \n" \
302 " .section .fixup,\"ax\" \n" \
291 "4: li %0, %4 \n" \ 303 "4: li %0, %4 \n" \
292 " move %1, $0 \n" \ 304 " move %1, $0 \n" \
293 " move %D1, $0 \n" \ 305 " move %D1, $0 \n" \
@@ -355,6 +367,7 @@ do { \
355 __asm__ __volatile__( \ 367 __asm__ __volatile__( \
356 "1: " insn " %z2, %3 # __put_user_asm\n" \ 368 "1: " insn " %z2, %3 # __put_user_asm\n" \
357 "2: \n" \ 369 "2: \n" \
370 " .insn \n" \
358 " .section .fixup,\"ax\" \n" \ 371 " .section .fixup,\"ax\" \n" \
359 "3: li %0, %4 \n" \ 372 "3: li %0, %4 \n" \
360 " j 2b \n" \ 373 " j 2b \n" \
@@ -373,6 +386,7 @@ do { \
373 "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ 386 "1: sw %2, (%3) # __put_user_asm_ll32 \n" \
374 "2: sw %D2, 4(%3) \n" \ 387 "2: sw %D2, 4(%3) \n" \
375 "3: \n" \ 388 "3: \n" \
389 " .insn \n" \
376 " .section .fixup,\"ax\" \n" \ 390 " .section .fixup,\"ax\" \n" \
377 "4: li %0, %4 \n" \ 391 "4: li %0, %4 \n" \
378 " j 3b \n" \ 392 " j 3b \n" \
@@ -524,6 +538,7 @@ do { \
524 __asm__ __volatile__( \ 538 __asm__ __volatile__( \
525 "1: " insn " %1, %3 \n" \ 539 "1: " insn " %1, %3 \n" \
526 "2: \n" \ 540 "2: \n" \
541 " .insn \n" \
527 " .section .fixup,\"ax\" \n" \ 542 " .section .fixup,\"ax\" \n" \
528 "3: li %0, %4 \n" \ 543 "3: li %0, %4 \n" \
529 " j 2b \n" \ 544 " j 2b \n" \
@@ -549,7 +564,9 @@ do { \
549 "1: ulw %1, (%3) \n" \ 564 "1: ulw %1, (%3) \n" \
550 "2: ulw %D1, 4(%3) \n" \ 565 "2: ulw %D1, 4(%3) \n" \
551 " move %0, $0 \n" \ 566 " move %0, $0 \n" \
552 "3: .section .fixup,\"ax\" \n" \ 567 "3: \n" \
568 " .insn \n" \
569 " .section .fixup,\"ax\" \n" \
553 "4: li %0, %4 \n" \ 570 "4: li %0, %4 \n" \
554 " move %1, $0 \n" \ 571 " move %1, $0 \n" \
555 " move %D1, $0 \n" \ 572 " move %D1, $0 \n" \
@@ -616,6 +633,7 @@ do { \
616 __asm__ __volatile__( \ 633 __asm__ __volatile__( \
617 "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ 634 "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \
618 "2: \n" \ 635 "2: \n" \
636 " .insn \n" \
619 " .section .fixup,\"ax\" \n" \ 637 " .section .fixup,\"ax\" \n" \
620 "3: li %0, %4 \n" \ 638 "3: li %0, %4 \n" \
621 " j 2b \n" \ 639 " j 2b \n" \
@@ -634,6 +652,7 @@ do { \
634 "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ 652 "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \
635 "2: sw %D2, 4(%3) \n" \ 653 "2: sw %D2, 4(%3) \n" \
636 "3: \n" \ 654 "3: \n" \
655 " .insn \n" \
637 " .section .fixup,\"ax\" \n" \ 656 " .section .fixup,\"ax\" \n" \
638 "4: li %0, %4 \n" \ 657 "4: li %0, %4 \n" \
639 " j 3b \n" \ 658 " j 3b \n" \
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 058e941626a6..370d967725c2 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -6,7 +6,7 @@
6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
7 * Copyright (C) 2005 Maciej W. Rozycki 7 * Copyright (C) 2005 Maciej W. Rozycki
8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2012 MIPS Technologies, Inc. 9 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
10 */ 10 */
11 11
12#include <linux/types.h> 12#include <linux/types.h>
@@ -22,44 +22,75 @@
22#define UASM_EXPORT_SYMBOL(sym) 22#define UASM_EXPORT_SYMBOL(sym)
23#endif 23#endif
24 24
25#define _UASM_ISA_CLASSIC 0
26#define _UASM_ISA_MICROMIPS 1
27
28#ifndef UASM_ISA
29#ifdef CONFIG_CPU_MICROMIPS
30#define UASM_ISA _UASM_ISA_MICROMIPS
31#else
32#define UASM_ISA _UASM_ISA_CLASSIC
33#endif
34#endif
35
36#if (UASM_ISA == _UASM_ISA_CLASSIC)
37#ifdef CONFIG_CPU_MICROMIPS
38#define ISAOPC(op) CL_uasm_i##op
39#define ISAFUNC(x) CL_##x
40#else
41#define ISAOPC(op) uasm_i##op
42#define ISAFUNC(x) x
43#endif
44#elif (UASM_ISA == _UASM_ISA_MICROMIPS)
45#ifdef CONFIG_CPU_MICROMIPS
46#define ISAOPC(op) uasm_i##op
47#define ISAFUNC(x) x
48#else
49#define ISAOPC(op) MM_uasm_i##op
50#define ISAFUNC(x) MM_##x
51#endif
52#else
53#error Unsupported micro-assembler ISA!!!
54#endif
55
25#define Ip_u1u2u3(op) \ 56#define Ip_u1u2u3(op) \
26void __uasminit \ 57void __uasminit \
27uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 58ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
28 59
29#define Ip_u2u1u3(op) \ 60#define Ip_u2u1u3(op) \
30void __uasminit \ 61void __uasminit \
31uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 62ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
32 63
33#define Ip_u3u1u2(op) \ 64#define Ip_u3u1u2(op) \
34void __uasminit \ 65void __uasminit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 66ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
36 67
37#define Ip_u1u2s3(op) \ 68#define Ip_u1u2s3(op) \
38void __uasminit \ 69void __uasminit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 70ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
40 71
41#define Ip_u2s3u1(op) \ 72#define Ip_u2s3u1(op) \
42void __uasminit \ 73void __uasminit \
43uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) 74ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c)
44 75
45#define Ip_u2u1s3(op) \ 76#define Ip_u2u1s3(op) \
46void __uasminit \ 77void __uasminit \
47uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 78ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c)
48 79
49#define Ip_u2u1msbu3(op) \ 80#define Ip_u2u1msbu3(op) \
50void __uasminit \ 81void __uasminit \
51uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ 82ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
52 unsigned int d) 83 unsigned int d)
53 84
54#define Ip_u1u2(op) \ 85#define Ip_u1u2(op) \
55void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 86void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
56 87
57#define Ip_u1s2(op) \ 88#define Ip_u1s2(op) \
58void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b) 89void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
59 90
60#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a) 91#define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a)
61 92
62#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf) 93#define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf)
63 94
64Ip_u2u1s3(_addiu); 95Ip_u2u1s3(_addiu);
65Ip_u3u1u2(_addu); 96Ip_u3u1u2(_addu);
@@ -132,19 +163,20 @@ struct uasm_label {
132 int lab; 163 int lab;
133}; 164};
134 165
135void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); 166void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr,
167 int lid);
136#ifdef CONFIG_64BIT 168#ifdef CONFIG_64BIT
137int uasm_in_compat_space_p(long addr); 169int ISAFUNC(uasm_in_compat_space_p)(long addr);
138#endif 170#endif
139int uasm_rel_hi(long val); 171int ISAFUNC(uasm_rel_hi)(long val);
140int uasm_rel_lo(long val); 172int ISAFUNC(uasm_rel_lo)(long val);
141void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); 173void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr);
142void UASM_i_LA(u32 **buf, unsigned int rs, long addr); 174void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr);
143 175
144#define UASM_L_LA(lb) \ 176#define UASM_L_LA(lb) \
145static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 177static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \
146{ \ 178{ \
147 uasm_build_label(lab, addr, label##lb); \ 179 ISAFUNC(uasm_build_label)(lab, addr, label##lb); \
148} 180}
149 181
150/* convenience macros for instructions */ 182/* convenience macros for instructions */
@@ -196,27 +228,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
196 unsigned int a2, unsigned int a3) 228 unsigned int a2, unsigned int a3)
197{ 229{
198 if (a3 < 32) 230 if (a3 < 32)
199 uasm_i_drotr(p, a1, a2, a3); 231 ISAOPC(_drotr)(p, a1, a2, a3);
200 else 232 else
201 uasm_i_drotr32(p, a1, a2, a3 - 32); 233 ISAOPC(_drotr32)(p, a1, a2, a3 - 32);
202} 234}
203 235
204static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, 236static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
205 unsigned int a2, unsigned int a3) 237 unsigned int a2, unsigned int a3)
206{ 238{
207 if (a3 < 32) 239 if (a3 < 32)
208 uasm_i_dsll(p, a1, a2, a3); 240 ISAOPC(_dsll)(p, a1, a2, a3);
209 else 241 else
210 uasm_i_dsll32(p, a1, a2, a3 - 32); 242 ISAOPC(_dsll32)(p, a1, a2, a3 - 32);
211} 243}
212 244
213static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, 245static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
214 unsigned int a2, unsigned int a3) 246 unsigned int a2, unsigned int a3)
215{ 247{
216 if (a3 < 32) 248 if (a3 < 32)
217 uasm_i_dsrl(p, a1, a2, a3); 249 ISAOPC(_dsrl)(p, a1, a2, a3);
218 else 250 else
219 uasm_i_dsrl32(p, a1, a2, a3 - 32); 251 ISAOPC(_dsrl32)(p, a1, a2, a3 - 32);
220} 252}
221 253
222/* Handle relocations. */ 254/* Handle relocations. */
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 4d078815eaa5..0f4aec2ad1e6 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -7,6 +7,7 @@
7 * 7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle 8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer 9 * Copyright (C) 2006 by Thiemo Seufer
10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 */ 11 */
11#ifndef _UAPI_ASM_INST_H 12#ifndef _UAPI_ASM_INST_H
12#define _UAPI_ASM_INST_H 13#define _UAPI_ASM_INST_H
@@ -193,6 +194,282 @@ enum lx_func {
193}; 194};
194 195
195/* 196/*
197 * (microMIPS) Major opcodes.
198 */
199enum mm_major_op {
200 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
201 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
202 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
203 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
204 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
205 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
206 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
207 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
208 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
209 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
210 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
211 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
212 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
213 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
214 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
215 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
216};
217
218/*
219 * (microMIPS) POOL32I minor opcodes.
220 */
221enum mm_32i_minor_op {
222 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
223 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
224 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
225 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
226 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
227 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
228 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
229 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
230 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
231};
232
233/*
234 * (microMIPS) POOL32A minor opcodes.
235 */
236enum mm_32a_minor_op {
237 mm_sll32_op = 0x000,
238 mm_ins_op = 0x00c,
239 mm_ext_op = 0x02c,
240 mm_pool32axf_op = 0x03c,
241 mm_srl32_op = 0x040,
242 mm_sra_op = 0x080,
243 mm_rotr_op = 0x0c0,
244 mm_lwxs_op = 0x118,
245 mm_addu32_op = 0x150,
246 mm_subu32_op = 0x1d0,
247 mm_and_op = 0x250,
248 mm_or32_op = 0x290,
249 mm_xor32_op = 0x310,
250};
251
252/*
253 * (microMIPS) POOL32B functions.
254 */
255enum mm_32b_func {
256 mm_lwc2_func = 0x0,
257 mm_lwp_func = 0x1,
258 mm_ldc2_func = 0x2,
259 mm_ldp_func = 0x4,
260 mm_lwm32_func = 0x5,
261 mm_cache_func = 0x6,
262 mm_ldm_func = 0x7,
263 mm_swc2_func = 0x8,
264 mm_swp_func = 0x9,
265 mm_sdc2_func = 0xa,
266 mm_sdp_func = 0xc,
267 mm_swm32_func = 0xd,
268 mm_sdm_func = 0xf,
269};
270
271/*
272 * (microMIPS) POOL32C functions.
273 */
274enum mm_32c_func {
275 mm_pref_func = 0x2,
276 mm_ll_func = 0x3,
277 mm_swr_func = 0x9,
278 mm_sc_func = 0xb,
279 mm_lwu_func = 0xe,
280};
281
282/*
283 * (microMIPS) POOL32AXF minor opcodes.
284 */
285enum mm_32axf_minor_op {
286 mm_mfc0_op = 0x003,
287 mm_mtc0_op = 0x00b,
288 mm_tlbp_op = 0x00d,
289 mm_jalr_op = 0x03c,
290 mm_tlbr_op = 0x04d,
291 mm_jalrhb_op = 0x07c,
292 mm_tlbwi_op = 0x08d,
293 mm_tlbwr_op = 0x0cd,
294 mm_jalrs_op = 0x13c,
295 mm_jalrshb_op = 0x17c,
296 mm_syscall_op = 0x22d,
297 mm_eret_op = 0x3cd,
298};
299
300/*
301 * (microMIPS) POOL32F minor opcodes.
302 */
303enum mm_32f_minor_op {
304 mm_32f_00_op = 0x00,
305 mm_32f_01_op = 0x01,
306 mm_32f_02_op = 0x02,
307 mm_32f_10_op = 0x08,
308 mm_32f_11_op = 0x09,
309 mm_32f_12_op = 0x0a,
310 mm_32f_20_op = 0x10,
311 mm_32f_30_op = 0x18,
312 mm_32f_40_op = 0x20,
313 mm_32f_41_op = 0x21,
314 mm_32f_42_op = 0x22,
315 mm_32f_50_op = 0x28,
316 mm_32f_51_op = 0x29,
317 mm_32f_52_op = 0x2a,
318 mm_32f_60_op = 0x30,
319 mm_32f_70_op = 0x38,
320 mm_32f_73_op = 0x3b,
321 mm_32f_74_op = 0x3c,
322};
323
324/*
325 * (microMIPS) POOL32F secondary minor opcodes.
326 */
327enum mm_32f_10_minor_op {
328 mm_lwxc1_op = 0x1,
329 mm_swxc1_op,
330 mm_ldxc1_op,
331 mm_sdxc1_op,
332 mm_luxc1_op,
333 mm_suxc1_op,
334};
335
336enum mm_32f_func {
337 mm_lwxc1_func = 0x048,
338 mm_swxc1_func = 0x088,
339 mm_ldxc1_func = 0x0c8,
340 mm_sdxc1_func = 0x108,
341};
342
343/*
344 * (microMIPS) POOL32F secondary minor opcodes.
345 */
346enum mm_32f_40_minor_op {
347 mm_fmovf_op,
348 mm_fmovt_op,
349};
350
351/*
352 * (microMIPS) POOL32F secondary minor opcodes.
353 */
354enum mm_32f_60_minor_op {
355 mm_fadd_op,
356 mm_fsub_op,
357 mm_fmul_op,
358 mm_fdiv_op,
359};
360
361/*
362 * (microMIPS) POOL32F secondary minor opcodes.
363 */
364enum mm_32f_70_minor_op {
365 mm_fmovn_op,
366 mm_fmovz_op,
367};
368
369/*
370 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
371 */
372enum mm_32f_73_minor_op {
373 mm_fmov0_op = 0x01,
374 mm_fcvtl_op = 0x04,
375 mm_movf0_op = 0x05,
376 mm_frsqrt_op = 0x08,
377 mm_ffloorl_op = 0x0c,
378 mm_fabs0_op = 0x0d,
379 mm_fcvtw_op = 0x24,
380 mm_movt0_op = 0x25,
381 mm_fsqrt_op = 0x28,
382 mm_ffloorw_op = 0x2c,
383 mm_fneg0_op = 0x2d,
384 mm_cfc1_op = 0x40,
385 mm_frecip_op = 0x48,
386 mm_fceill_op = 0x4c,
387 mm_fcvtd0_op = 0x4d,
388 mm_ctc1_op = 0x60,
389 mm_fceilw_op = 0x6c,
390 mm_fcvts0_op = 0x6d,
391 mm_mfc1_op = 0x80,
392 mm_fmov1_op = 0x81,
393 mm_movf1_op = 0x85,
394 mm_ftruncl_op = 0x8c,
395 mm_fabs1_op = 0x8d,
396 mm_mtc1_op = 0xa0,
397 mm_movt1_op = 0xa5,
398 mm_ftruncw_op = 0xac,
399 mm_fneg1_op = 0xad,
400 mm_froundl_op = 0xcc,
401 mm_fcvtd1_op = 0xcd,
402 mm_froundw_op = 0xec,
403 mm_fcvts1_op = 0xed,
404};
405
406/*
407 * (microMIPS) POOL16C minor opcodes.
408 */
409enum mm_16c_minor_op {
410 mm_lwm16_op = 0x04,
411 mm_swm16_op = 0x05,
412 mm_jr16_op = 0x18,
413 mm_jrc_op = 0x1a,
414 mm_jalr16_op = 0x1c,
415 mm_jalrs16_op = 0x1e,
416};
417
418/*
419 * (microMIPS) POOL16D minor opcodes.
420 */
421enum mm_16d_minor_op {
422 mm_addius5_func,
423 mm_addiusp_func,
424};
425
426/*
427 * (MIPS16e) opcodes.
428 */
429enum MIPS16e_ops {
430 MIPS16e_jal_op = 003,
431 MIPS16e_ld_op = 007,
432 MIPS16e_i8_op = 014,
433 MIPS16e_sd_op = 017,
434 MIPS16e_lb_op = 020,
435 MIPS16e_lh_op = 021,
436 MIPS16e_lwsp_op = 022,
437 MIPS16e_lw_op = 023,
438 MIPS16e_lbu_op = 024,
439 MIPS16e_lhu_op = 025,
440 MIPS16e_lwpc_op = 026,
441 MIPS16e_lwu_op = 027,
442 MIPS16e_sb_op = 030,
443 MIPS16e_sh_op = 031,
444 MIPS16e_swsp_op = 032,
445 MIPS16e_sw_op = 033,
446 MIPS16e_rr_op = 035,
447 MIPS16e_extend_op = 036,
448 MIPS16e_i64_op = 037,
449};
450
451enum MIPS16e_i64_func {
452 MIPS16e_ldsp_func,
453 MIPS16e_sdsp_func,
454 MIPS16e_sdrasp_func,
455 MIPS16e_dadjsp_func,
456 MIPS16e_ldpc_func,
457};
458
459enum MIPS16e_rr_func {
460 MIPS16e_jr_func,
461};
462
463enum MIPS6e_i8_func {
464 MIPS16e_swrasp_func = 02,
465};
466
467/*
468 * (microMIPS & MIPS16e) NOP instruction.
469 */
470#define MM_NOP16 0x0c00
471
472/*
196 * Damn ... bitfields depend from byteorder :-( 473 * Damn ... bitfields depend from byteorder :-(
197 */ 474 */
198#ifdef __MIPSEB__ 475#ifdef __MIPSEB__
@@ -311,6 +588,262 @@ struct v_format { /* MDMX vector format */
311 ;))))))) 588 ;)))))))
312}; 589};
313 590
591/*
592 * microMIPS instruction formats (32-bit length)
593 *
594 * NOTE:
595 * Parenthesis denote whether the format is a microMIPS instruction or
596 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
597 */
598struct fb_format { /* FPU branch format (MIPS32) */
599 BITFIELD_FIELD(unsigned int opcode : 6,
600 BITFIELD_FIELD(unsigned int bc : 5,
601 BITFIELD_FIELD(unsigned int cc : 3,
602 BITFIELD_FIELD(unsigned int flag : 2,
603 BITFIELD_FIELD(signed int simmediate : 16,
604 ;)))))
605};
606
607struct fp0_format { /* FPU multiply and add format (MIPS32) */
608 BITFIELD_FIELD(unsigned int opcode : 6,
609 BITFIELD_FIELD(unsigned int fmt : 5,
610 BITFIELD_FIELD(unsigned int ft : 5,
611 BITFIELD_FIELD(unsigned int fs : 5,
612 BITFIELD_FIELD(unsigned int fd : 5,
613 BITFIELD_FIELD(unsigned int func : 6,
614 ;))))))
615};
616
617struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
618 BITFIELD_FIELD(unsigned int opcode : 6,
619 BITFIELD_FIELD(unsigned int ft : 5,
620 BITFIELD_FIELD(unsigned int fs : 5,
621 BITFIELD_FIELD(unsigned int fd : 5,
622 BITFIELD_FIELD(unsigned int fmt : 3,
623 BITFIELD_FIELD(unsigned int op : 2,
624 BITFIELD_FIELD(unsigned int func : 6,
625 ;)))))))
626};
627
628struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
629 BITFIELD_FIELD(unsigned int opcode : 6,
630 BITFIELD_FIELD(unsigned int op : 5,
631 BITFIELD_FIELD(unsigned int rt : 5,
632 BITFIELD_FIELD(unsigned int fs : 5,
633 BITFIELD_FIELD(unsigned int fd : 5,
634 BITFIELD_FIELD(unsigned int func : 6,
635 ;))))))
636};
637
638struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
639 BITFIELD_FIELD(unsigned int opcode : 6,
640 BITFIELD_FIELD(unsigned int rt : 5,
641 BITFIELD_FIELD(unsigned int fs : 5,
642 BITFIELD_FIELD(unsigned int fmt : 2,
643 BITFIELD_FIELD(unsigned int op : 8,
644 BITFIELD_FIELD(unsigned int func : 6,
645 ;))))))
646};
647
648struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
649 BITFIELD_FIELD(unsigned int opcode : 6,
650 BITFIELD_FIELD(unsigned int fd : 5,
651 BITFIELD_FIELD(unsigned int fs : 5,
652 BITFIELD_FIELD(unsigned int cc : 3,
653 BITFIELD_FIELD(unsigned int zero : 2,
654 BITFIELD_FIELD(unsigned int fmt : 2,
655 BITFIELD_FIELD(unsigned int op : 3,
656 BITFIELD_FIELD(unsigned int func : 6,
657 ;))))))))
658};
659
660struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
661 BITFIELD_FIELD(unsigned int opcode : 6,
662 BITFIELD_FIELD(unsigned int rt : 5,
663 BITFIELD_FIELD(unsigned int fs : 5,
664 BITFIELD_FIELD(unsigned int fmt : 3,
665 BITFIELD_FIELD(unsigned int op : 7,
666 BITFIELD_FIELD(unsigned int func : 6,
667 ;))))))
668};
669
670struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
671 BITFIELD_FIELD(unsigned int opcode : 6,
672 BITFIELD_FIELD(unsigned int rt : 5,
673 BITFIELD_FIELD(unsigned int fs : 5,
674 BITFIELD_FIELD(unsigned int cc : 3,
675 BITFIELD_FIELD(unsigned int fmt : 3,
676 BITFIELD_FIELD(unsigned int cond : 4,
677 BITFIELD_FIELD(unsigned int func : 6,
678 ;)))))))
679};
680
681struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
682 BITFIELD_FIELD(unsigned int opcode : 6,
683 BITFIELD_FIELD(unsigned int index : 5,
684 BITFIELD_FIELD(unsigned int base : 5,
685 BITFIELD_FIELD(unsigned int fd : 5,
686 BITFIELD_FIELD(unsigned int op : 5,
687 BITFIELD_FIELD(unsigned int func : 6,
688 ;))))))
689};
690
691struct fp6_format { /* FPU madd and msub format (MIPS IV) */
692 BITFIELD_FIELD(unsigned int opcode : 6,
693 BITFIELD_FIELD(unsigned int fr : 5,
694 BITFIELD_FIELD(unsigned int ft : 5,
695 BITFIELD_FIELD(unsigned int fs : 5,
696 BITFIELD_FIELD(unsigned int fd : 5,
697 BITFIELD_FIELD(unsigned int func : 6,
698 ;))))))
699};
700
701struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
702 BITFIELD_FIELD(unsigned int opcode : 6,
703 BITFIELD_FIELD(unsigned int ft : 5,
704 BITFIELD_FIELD(unsigned int fs : 5,
705 BITFIELD_FIELD(unsigned int fd : 5,
706 BITFIELD_FIELD(unsigned int fr : 5,
707 BITFIELD_FIELD(unsigned int func : 6,
708 ;))))))
709};
710
711struct mm_i_format { /* Immediate format (microMIPS) */
712 BITFIELD_FIELD(unsigned int opcode : 6,
713 BITFIELD_FIELD(unsigned int rt : 5,
714 BITFIELD_FIELD(unsigned int rs : 5,
715 BITFIELD_FIELD(signed int simmediate : 16,
716 ;))))
717};
718
719struct mm_m_format { /* Multi-word load/store format (microMIPS) */
720 BITFIELD_FIELD(unsigned int opcode : 6,
721 BITFIELD_FIELD(unsigned int rd : 5,
722 BITFIELD_FIELD(unsigned int base : 5,
723 BITFIELD_FIELD(unsigned int func : 4,
724 BITFIELD_FIELD(signed int simmediate : 12,
725 ;)))))
726};
727
728struct mm_x_format { /* Scaled indexed load format (microMIPS) */
729 BITFIELD_FIELD(unsigned int opcode : 6,
730 BITFIELD_FIELD(unsigned int index : 5,
731 BITFIELD_FIELD(unsigned int base : 5,
732 BITFIELD_FIELD(unsigned int rd : 5,
733 BITFIELD_FIELD(unsigned int func : 11,
734 ;)))))
735};
736
737/*
738 * microMIPS instruction formats (16-bit length)
739 */
740struct mm_b0_format { /* Unconditional branch format (microMIPS) */
741 BITFIELD_FIELD(unsigned int opcode : 6,
742 BITFIELD_FIELD(signed int simmediate : 10,
743 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
744 ;)))
745};
746
747struct mm_b1_format { /* Conditional branch format (microMIPS) */
748 BITFIELD_FIELD(unsigned int opcode : 6,
749 BITFIELD_FIELD(unsigned int rs : 3,
750 BITFIELD_FIELD(signed int simmediate : 7,
751 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
752 ;))))
753};
754
755struct mm16_m_format { /* Multi-word load/store format */
756 BITFIELD_FIELD(unsigned int opcode : 6,
757 BITFIELD_FIELD(unsigned int func : 4,
758 BITFIELD_FIELD(unsigned int rlist : 2,
759 BITFIELD_FIELD(unsigned int imm : 4,
760 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
761 ;)))))
762};
763
764struct mm16_rb_format { /* Signed immediate format */
765 BITFIELD_FIELD(unsigned int opcode : 6,
766 BITFIELD_FIELD(unsigned int rt : 3,
767 BITFIELD_FIELD(unsigned int base : 3,
768 BITFIELD_FIELD(signed int simmediate : 4,
769 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
770 ;)))))
771};
772
773struct mm16_r3_format { /* Load from global pointer format */
774 BITFIELD_FIELD(unsigned int opcode : 6,
775 BITFIELD_FIELD(unsigned int rt : 3,
776 BITFIELD_FIELD(signed int simmediate : 7,
777 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
778 ;))))
779};
780
781struct mm16_r5_format { /* Load/store from stack pointer format */
782 BITFIELD_FIELD(unsigned int opcode : 6,
783 BITFIELD_FIELD(unsigned int rt : 5,
784 BITFIELD_FIELD(signed int simmediate : 5,
785 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
786 ;))))
787};
788
789/*
790 * MIPS16e instruction formats (16-bit length)
791 */
792struct m16e_rr {
793 BITFIELD_FIELD(unsigned int opcode : 5,
794 BITFIELD_FIELD(unsigned int rx : 3,
795 BITFIELD_FIELD(unsigned int nd : 1,
796 BITFIELD_FIELD(unsigned int l : 1,
797 BITFIELD_FIELD(unsigned int ra : 1,
798 BITFIELD_FIELD(unsigned int func : 5,
799 ;))))))
800};
801
802struct m16e_jal {
803 BITFIELD_FIELD(unsigned int opcode : 5,
804 BITFIELD_FIELD(unsigned int x : 1,
805 BITFIELD_FIELD(unsigned int imm20_16 : 5,
806 BITFIELD_FIELD(signed int imm25_21 : 5,
807 ;))))
808};
809
810struct m16e_i64 {
811 BITFIELD_FIELD(unsigned int opcode : 5,
812 BITFIELD_FIELD(unsigned int func : 3,
813 BITFIELD_FIELD(unsigned int imm : 8,
814 ;)))
815};
816
817struct m16e_ri64 {
818 BITFIELD_FIELD(unsigned int opcode : 5,
819 BITFIELD_FIELD(unsigned int func : 3,
820 BITFIELD_FIELD(unsigned int ry : 3,
821 BITFIELD_FIELD(unsigned int imm : 5,
822 ;))))
823};
824
825struct m16e_ri {
826 BITFIELD_FIELD(unsigned int opcode : 5,
827 BITFIELD_FIELD(unsigned int rx : 3,
828 BITFIELD_FIELD(unsigned int imm : 8,
829 ;)))
830};
831
832struct m16e_rri {
833 BITFIELD_FIELD(unsigned int opcode : 5,
834 BITFIELD_FIELD(unsigned int rx : 3,
835 BITFIELD_FIELD(unsigned int ry : 3,
836 BITFIELD_FIELD(unsigned int imm : 5,
837 ;))))
838};
839
840struct m16e_i8 {
841 BITFIELD_FIELD(unsigned int opcode : 5,
842 BITFIELD_FIELD(unsigned int func : 3,
843 BITFIELD_FIELD(unsigned int imm : 8,
844 ;)))
845};
846
314union mips_instruction { 847union mips_instruction {
315 unsigned int word; 848 unsigned int word;
316 unsigned short halfword[2]; 849 unsigned short halfword[2];
@@ -326,6 +859,37 @@ union mips_instruction {
326 struct b_format b_format; 859 struct b_format b_format;
327 struct ps_format ps_format; 860 struct ps_format ps_format;
328 struct v_format v_format; 861 struct v_format v_format;
862 struct fb_format fb_format;
863 struct fp0_format fp0_format;
864 struct mm_fp0_format mm_fp0_format;
865 struct fp1_format fp1_format;
866 struct mm_fp1_format mm_fp1_format;
867 struct mm_fp2_format mm_fp2_format;
868 struct mm_fp3_format mm_fp3_format;
869 struct mm_fp4_format mm_fp4_format;
870 struct mm_fp5_format mm_fp5_format;
871 struct fp6_format fp6_format;
872 struct mm_fp6_format mm_fp6_format;
873 struct mm_i_format mm_i_format;
874 struct mm_m_format mm_m_format;
875 struct mm_x_format mm_x_format;
876 struct mm_b0_format mm_b0_format;
877 struct mm_b1_format mm_b1_format;
878 struct mm16_m_format mm16_m_format ;
879 struct mm16_rb_format mm16_rb_format;
880 struct mm16_r3_format mm16_r3_format;
881 struct mm16_r5_format mm16_r5_format;
882};
883
884union mips16e_instruction {
885 unsigned int full : 16;
886 struct m16e_rr rr;
887 struct m16e_jal jal;
888 struct m16e_i64 i64;
889 struct m16e_ri64 ri64;
890 struct m16e_ri ri;
891 struct m16e_rri rri;
892 struct m16e_i8 i8;
329}; 893};
330 894
331#endif /* _UAPI_ASM_INST_H */ 895#endif /* _UAPI_ASM_INST_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 16:34:44 -0500