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authorManuel Lauss <manuel.lauss@googlemail.com>2009-10-07 14:15:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-02-27 06:52:53 -0500
commit788144656b8a862e724a1296e64ab6375eb541ed (patch)
tree96208eed56da25acdf9d923b9d9986e82dcd8944 /arch/mips/include
parent93e9cd8485b31e5a33f1040bff4d15e65c0b2d19 (diff)
MIPS: Alchemy: Stop IRQ name sharing
Eliminate the sharing of IRQ names among the differenct Alchemy variants. IRQ numbers need no longer be hidden behind a CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy code less reliant on a hardcoded subtype. This patch also renames the GPIO irq number constants. It's really an interrupt line, NOT a GPIO number! Code which relied on certain irq numbers to have the same name across all supported cpu subtypes is changed to determine current cpu subtype at runtime; in some places this isn't possible so a "compat" symbol is used. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h674
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h74
2 files changed, 367 insertions, 381 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 2dc87d3b0428..c2e233997b6c 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -174,6 +174,333 @@ void au_sleep(void);
174void save_au1xxx_intctl(void); 174void save_au1xxx_intctl(void);
175void restore_au1xxx_intctl(void); 175void restore_au1xxx_intctl(void);
176 176
177
178/* SOC Interrupt numbers */
179
180#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
181#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
182#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
183#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
184#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
185
186enum soc_au1000_ints {
187 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
188 AU1000_UART0_INT = AU1000_FIRST_INT,
189 AU1000_UART1_INT,
190 AU1000_UART2_INT,
191 AU1000_UART3_INT,
192 AU1000_SSI0_INT,
193 AU1000_SSI1_INT,
194 AU1000_DMA_INT_BASE,
195
196 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
197 AU1000_TOY_MATCH0_INT,
198 AU1000_TOY_MATCH1_INT,
199 AU1000_TOY_MATCH2_INT,
200 AU1000_RTC_INT,
201 AU1000_RTC_MATCH0_INT,
202 AU1000_RTC_MATCH1_INT,
203 AU1000_RTC_MATCH2_INT,
204 AU1000_IRDA_TX_INT,
205 AU1000_IRDA_RX_INT,
206 AU1000_USB_DEV_REQ_INT,
207 AU1000_USB_DEV_SUS_INT,
208 AU1000_USB_HOST_INT,
209 AU1000_ACSYNC_INT,
210 AU1000_MAC0_DMA_INT,
211 AU1000_MAC1_DMA_INT,
212 AU1000_I2S_UO_INT,
213 AU1000_AC97C_INT,
214 AU1000_GPIO0_INT,
215 AU1000_GPIO1_INT,
216 AU1000_GPIO2_INT,
217 AU1000_GPIO3_INT,
218 AU1000_GPIO4_INT,
219 AU1000_GPIO5_INT,
220 AU1000_GPIO6_INT,
221 AU1000_GPIO7_INT,
222 AU1000_GPIO8_INT,
223 AU1000_GPIO9_INT,
224 AU1000_GPIO10_INT,
225 AU1000_GPIO11_INT,
226 AU1000_GPIO12_INT,
227 AU1000_GPIO13_INT,
228 AU1000_GPIO14_INT,
229 AU1000_GPIO15_INT,
230 AU1000_GPIO16_INT,
231 AU1000_GPIO17_INT,
232 AU1000_GPIO18_INT,
233 AU1000_GPIO19_INT,
234 AU1000_GPIO20_INT,
235 AU1000_GPIO21_INT,
236 AU1000_GPIO22_INT,
237 AU1000_GPIO23_INT,
238 AU1000_GPIO24_INT,
239 AU1000_GPIO25_INT,
240 AU1000_GPIO26_INT,
241 AU1000_GPIO27_INT,
242 AU1000_GPIO28_INT,
243 AU1000_GPIO29_INT,
244 AU1000_GPIO30_INT,
245 AU1000_GPIO31_INT,
246};
247
248enum soc_au1100_ints {
249 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
250 AU1100_UART0_INT = AU1100_FIRST_INT,
251 AU1100_UART1_INT,
252 AU1100_SD_INT,
253 AU1100_UART3_INT,
254 AU1100_SSI0_INT,
255 AU1100_SSI1_INT,
256 AU1100_DMA_INT_BASE,
257
258 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
259 AU1100_TOY_MATCH0_INT,
260 AU1100_TOY_MATCH1_INT,
261 AU1100_TOY_MATCH2_INT,
262 AU1100_RTC_INT,
263 AU1100_RTC_MATCH0_INT,
264 AU1100_RTC_MATCH1_INT,
265 AU1100_RTC_MATCH2_INT,
266 AU1100_IRDA_TX_INT,
267 AU1100_IRDA_RX_INT,
268 AU1100_USB_DEV_REQ_INT,
269 AU1100_USB_DEV_SUS_INT,
270 AU1100_USB_HOST_INT,
271 AU1100_ACSYNC_INT,
272 AU1100_MAC0_DMA_INT,
273 AU1100_GPIO208_215_INT,
274 AU1100_LCD_INT,
275 AU1100_AC97C_INT,
276 AU1100_GPIO0_INT,
277 AU1100_GPIO1_INT,
278 AU1100_GPIO2_INT,
279 AU1100_GPIO3_INT,
280 AU1100_GPIO4_INT,
281 AU1100_GPIO5_INT,
282 AU1100_GPIO6_INT,
283 AU1100_GPIO7_INT,
284 AU1100_GPIO8_INT,
285 AU1100_GPIO9_INT,
286 AU1100_GPIO10_INT,
287 AU1100_GPIO11_INT,
288 AU1100_GPIO12_INT,
289 AU1100_GPIO13_INT,
290 AU1100_GPIO14_INT,
291 AU1100_GPIO15_INT,
292 AU1100_GPIO16_INT,
293 AU1100_GPIO17_INT,
294 AU1100_GPIO18_INT,
295 AU1100_GPIO19_INT,
296 AU1100_GPIO20_INT,
297 AU1100_GPIO21_INT,
298 AU1100_GPIO22_INT,
299 AU1100_GPIO23_INT,
300 AU1100_GPIO24_INT,
301 AU1100_GPIO25_INT,
302 AU1100_GPIO26_INT,
303 AU1100_GPIO27_INT,
304 AU1100_GPIO28_INT,
305 AU1100_GPIO29_INT,
306 AU1100_GPIO30_INT,
307 AU1100_GPIO31_INT,
308};
309
310enum soc_au1500_ints {
311 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
312 AU1500_UART0_INT = AU1500_FIRST_INT,
313 AU1500_PCI_INTA,
314 AU1500_PCI_INTB,
315 AU1500_UART3_INT,
316 AU1500_PCI_INTC,
317 AU1500_PCI_INTD,
318 AU1500_DMA_INT_BASE,
319
320 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
321 AU1500_TOY_MATCH0_INT,
322 AU1500_TOY_MATCH1_INT,
323 AU1500_TOY_MATCH2_INT,
324 AU1500_RTC_INT,
325 AU1500_RTC_MATCH0_INT,
326 AU1500_RTC_MATCH1_INT,
327 AU1500_RTC_MATCH2_INT,
328 AU1500_PCI_ERR_INT,
329 AU1500_RESERVED_INT,
330 AU1500_USB_DEV_REQ_INT,
331 AU1500_USB_DEV_SUS_INT,
332 AU1500_USB_HOST_INT,
333 AU1500_ACSYNC_INT,
334 AU1500_MAC0_DMA_INT,
335 AU1500_MAC1_DMA_INT,
336 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
337 AU1500_GPIO0_INT,
338 AU1500_GPIO1_INT,
339 AU1500_GPIO2_INT,
340 AU1500_GPIO3_INT,
341 AU1500_GPIO4_INT,
342 AU1500_GPIO5_INT,
343 AU1500_GPIO6_INT,
344 AU1500_GPIO7_INT,
345 AU1500_GPIO8_INT,
346 AU1500_GPIO9_INT,
347 AU1500_GPIO10_INT,
348 AU1500_GPIO11_INT,
349 AU1500_GPIO12_INT,
350 AU1500_GPIO13_INT,
351 AU1500_GPIO14_INT,
352 AU1500_GPIO15_INT,
353 AU1500_GPIO200_INT,
354 AU1500_GPIO201_INT,
355 AU1500_GPIO202_INT,
356 AU1500_GPIO203_INT,
357 AU1500_GPIO20_INT,
358 AU1500_GPIO204_INT,
359 AU1500_GPIO205_INT,
360 AU1500_GPIO23_INT,
361 AU1500_GPIO24_INT,
362 AU1500_GPIO25_INT,
363 AU1500_GPIO26_INT,
364 AU1500_GPIO27_INT,
365 AU1500_GPIO28_INT,
366 AU1500_GPIO206_INT,
367 AU1500_GPIO207_INT,
368 AU1500_GPIO208_215_INT,
369};
370
371enum soc_au1550_ints {
372 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
373 AU1550_UART0_INT = AU1550_FIRST_INT,
374 AU1550_PCI_INTA,
375 AU1550_PCI_INTB,
376 AU1550_DDMA_INT,
377 AU1550_CRYPTO_INT,
378 AU1550_PCI_INTC,
379 AU1550_PCI_INTD,
380 AU1550_PCI_RST_INT,
381 AU1550_UART1_INT,
382 AU1550_UART3_INT,
383 AU1550_PSC0_INT,
384 AU1550_PSC1_INT,
385 AU1550_PSC2_INT,
386 AU1550_PSC3_INT,
387 AU1550_TOY_INT,
388 AU1550_TOY_MATCH0_INT,
389 AU1550_TOY_MATCH1_INT,
390 AU1550_TOY_MATCH2_INT,
391 AU1550_RTC_INT,
392 AU1550_RTC_MATCH0_INT,
393 AU1550_RTC_MATCH1_INT,
394 AU1550_RTC_MATCH2_INT,
395
396 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
397 AU1550_USB_DEV_REQ_INT,
398 AU1550_USB_DEV_SUS_INT,
399 AU1550_USB_HOST_INT,
400 AU1550_MAC0_DMA_INT,
401 AU1550_MAC1_DMA_INT,
402 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
403 AU1550_GPIO1_INT,
404 AU1550_GPIO2_INT,
405 AU1550_GPIO3_INT,
406 AU1550_GPIO4_INT,
407 AU1550_GPIO5_INT,
408 AU1550_GPIO6_INT,
409 AU1550_GPIO7_INT,
410 AU1550_GPIO8_INT,
411 AU1550_GPIO9_INT,
412 AU1550_GPIO10_INT,
413 AU1550_GPIO11_INT,
414 AU1550_GPIO12_INT,
415 AU1550_GPIO13_INT,
416 AU1550_GPIO14_INT,
417 AU1550_GPIO15_INT,
418 AU1550_GPIO200_INT,
419 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
420 AU1550_GPIO16_INT,
421 AU1550_GPIO17_INT,
422 AU1550_GPIO20_INT,
423 AU1550_GPIO21_INT,
424 AU1550_GPIO22_INT,
425 AU1550_GPIO23_INT,
426 AU1550_GPIO24_INT,
427 AU1550_GPIO25_INT,
428 AU1550_GPIO26_INT,
429 AU1550_GPIO27_INT,
430 AU1550_GPIO28_INT,
431 AU1550_GPIO206_INT,
432 AU1550_GPIO207_INT,
433 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
434};
435
436enum soc_au1200_ints {
437 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
438 AU1200_UART0_INT = AU1200_FIRST_INT,
439 AU1200_SWT_INT,
440 AU1200_SD_INT,
441 AU1200_DDMA_INT,
442 AU1200_MAE_BE_INT,
443 AU1200_GPIO200_INT,
444 AU1200_GPIO201_INT,
445 AU1200_GPIO202_INT,
446 AU1200_UART1_INT,
447 AU1200_MAE_FE_INT,
448 AU1200_PSC0_INT,
449 AU1200_PSC1_INT,
450 AU1200_AES_INT,
451 AU1200_CAMERA_INT,
452 AU1200_TOY_INT,
453 AU1200_TOY_MATCH0_INT,
454 AU1200_TOY_MATCH1_INT,
455 AU1200_TOY_MATCH2_INT,
456 AU1200_RTC_INT,
457 AU1200_RTC_MATCH0_INT,
458 AU1200_RTC_MATCH1_INT,
459 AU1200_RTC_MATCH2_INT,
460 AU1200_GPIO203_INT,
461 AU1200_NAND_INT,
462 AU1200_GPIO204_INT,
463 AU1200_GPIO205_INT,
464 AU1200_GPIO206_INT,
465 AU1200_GPIO207_INT,
466 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
467 AU1200_USB_INT,
468 AU1200_LCD_INT,
469 AU1200_MAE_BOTH_INT,
470 AU1200_GPIO0_INT,
471 AU1200_GPIO1_INT,
472 AU1200_GPIO2_INT,
473 AU1200_GPIO3_INT,
474 AU1200_GPIO4_INT,
475 AU1200_GPIO5_INT,
476 AU1200_GPIO6_INT,
477 AU1200_GPIO7_INT,
478 AU1200_GPIO8_INT,
479 AU1200_GPIO9_INT,
480 AU1200_GPIO10_INT,
481 AU1200_GPIO11_INT,
482 AU1200_GPIO12_INT,
483 AU1200_GPIO13_INT,
484 AU1200_GPIO14_INT,
485 AU1200_GPIO15_INT,
486 AU1200_GPIO16_INT,
487 AU1200_GPIO17_INT,
488 AU1200_GPIO18_INT,
489 AU1200_GPIO19_INT,
490 AU1200_GPIO20_INT,
491 AU1200_GPIO21_INT,
492 AU1200_GPIO22_INT,
493 AU1200_GPIO23_INT,
494 AU1200_GPIO24_INT,
495 AU1200_GPIO25_INT,
496 AU1200_GPIO26_INT,
497 AU1200_GPIO27_INT,
498 AU1200_GPIO28_INT,
499 AU1200_GPIO29_INT,
500 AU1200_GPIO30_INT,
501 AU1200_GPIO31_INT,
502};
503
177#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 504#endif /* !defined (_LANGUAGE_ASSEMBLY) */
178 505
179/* 506/*
@@ -565,70 +892,9 @@ void restore_au1xxx_intctl(void);
565 892
566#define IC1_TESTBIT 0xB1800080 893#define IC1_TESTBIT 0xB1800080
567 894
568/* Interrupt Numbers */ 895
569/* Au1000 */ 896/* Au1000 */
570#ifdef CONFIG_SOC_AU1000 897#ifdef CONFIG_SOC_AU1000
571enum soc_au1000_ints {
572 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
573 AU1000_UART0_INT = AU1000_FIRST_INT,
574 AU1000_UART1_INT, /* au1000 */
575 AU1000_UART2_INT, /* au1000 */
576 AU1000_UART3_INT,
577 AU1000_SSI0_INT, /* au1000 */
578 AU1000_SSI1_INT, /* au1000 */
579 AU1000_DMA_INT_BASE,
580
581 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
582 AU1000_TOY_MATCH0_INT,
583 AU1000_TOY_MATCH1_INT,
584 AU1000_TOY_MATCH2_INT,
585 AU1000_RTC_INT,
586 AU1000_RTC_MATCH0_INT,
587 AU1000_RTC_MATCH1_INT,
588 AU1000_RTC_MATCH2_INT,
589 AU1000_IRDA_TX_INT, /* au1000 */
590 AU1000_IRDA_RX_INT, /* au1000 */
591 AU1000_USB_DEV_REQ_INT,
592 AU1000_USB_DEV_SUS_INT,
593 AU1000_USB_HOST_INT,
594 AU1000_ACSYNC_INT,
595 AU1000_MAC0_DMA_INT,
596 AU1000_MAC1_DMA_INT,
597 AU1000_I2S_UO_INT, /* au1000 */
598 AU1000_AC97C_INT,
599 AU1000_GPIO_0,
600 AU1000_GPIO_1,
601 AU1000_GPIO_2,
602 AU1000_GPIO_3,
603 AU1000_GPIO_4,
604 AU1000_GPIO_5,
605 AU1000_GPIO_6,
606 AU1000_GPIO_7,
607 AU1000_GPIO_8,
608 AU1000_GPIO_9,
609 AU1000_GPIO_10,
610 AU1000_GPIO_11,
611 AU1000_GPIO_12,
612 AU1000_GPIO_13,
613 AU1000_GPIO_14,
614 AU1000_GPIO_15,
615 AU1000_GPIO_16,
616 AU1000_GPIO_17,
617 AU1000_GPIO_18,
618 AU1000_GPIO_19,
619 AU1000_GPIO_20,
620 AU1000_GPIO_21,
621 AU1000_GPIO_22,
622 AU1000_GPIO_23,
623 AU1000_GPIO_24,
624 AU1000_GPIO_25,
625 AU1000_GPIO_26,
626 AU1000_GPIO_27,
627 AU1000_GPIO_28,
628 AU1000_GPIO_29,
629 AU1000_GPIO_30,
630 AU1000_GPIO_31,
631};
632 898
633#define UART0_ADDR 0xB1100000 899#define UART0_ADDR 0xB1100000
634#define UART1_ADDR 0xB1200000 900#define UART1_ADDR 0xB1200000
@@ -637,6 +903,7 @@ enum soc_au1000_ints {
637 903
638#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 904#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
639#define USB_HOST_CONFIG 0xB017FFFC 905#define USB_HOST_CONFIG 0xB017FFFC
906#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
640 907
641#define AU1000_ETH0_BASE 0xB0500000 908#define AU1000_ETH0_BASE 0xB0500000
642#define AU1000_ETH1_BASE 0xB0510000 909#define AU1000_ETH1_BASE 0xB0510000
@@ -647,78 +914,13 @@ enum soc_au1000_ints {
647 914
648/* Au1500 */ 915/* Au1500 */
649#ifdef CONFIG_SOC_AU1500 916#ifdef CONFIG_SOC_AU1500
650enum soc_au1500_ints {
651 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
652 AU1500_UART0_INT = AU1500_FIRST_INT,
653 AU1000_PCI_INTA, /* au1500 */
654 AU1000_PCI_INTB, /* au1500 */
655 AU1500_UART3_INT,
656 AU1000_PCI_INTC, /* au1500 */
657 AU1000_PCI_INTD, /* au1500 */
658 AU1000_DMA_INT_BASE,
659
660 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
661 AU1000_TOY_MATCH0_INT,
662 AU1000_TOY_MATCH1_INT,
663 AU1000_TOY_MATCH2_INT,
664 AU1000_RTC_INT,
665 AU1000_RTC_MATCH0_INT,
666 AU1000_RTC_MATCH1_INT,
667 AU1000_RTC_MATCH2_INT,
668 AU1500_PCI_ERR_INT,
669 AU1500_RESERVED_INT,
670 AU1000_USB_DEV_REQ_INT,
671 AU1000_USB_DEV_SUS_INT,
672 AU1000_USB_HOST_INT,
673 AU1000_ACSYNC_INT,
674 AU1500_MAC0_DMA_INT,
675 AU1500_MAC1_DMA_INT,
676 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
677 AU1000_GPIO_0,
678 AU1000_GPIO_1,
679 AU1000_GPIO_2,
680 AU1000_GPIO_3,
681 AU1000_GPIO_4,
682 AU1000_GPIO_5,
683 AU1000_GPIO_6,
684 AU1000_GPIO_7,
685 AU1000_GPIO_8,
686 AU1000_GPIO_9,
687 AU1000_GPIO_10,
688 AU1000_GPIO_11,
689 AU1000_GPIO_12,
690 AU1000_GPIO_13,
691 AU1000_GPIO_14,
692 AU1000_GPIO_15,
693 AU1500_GPIO_200,
694 AU1500_GPIO_201,
695 AU1500_GPIO_202,
696 AU1500_GPIO_203,
697 AU1500_GPIO_20,
698 AU1500_GPIO_204,
699 AU1500_GPIO_205,
700 AU1500_GPIO_23,
701 AU1500_GPIO_24,
702 AU1500_GPIO_25,
703 AU1500_GPIO_26,
704 AU1500_GPIO_27,
705 AU1500_GPIO_28,
706 AU1500_GPIO_206,
707 AU1500_GPIO_207,
708 AU1500_GPIO_208_215,
709};
710
711/* shortcuts */
712#define INTA AU1000_PCI_INTA
713#define INTB AU1000_PCI_INTB
714#define INTC AU1000_PCI_INTC
715#define INTD AU1000_PCI_INTD
716 917
717#define UART0_ADDR 0xB1100000 918#define UART0_ADDR 0xB1100000
718#define UART3_ADDR 0xB1400000 919#define UART3_ADDR 0xB1400000
719 920
720#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 921#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
721#define USB_HOST_CONFIG 0xB017fffc 922#define USB_HOST_CONFIG 0xB017fffc
923#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
722 924
723#define AU1500_ETH0_BASE 0xB1500000 925#define AU1500_ETH0_BASE 0xB1500000
724#define AU1500_ETH1_BASE 0xB1510000 926#define AU1500_ETH1_BASE 0xB1510000
@@ -729,67 +931,6 @@ enum soc_au1500_ints {
729 931
730/* Au1100 */ 932/* Au1100 */
731#ifdef CONFIG_SOC_AU1100 933#ifdef CONFIG_SOC_AU1100
732enum soc_au1100_ints {
733 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
734 AU1100_UART0_INT = AU1100_FIRST_INT,
735 AU1100_UART1_INT,
736 AU1100_SD_INT,
737 AU1100_UART3_INT,
738 AU1000_SSI0_INT,
739 AU1000_SSI1_INT,
740 AU1000_DMA_INT_BASE,
741
742 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
743 AU1000_TOY_MATCH0_INT,
744 AU1000_TOY_MATCH1_INT,
745 AU1000_TOY_MATCH2_INT,
746 AU1000_RTC_INT,
747 AU1000_RTC_MATCH0_INT,
748 AU1000_RTC_MATCH1_INT,
749 AU1000_RTC_MATCH2_INT,
750 AU1000_IRDA_TX_INT,
751 AU1000_IRDA_RX_INT,
752 AU1000_USB_DEV_REQ_INT,
753 AU1000_USB_DEV_SUS_INT,
754 AU1000_USB_HOST_INT,
755 AU1000_ACSYNC_INT,
756 AU1100_MAC0_DMA_INT,
757 AU1100_GPIO_208_215,
758 AU1100_LCD_INT,
759 AU1000_AC97C_INT,
760 AU1000_GPIO_0,
761 AU1000_GPIO_1,
762 AU1000_GPIO_2,
763 AU1000_GPIO_3,
764 AU1000_GPIO_4,
765 AU1000_GPIO_5,
766 AU1000_GPIO_6,
767 AU1000_GPIO_7,
768 AU1000_GPIO_8,
769 AU1000_GPIO_9,
770 AU1000_GPIO_10,
771 AU1000_GPIO_11,
772 AU1000_GPIO_12,
773 AU1000_GPIO_13,
774 AU1000_GPIO_14,
775 AU1000_GPIO_15,
776 AU1000_GPIO_16,
777 AU1000_GPIO_17,
778 AU1000_GPIO_18,
779 AU1000_GPIO_19,
780 AU1000_GPIO_20,
781 AU1000_GPIO_21,
782 AU1000_GPIO_22,
783 AU1000_GPIO_23,
784 AU1000_GPIO_24,
785 AU1000_GPIO_25,
786 AU1000_GPIO_26,
787 AU1000_GPIO_27,
788 AU1000_GPIO_28,
789 AU1000_GPIO_29,
790 AU1000_GPIO_30,
791 AU1000_GPIO_31,
792};
793 934
794#define UART0_ADDR 0xB1100000 935#define UART0_ADDR 0xB1100000
795#define UART1_ADDR 0xB1200000 936#define UART1_ADDR 0xB1200000
@@ -797,6 +938,7 @@ enum soc_au1100_ints {
797 938
798#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */ 939#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
799#define USB_HOST_CONFIG 0xB017FFFC 940#define USB_HOST_CONFIG 0xB017FFFC
941#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
800 942
801#define AU1100_ETH0_BASE 0xB0500000 943#define AU1100_ETH0_BASE 0xB0500000
802#define AU1100_MAC0_ENABLE 0xB0520000 944#define AU1100_MAC0_ENABLE 0xB0520000
@@ -804,80 +946,6 @@ enum soc_au1100_ints {
804#endif /* CONFIG_SOC_AU1100 */ 946#endif /* CONFIG_SOC_AU1100 */
805 947
806#ifdef CONFIG_SOC_AU1550 948#ifdef CONFIG_SOC_AU1550
807enum soc_au1550_ints {
808 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
809 AU1550_UART0_INT = AU1550_FIRST_INT,
810 AU1550_PCI_INTA,
811 AU1550_PCI_INTB,
812 AU1550_DDMA_INT,
813 AU1550_CRYPTO_INT,
814 AU1550_PCI_INTC,
815 AU1550_PCI_INTD,
816 AU1550_PCI_RST_INT,
817 AU1550_UART1_INT,
818 AU1550_UART3_INT,
819 AU1550_PSC0_INT,
820 AU1550_PSC1_INT,
821 AU1550_PSC2_INT,
822 AU1550_PSC3_INT,
823 AU1000_TOY_INT,
824 AU1000_TOY_MATCH0_INT,
825 AU1000_TOY_MATCH1_INT,
826 AU1000_TOY_MATCH2_INT,
827 AU1000_RTC_INT,
828 AU1000_RTC_MATCH0_INT,
829 AU1000_RTC_MATCH1_INT,
830 AU1000_RTC_MATCH2_INT,
831
832 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
833 AU1550_USB_DEV_REQ_INT,
834 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
835 AU1550_USB_DEV_SUS_INT,
836 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
837 AU1550_USB_HOST_INT,
838 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
839 AU1550_MAC0_DMA_INT,
840 AU1550_MAC1_DMA_INT,
841 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
842 AU1000_GPIO_1,
843 AU1000_GPIO_2,
844 AU1000_GPIO_3,
845 AU1000_GPIO_4,
846 AU1000_GPIO_5,
847 AU1000_GPIO_6,
848 AU1000_GPIO_7,
849 AU1000_GPIO_8,
850 AU1000_GPIO_9,
851 AU1000_GPIO_10,
852 AU1000_GPIO_11,
853 AU1000_GPIO_12,
854 AU1000_GPIO_13,
855 AU1000_GPIO_14,
856 AU1000_GPIO_15,
857 AU1550_GPIO_200,
858 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
859 AU1500_GPIO_16,
860 AU1500_GPIO_17,
861 AU1500_GPIO_20,
862 AU1500_GPIO_21,
863 AU1500_GPIO_22,
864 AU1500_GPIO_23,
865 AU1500_GPIO_24,
866 AU1500_GPIO_25,
867 AU1500_GPIO_26,
868 AU1500_GPIO_27,
869 AU1500_GPIO_28,
870 AU1500_GPIO_206,
871 AU1500_GPIO_207,
872 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
873};
874
875/* shortcuts */
876#define INTA AU1550_PCI_INTA
877#define INTB AU1550_PCI_INTB
878#define INTC AU1550_PCI_INTC
879#define INTD AU1550_PCI_INTD
880
881#define UART0_ADDR 0xB1100000 949#define UART0_ADDR 0xB1100000
882#define UART1_ADDR 0xB1200000 950#define UART1_ADDR 0xB1200000
883#define UART3_ADDR 0xB1400000 951#define UART3_ADDR 0xB1400000
@@ -885,6 +953,7 @@ enum soc_au1550_ints {
885#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */ 953#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
886#define USB_OHCI_LEN 0x00060000 954#define USB_OHCI_LEN 0x00060000
887#define USB_HOST_CONFIG 0xB4027ffc 955#define USB_HOST_CONFIG 0xB4027ffc
956#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
888 957
889#define AU1550_ETH0_BASE 0xB0500000 958#define AU1550_ETH0_BASE 0xB0500000
890#define AU1550_ETH1_BASE 0xB0510000 959#define AU1550_ETH1_BASE 0xB0510000
@@ -893,75 +962,8 @@ enum soc_au1550_ints {
893#define NUM_ETH_INTERFACES 2 962#define NUM_ETH_INTERFACES 2
894#endif /* CONFIG_SOC_AU1550 */ 963#endif /* CONFIG_SOC_AU1550 */
895 964
965
896#ifdef CONFIG_SOC_AU1200 966#ifdef CONFIG_SOC_AU1200
897enum soc_au1200_ints {
898 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
899 AU1200_UART0_INT = AU1200_FIRST_INT,
900 AU1200_SWT_INT,
901 AU1200_SD_INT,
902 AU1200_DDMA_INT,
903 AU1200_MAE_BE_INT,
904 AU1200_GPIO_200,
905 AU1200_GPIO_201,
906 AU1200_GPIO_202,
907 AU1200_UART1_INT,
908 AU1200_MAE_FE_INT,
909 AU1200_PSC0_INT,
910 AU1200_PSC1_INT,
911 AU1200_AES_INT,
912 AU1200_CAMERA_INT,
913 AU1000_TOY_INT,
914 AU1000_TOY_MATCH0_INT,
915 AU1000_TOY_MATCH1_INT,
916 AU1000_TOY_MATCH2_INT,
917 AU1000_RTC_INT,
918 AU1000_RTC_MATCH0_INT,
919 AU1000_RTC_MATCH1_INT,
920 AU1000_RTC_MATCH2_INT,
921 AU1200_GPIO_203,
922 AU1200_NAND_INT,
923 AU1200_GPIO_204,
924 AU1200_GPIO_205,
925 AU1200_GPIO_206,
926 AU1200_GPIO_207,
927 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
928 AU1200_USB_INT,
929 AU1000_USB_HOST_INT = AU1200_USB_INT,
930 AU1200_LCD_INT,
931 AU1200_MAE_BOTH_INT,
932 AU1000_GPIO_0,
933 AU1000_GPIO_1,
934 AU1000_GPIO_2,
935 AU1000_GPIO_3,
936 AU1000_GPIO_4,
937 AU1000_GPIO_5,
938 AU1000_GPIO_6,
939 AU1000_GPIO_7,
940 AU1000_GPIO_8,
941 AU1000_GPIO_9,
942 AU1000_GPIO_10,
943 AU1000_GPIO_11,
944 AU1000_GPIO_12,
945 AU1000_GPIO_13,
946 AU1000_GPIO_14,
947 AU1000_GPIO_15,
948 AU1000_GPIO_16,
949 AU1000_GPIO_17,
950 AU1000_GPIO_18,
951 AU1000_GPIO_19,
952 AU1000_GPIO_20,
953 AU1000_GPIO_21,
954 AU1000_GPIO_22,
955 AU1000_GPIO_23,
956 AU1000_GPIO_24,
957 AU1000_GPIO_25,
958 AU1000_GPIO_26,
959 AU1000_GPIO_27,
960 AU1000_GPIO_28,
961 AU1000_GPIO_29,
962 AU1000_GPIO_30,
963 AU1000_GPIO_31,
964};
965 967
966#define UART0_ADDR 0xB1100000 968#define UART0_ADDR 0xB1100000
967#define UART1_ADDR 0xB1200000 969#define UART1_ADDR 0xB1200000
@@ -990,15 +992,9 @@ enum soc_au1200_ints {
990#define USBMSRMCFG_RDCOMB 30 992#define USBMSRMCFG_RDCOMB 30
991#define USBMSRMCFG_PFEN 31 993#define USBMSRMCFG_PFEN 31
992 994
993#endif /* CONFIG_SOC_AU1200 */ 995#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
994 996
995#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) 997#endif /* CONFIG_SOC_AU1200 */
996#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
997#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
998#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
999
1000#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
1001#define INTX 0xFF /* not valid */
1002 998
1003/* Programmable Counters 0 and 1 */ 999/* Programmable Counters 0 and 1 */
1004#define SYS_BASE 0xB1900000 1000#define SYS_BASE 0xB1900000
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 91595fa89034..9cf32d9dbb21 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -35,15 +35,13 @@ static inline int au1000_gpio2_to_irq(int gpio)
35 return -ENXIO; 35 return -ENXIO;
36} 36}
37 37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq) 38static inline int au1000_irq_to_gpio(int irq)
40{ 39{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31)) 40 if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 41 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
43 42
44 return -ENXIO; 43 return -ENXIO;
45} 44}
46#endif
47 45
48static inline int au1500_gpio1_to_irq(int gpio) 46static inline int au1500_gpio1_to_irq(int gpio)
49{ 47{
@@ -71,27 +69,25 @@ static inline int au1500_gpio2_to_irq(int gpio)
71 return -ENXIO; 69 return -ENXIO;
72} 70}
73 71
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq) 72static inline int au1500_irq_to_gpio(int irq)
76{ 73{
77 switch (irq) { 74 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15: 75 case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
79 case AU1500_GPIO_20: 76 case AU1500_GPIO20_INT:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28: 77 case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 78 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203: 79 case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0; 80 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205: 81 case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4; 82 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207: 83 case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 84 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
88 case AU1500_GPIO_208_215: 85 case AU1500_GPIO208_215_INT:
89 return ALCHEMY_GPIO2_BASE + 8; 86 return ALCHEMY_GPIO2_BASE + 8;
90 } 87 }
91 88
92 return -ENXIO; 89 return -ENXIO;
93} 90}
94#endif
95 91
96static inline int au1100_gpio1_to_irq(int gpio) 92static inline int au1100_gpio1_to_irq(int gpio)
97{ 93{
@@ -108,19 +104,17 @@ static inline int au1100_gpio2_to_irq(int gpio)
108 return -ENXIO; 104 return -ENXIO;
109} 105}
110 106
111#ifdef CONFIG_SOC_AU1100
112static inline int au1100_irq_to_gpio(int irq) 107static inline int au1100_irq_to_gpio(int irq)
113{ 108{
114 switch (irq) { 109 switch (irq) {
115 case AU1000_GPIO_0 ... AU1000_GPIO_31: 110 case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
116 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 111 return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
117 case AU1100_GPIO_208_215: 112 case AU1100_GPIO208_215_INT:
118 return ALCHEMY_GPIO2_BASE + 8; 113 return ALCHEMY_GPIO2_BASE + 8;
119 } 114 }
120 115
121 return -ENXIO; 116 return -ENXIO;
122} 117}
123#endif
124 118
125static inline int au1550_gpio1_to_irq(int gpio) 119static inline int au1550_gpio1_to_irq(int gpio)
126{ 120{
@@ -149,24 +143,22 @@ static inline int au1550_gpio2_to_irq(int gpio)
149 return -ENXIO; 143 return -ENXIO;
150} 144}
151 145
152#ifdef CONFIG_SOC_AU1550
153static inline int au1550_irq_to_gpio(int irq) 146static inline int au1550_irq_to_gpio(int irq)
154{ 147{
155 switch (irq) { 148 switch (irq) {
156 case AU1000_GPIO_0 ... AU1000_GPIO_15: 149 case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
157 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 150 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
158 case AU1550_GPIO_200: 151 case AU1550_GPIO200_INT:
159 case AU1500_GPIO_201_205: 152 case AU1550_GPIO201_205_INT:
160 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0; 153 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
161 case AU1500_GPIO_16 ... AU1500_GPIO_28: 154 case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
162 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16; 155 return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
163 case AU1500_GPIO_206 ... AU1500_GPIO_208_218: 156 case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
164 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; 157 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
165 } 158 }
166 159
167 return -ENXIO; 160 return -ENXIO;
168} 161}
169#endif
170 162
171static inline int au1200_gpio1_to_irq(int gpio) 163static inline int au1200_gpio1_to_irq(int gpio)
172{ 164{
@@ -187,23 +179,21 @@ static inline int au1200_gpio2_to_irq(int gpio)
187 return -ENXIO; 179 return -ENXIO;
188} 180}
189 181
190#ifdef CONFIG_SOC_AU1200
191static inline int au1200_irq_to_gpio(int irq) 182static inline int au1200_irq_to_gpio(int irq)
192{ 183{
193 switch (irq) { 184 switch (irq) {
194 case AU1000_GPIO_0 ... AU1000_GPIO_31: 185 case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
195 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; 186 return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
196 case AU1200_GPIO_200 ... AU1200_GPIO_202: 187 case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
197 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0; 188 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
198 case AU1200_GPIO_203: 189 case AU1200_GPIO203_INT:
199 return ALCHEMY_GPIO2_BASE + 3; 190 return ALCHEMY_GPIO2_BASE + 3;
200 case AU1200_GPIO_204 ... AU1200_GPIO_208_215: 191 case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
201 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4; 192 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
202 } 193 }
203 194
204 return -ENXIO; 195 return -ENXIO;
205} 196}
206#endif
207 197
208/* 198/*
209 * GPIO1 block macros for common linux gpio functions. 199 * GPIO1 block macros for common linux gpio functions.
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 06:00:46 -0500