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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-23 18:22:14 -0500
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 04:57:20 -0500
commit58f07778ce9d32c22cecb1d8ef348001f0e705c9 (patch)
tree8b4462addd9058cbdf8f6085169f48c318fe7478 /arch/mips/include
parent54293ec3074a5fe61abd297502f68b2529a3dab3 (diff)
MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon/executive and asm/octeon.
These files are used to coordinate resource sharing between all of the programs running on the OCTEON SOC. The OCTEON processor has many CPU cores (current parts have up to 16, but more are possible). It also has a variety of on-chip hardware blocks for things like network acceleration, encryption and RAID. One typical configuration is to run Linux on several of the CPU cores, and other dedicated applications on the other cores. Resource allocation between the various programs running on the system (Linux kernel and other dedicated applications) needs to be coordinated. The code we use to do this we call the 'executive'. All of this resource allocation and sharing code is gathered together in the executive directory. Included in the patch set are the following files: cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation. All memory used by the Linux kernel is obtained here at boot time. cvmx-l2c.c -- Coordinates operations on the shared level 2 cache. octeon-model.c -- Probes chip capabilities and version. The corresponding headers are in asm/octeon. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/executive/Makefile create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h create mode 100644 arch/mips/include/asm/octeon/cvmx.h create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h create mode 100644 arch/mips/include/asm/octeon/octeon-model.h
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asm.h128
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h262
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h288
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h325
-rw-r--r--arch/mips/include/asm/octeon/cvmx-packet.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spinlock.h232
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sysinfo.h152
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h505
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h119
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h321
10 files changed, 2393 insertions, 0 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
new file mode 100644
index 000000000000..b21d3fc1ef91
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -0,0 +1,128 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This is file defines ASM primitives for the executive.
31 */
32#ifndef __CVMX_ASM_H__
33#define __CVMX_ASM_H__
34
35#include "octeon-model.h"
36
37/* other useful stuff */
38#define CVMX_SYNC asm volatile ("sync" : : : "memory")
39/* String version of SYNCW macro for using in inline asm constructs */
40#define CVMX_SYNCW_STR "syncw\nsyncw\n"
41#ifdef __OCTEON__
42
43/* Deprecated, will be removed in future release */
44#define CVMX_SYNCIO asm volatile ("nop")
45
46#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
47
48/* Deprecated, will be removed in future release */
49#define CVMX_SYNCIOALL asm volatile ("nop")
50
51/*
52 * We actually use two syncw instructions in a row when we need a write
53 * memory barrier. This is because the CN3XXX series of Octeons have
54 * errata Core-401. This can cause a single syncw to not enforce
55 * ordering under very rare conditions. Even if it is rare, better safe
56 * than sorry.
57 */
58#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
59
60/*
61 * Define new sync instructions to be normal SYNC instructions for
62 * operating systems that use threads.
63 */
64#define CVMX_SYNCWS CVMX_SYNCW
65#define CVMX_SYNCS CVMX_SYNC
66#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
67#else
68/*
69 * Not using a Cavium compiler, always use the slower sync so the
70 * assembler stays happy.
71 */
72/* Deprecated, will be removed in future release */
73#define CVMX_SYNCIO asm volatile ("nop")
74
75#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
76
77/* Deprecated, will be removed in future release */
78#define CVMX_SYNCIOALL asm volatile ("nop")
79
80#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
81#define CVMX_SYNCWS CVMX_SYNCW
82#define CVMX_SYNCS CVMX_SYNC
83#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
84#endif
85
86/*
87 * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
88 * (actually old value or zero) until that byte is stored to (by this or
89 * another processor. Note that the value of each byte is not only
90 * unpredictable, but may also change again - up until the point when one
91 * of the cores stores to the byte.
92 */
93#define CVMX_PREPARE_FOR_STORE(address, offset) \
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
95 [rbase] "d" (address))
96/*
97 * This is a command headed to the L2 controller to tell it to clear
98 * its dirty bit for a block. Basically, SW is telling HW that the
99 * current version of the block will not be used.
100 */
101#define CVMX_DONT_WRITE_BACK(address, offset) \
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
103 [rbase] "d" (address))
104
105/* flush stores, invalidate entire icache */
106#define CVMX_ICACHE_INVALIDATE \
107 { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
108
109/* flush stores, invalidate entire icache */
110#define CVMX_ICACHE_INVALIDATE2 \
111 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
112
113/* complete prefetches, invalidate entire dcache */
114#define CVMX_DCACHE_INVALIDATE \
115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
116
117
118#define CVMX_POP(result, input) \
119 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
120#define CVMX_DPOP(result, input) \
121 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
122
123/* some new cop0-like stuff */
124#define CVMX_RDHWR(result, regstr) \
125 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
126#define CVMX_RDHWRNV(result, regstr) \
127 asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
128#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
new file mode 100644
index 000000000000..692989acd8a9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -0,0 +1,262 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Header file containing the ABI with the bootloader.
30 */
31
32#ifndef __CVMX_BOOTINFO_H__
33#define __CVMX_BOOTINFO_H__
34
35/*
36 * Current major and minor versions of the CVMX bootinfo block that is
37 * passed from the bootloader to the application. This is versioned
38 * so that applications can properly handle multiple bootloader
39 * versions.
40 */
41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2
43
44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
46/*
47 * This structure is populated by the bootloader. For binary
48 * compatibility the only changes that should be made are
49 * adding members to the end of the structure, and the minor
50 * version should be incremented at that time.
51 * If an incompatible change is made, the major version
52 * must be incremented, and the minor version should be reset
53 * to 0.
54 */
55struct cvmx_bootinfo {
56 uint32_t major_version;
57 uint32_t minor_version;
58
59 uint64_t stack_top;
60 uint64_t heap_base;
61 uint64_t heap_end;
62 uint64_t desc_vaddr;
63
64 uint32_t exception_base_addr;
65 uint32_t stack_size;
66 uint32_t flags;
67 uint32_t core_mask;
68 /* DRAM size in megabytes */
69 uint32_t dram_size;
70 /* physical address of free memory descriptor block*/
71 uint32_t phy_mem_desc_addr;
72 /* used to pass flags from app to debugger */
73 uint32_t debugger_flags_base_addr;
74
75 /* CPU clock speed, in hz */
76 uint32_t eclock_hz;
77
78 /* DRAM clock speed, in hz */
79 uint32_t dclock_hz;
80
81 uint32_t reserved0;
82 uint16_t board_type;
83 uint8_t board_rev_major;
84 uint8_t board_rev_minor;
85 uint16_t reserved1;
86 uint8_t reserved2;
87 uint8_t reserved3;
88 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
89 uint8_t mac_addr_base[6];
90 uint8_t mac_addr_count;
91#if (CVMX_BOOTINFO_MIN_VER >= 1)
92 /*
93 * Several boards support compact flash on the Octeon boot
94 * bus. The CF memory spaces may be mapped to different
95 * addresses on different boards. These are the physical
96 * addresses, so care must be taken to use the correct
97 * XKPHYS/KSEG0 addressing depending on the application's
98 * ABI. These values will be 0 if CF is not present.
99 */
100 uint64_t compact_flash_common_base_addr;
101 uint64_t compact_flash_attribute_base_addr;
102 /*
103 * Base address of the LED display (as on EBT3000 board)
104 * This will be 0 if LED display not present.
105 */
106 uint64_t led_display_base_addr;
107#endif
108#if (CVMX_BOOTINFO_MIN_VER >= 2)
109 /* DFA reference clock in hz (if applicable)*/
110 uint32_t dfa_ref_clock_hz;
111
112 /*
113 * flags indicating various configuration options. These
114 * flags supercede the 'flags' variable and should be used
115 * instead if available.
116 */
117 uint32_t config_flags;
118#endif
119
120};
121
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
123#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
124#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
125#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
126/* This flag is set if the TLB mappings are not contained in the
127 * 0x10000000 - 0x20000000 boot bus region. */
128#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
129#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
130
131#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
132
133/* Type defines for board and chip types */
134enum cvmx_board_types_enum {
135 CVMX_BOARD_TYPE_NULL = 0,
136 CVMX_BOARD_TYPE_SIM = 1,
137 CVMX_BOARD_TYPE_EBT3000 = 2,
138 CVMX_BOARD_TYPE_KODAMA = 3,
139 CVMX_BOARD_TYPE_NIAGARA = 4,
140 CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
141 CVMX_BOARD_TYPE_THUNDER = 6,
142 CVMX_BOARD_TYPE_TRANTOR = 7,
143 CVMX_BOARD_TYPE_EBH3000 = 8,
144 CVMX_BOARD_TYPE_EBH3100 = 9,
145 CVMX_BOARD_TYPE_HIKARI = 10,
146 CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
147 CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
148 CVMX_BOARD_TYPE_KBP = 13,
149 /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
150 CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
151 CVMX_BOARD_TYPE_EBT5800 = 15,
152 CVMX_BOARD_TYPE_NICPRO2 = 16,
153 CVMX_BOARD_TYPE_EBH5600 = 17,
154 CVMX_BOARD_TYPE_EBH5601 = 18,
155 CVMX_BOARD_TYPE_EBH5200 = 19,
156 CVMX_BOARD_TYPE_BBGW_REF = 20,
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_MAX,
161
162 /*
163 * The range from CVMX_BOARD_TYPE_MAX to
164 * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
165 * SDK use.
166 */
167
168 /*
169 * Set aside a range for customer boards. These numbers are managed
170 * by Cavium.
171 */
172 CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
173 CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
174 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
175 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
176 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
177 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
178
179 /*
180 * Set aside a range for customer private use. The SDK won't
181 * use any numbers in this range.
182 */
183 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
184 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
185
186 /* The remaining range is reserved for future use. */
187};
188
189enum cvmx_chip_types_enum {
190 CVMX_CHIP_TYPE_NULL = 0,
191 CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
192 CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
193 CVMX_CHIP_TYPE_MAX,
194};
195
196/* Compatability alias for NAC38 name change, planned to be removed
197 * from SDK 1.7 */
198#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
199
200/* Functions to return string based on type */
201#define ENUM_BRD_TYPE_CASE(x) \
202 case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
203static inline const char *cvmx_board_type_to_string(enum
204 cvmx_board_types_enum type)
205{
206 switch (type) {
207 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
208 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
209 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
210 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
211 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
212 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
213 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
214 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
215 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
216 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
217 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
218 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
219 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
220 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
221 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
222 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
223 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
224 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
225 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
226 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
227 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232
233 /* Customer boards listed here */
234 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
240
241 /* Customer private range */
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
244 }
245 return "Unsupported Board";
246}
247
248#define ENUM_CHIP_TYPE_CASE(x) \
249 case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
250static inline const char *cvmx_chip_type_to_string(enum
251 cvmx_chip_types_enum type)
252{
253 switch (type) {
254 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
255 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
256 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
257 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
258 }
259 return "Unsupported Chip";
260}
261
262#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
new file mode 100644
index 000000000000..1cbe4b55889d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -0,0 +1,288 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#ifndef __CVMX_BOOTMEM_H__
34#define __CVMX_BOOTMEM_H__
35/* Must be multiple of 8, changing breaks ABI */
36#define CVMX_BOOTMEM_NAME_LEN 128
37
38/* Can change without breaking ABI */
39#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
40
41/* minimum alignment of bootmem alloced blocks */
42#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
43
44/* Flags for cvmx_bootmem_phy_mem* functions */
45/* Allocate from end of block instead of beginning */
46#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0)
47
48/* Don't do any locking. */
49#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1)
50
51/* First bytes of each free physical block of memory contain this structure,
52 * which is used to maintain the free memory list. Since the bootloader is
53 * only 32 bits, there is a union providing 64 and 32 bit versions. The
54 * application init code converts addresses to 64 bit addresses before the
55 * application starts.
56 */
57struct cvmx_bootmem_block_header {
58 /*
59 * Note: these are referenced from assembly routines in the
60 * bootloader, so this structure should not be changed
61 * without changing those routines as well.
62 */
63 uint64_t next_block_addr;
64 uint64_t size;
65
66};
67
68/*
69 * Structure for named memory blocks. Number of descriptors available
70 * can be changed without affecting compatiblity, but name length
71 * changes require a bump in the bootmem descriptor version Note: This
72 * structure must be naturally 64 bit aligned, as a single memory
73 * image will be used by both 32 and 64 bit programs.
74 */
75struct cvmx_bootmem_named_block_desc {
76 /* Base address of named block */
77 uint64_t base_addr;
78 /*
79 * Size actually allocated for named block (may differ from
80 * requested).
81 */
82 uint64_t size;
83 /* name of named block */
84 char name[CVMX_BOOTMEM_NAME_LEN];
85};
86
87/* Current descriptor versions */
88/* CVMX bootmem descriptor major version */
89#define CVMX_BOOTMEM_DESC_MAJ_VER 3
90
91/* CVMX bootmem descriptor minor version */
92#define CVMX_BOOTMEM_DESC_MIN_VER 0
93
94/* First three members of cvmx_bootmem_desc_t are left in original
95 * positions for backwards compatibility.
96 */
97struct cvmx_bootmem_desc {
98 /* spinlock to control access to list */
99 uint32_t lock;
100 /* flags for indicating various conditions */
101 uint32_t flags;
102 uint64_t head_addr;
103
104 /* Incremented when incompatible changes made */
105 uint32_t major_version;
106
107 /*
108 * Incremented changed when compatible changes made, reset to
109 * zero when major incremented.
110 */
111 uint32_t minor_version;
112
113 uint64_t app_data_addr;
114 uint64_t app_data_size;
115
116 /* number of elements in named blocks array */
117 uint32_t named_block_num_blocks;
118
119 /* length of name array in bootmem blocks */
120 uint32_t named_block_name_len;
121 /* address of named memory block descriptors */
122 uint64_t named_block_array_addr;
123
124};
125
126/**
127 * Initialize the boot alloc memory structures. This is
128 * normally called inside of cvmx_user_app_init()
129 *
130 * @mem_desc_ptr: Address of the free memory list
131 */
132extern int cvmx_bootmem_init(void *mem_desc_ptr);
133
134/**
135 * Allocate a block of memory from the free list that was passed
136 * to the application by the bootloader.
137 * This is an allocate-only algorithm, so freeing memory is not possible.
138 *
139 * @size: Size in bytes of block to allocate
140 * @alignment: Alignment required - must be power of 2
141 *
142 * Returns pointer to block of memory, NULL on error
143 */
144extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
145
146/**
147 * Allocate a block of memory from the free list that was
148 * passed to the application by the bootloader at a specific
149 * address. This is an allocate-only algorithm, so
150 * freeing memory is not possible. Allocation will fail if
151 * memory cannot be allocated at the specified address.
152 *
153 * @size: Size in bytes of block to allocate
154 * @address: Physical address to allocate memory at. If this memory is not
155 * available, the allocation fails.
156 * @alignment: Alignment required - must be power of 2
157 * Returns pointer to block of memory, NULL on error
158 */
159extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
160 uint64_t alignment);
161
162/**
163 * Allocate a block of memory from the free list that was
164 * passed to the application by the bootloader within a specified
165 * address range. This is an allocate-only algorithm, so
166 * freeing memory is not possible. Allocation will fail if
167 * memory cannot be allocated in the requested range.
168 *
169 * @size: Size in bytes of block to allocate
170 * @min_addr: defines the minimum address of the range
171 * @max_addr: defines the maximum address of the range
172 * @alignment: Alignment required - must be power of 2
173 * Returns pointer to block of memory, NULL on error
174 */
175extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
176 uint64_t min_addr, uint64_t max_addr);
177
178/**
179 * Frees a previously allocated named bootmem block.
180 *
181 * @name: name of block to free
182 *
183 * Returns 0 on failure,
184 * !0 on success
185 */
186extern int cvmx_bootmem_free_named(char *name);
187
188/**
189 * Finds a named bootmem block by name.
190 *
191 * @name: name of block to free
192 *
193 * Returns pointer to named block descriptor on success
194 * 0 on failure
195 */
196struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
197
198/**
199 * Allocates a block of physical memory from the free list, at
200 * (optional) requested address and alignment.
201 *
202 * @req_size: size of region to allocate. All requests are rounded up
203 * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
204 *
205 * @address_min: Minimum address that block can occupy.
206 *
207 * @address_max: Specifies the maximum address_min (inclusive) that
208 * the allocation can use.
209 *
210 * @alignment: Requested alignment of the block. If this alignment
211 * cannot be met, the allocation fails. This must be a
212 * power of 2. (Note: Alignment of
213 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
214 * internally enforced. Requested alignments of less than
215 * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
216 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
217 *
218 * @flags: Flags to control options for the allocation.
219 *
220 * Returns physical address of block allocated, or -1 on failure
221 */
222int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
223 uint64_t address_max, uint64_t alignment,
224 uint32_t flags);
225
226/**
227 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table.
229 *
230 * @name: Name of memory block to find. If NULL pointer given, then
231 * finds unused descriptor, if available.
232 *
233 * @flags: Flags to control options for the allocation.
234 *
235 * Returns Pointer to memory block descriptor, NULL if not found.
236 * If NULL returned when name parameter is NULL, then no memory
237 * block descriptors are available.
238 */
239struct cvmx_bootmem_named_block_desc *
240cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
241
242/**
243 * Frees a named block.
244 *
245 * @name: name of block to free
246 * @flags: flags for passing options
247 *
248 * Returns 0 on failure
249 * 1 on success
250 */
251int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
252
253/**
254 * Frees a block to the bootmem allocator list. This must
255 * be used with care, as the size provided must match the size
256 * of the block that was allocated, or the list will become
257 * corrupted.
258 *
259 * IMPORTANT: This is only intended to be used as part of named block
260 * frees and initial population of the free memory list.
261 * *
262 *
263 * @phy_addr: physical address of block
264 * @size: size of block in bytes.
265 * @flags: flags for passing options
266 *
267 * Returns 1 on success,
268 * 0 on failure
269 */
270int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
271
272/**
273 * Locks the bootmem allocator. This is useful in certain situations
274 * where multiple allocations must be made without being interrupted.
275 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
276 *
277 */
278void cvmx_bootmem_lock(void);
279
280/**
281 * Unlocks the bootmem allocator. This is useful in certain situations
282 * where multiple allocations must be made without being interrupted.
283 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
284 *
285 */
286void cvmx_bootmem_unlock(void);
287
288#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
new file mode 100644
index 000000000000..2a8c0902ea50
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -0,0 +1,325 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
31 * facilities.
32 */
33
34#ifndef __CVMX_L2C_H__
35#define __CVMX_L2C_H__
36
37/* Deprecated macro, use function */
38#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
39
40/* Deprecated macro, use function */
41#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
42
43/* Deprecated macro, use function */
44#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
45
46#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
47#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
48
49/* Defines for index aliasing computations */
50#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
51 (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
52
53#define CVMX_L2C_ALIAS_MASK \
54 (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
55
56union cvmx_l2c_tag {
57 uint64_t u64;
58 struct {
59 uint64_t reserved:28;
60 uint64_t V:1; /* Line valid */
61 uint64_t D:1; /* Line dirty */
62 uint64_t L:1; /* Line locked */
63 uint64_t U:1; /* Use, LRU eviction */
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 } s;
66};
67
68 /* L2C Performance Counter events. */
69enum cvmx_l2c_event {
70 CVMX_L2C_EVENT_CYCLES = 0,
71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
73 CVMX_L2C_EVENT_DATA_MISS = 3,
74 CVMX_L2C_EVENT_DATA_HIT = 4,
75 CVMX_L2C_EVENT_MISS = 5,
76 CVMX_L2C_EVENT_HIT = 6,
77 CVMX_L2C_EVENT_VICTIM_HIT = 7,
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
79 CVMX_L2C_EVENT_TAG_PROBE = 9,
80 CVMX_L2C_EVENT_TAG_UPDATE = 10,
81 CVMX_L2C_EVENT_TAG_COMPLETE = 11,
82 CVMX_L2C_EVENT_TAG_DIRTY = 12,
83 CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
84 CVMX_L2C_EVENT_DATA_STORE_READ = 14,
85 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
86 CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
87 CVMX_L2C_EVENT_WRITE_REQUEST = 17,
88 CVMX_L2C_EVENT_READ_REQUEST = 18,
89 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
90 CVMX_L2C_EVENT_XMC_NOP = 20,
91 CVMX_L2C_EVENT_XMC_LDT = 21,
92 CVMX_L2C_EVENT_XMC_LDI = 22,
93 CVMX_L2C_EVENT_XMC_LDD = 23,
94 CVMX_L2C_EVENT_XMC_STF = 24,
95 CVMX_L2C_EVENT_XMC_STT = 25,
96 CVMX_L2C_EVENT_XMC_STP = 26,
97 CVMX_L2C_EVENT_XMC_STC = 27,
98 CVMX_L2C_EVENT_XMC_DWB = 28,
99 CVMX_L2C_EVENT_XMC_PL2 = 29,
100 CVMX_L2C_EVENT_XMC_PSL1 = 30,
101 CVMX_L2C_EVENT_XMC_IOBLD = 31,
102 CVMX_L2C_EVENT_XMC_IOBST = 32,
103 CVMX_L2C_EVENT_XMC_IOBDMA = 33,
104 CVMX_L2C_EVENT_XMC_IOBRSP = 34,
105 CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
106 CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
107 CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
108 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
109 CVMX_L2C_EVENT_RSC_NOP = 39,
110 CVMX_L2C_EVENT_RSC_STDN = 40,
111 CVMX_L2C_EVENT_RSC_FILL = 41,
112 CVMX_L2C_EVENT_RSC_REFL = 42,
113 CVMX_L2C_EVENT_RSC_STIN = 43,
114 CVMX_L2C_EVENT_RSC_SCIN = 44,
115 CVMX_L2C_EVENT_RSC_SCFL = 45,
116 CVMX_L2C_EVENT_RSC_SCDN = 46,
117 CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
118 CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
119 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
120 CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
121 CVMX_L2C_EVENT_LRF_REQ = 51,
122 CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
123 CVMX_L2C_EVENT_DT_WR_INVAL = 53
124};
125
126/**
127 * Configure one of the four L2 Cache performance counters to capture event
128 * occurences.
129 *
130 * @counter: The counter to configure. Range 0..3.
131 * @event: The type of L2 Cache event occurrence to count.
132 * @clear_on_read: When asserted, any read of the performance counter
133 * clears the counter.
134 *
135 * The routine does not clear the counter.
136 */
137void cvmx_l2c_config_perf(uint32_t counter,
138 enum cvmx_l2c_event event, uint32_t clear_on_read);
139/**
140 * Read the given L2 Cache performance counter. The counter must be configured
141 * before reading, but this routine does not enforce this requirement.
142 *
143 * @counter: The counter to configure. Range 0..3.
144 *
145 * Returns The current counter value.
146 */
147uint64_t cvmx_l2c_read_perf(uint32_t counter);
148
149/**
150 * Return the L2 Cache way partitioning for a given core.
151 *
152 * @core: The core processor of interest.
153 *
154 * Returns The mask specifying the partitioning. 0 bits in mask indicates
155 * the cache 'ways' that a core can evict from.
156 * -1 on error
157 */
158int cvmx_l2c_get_core_way_partition(uint32_t core);
159
160/**
161 * Partitions the L2 cache for a core
162 *
163 * @core: The core that the partitioning applies to.
164 *
165 * @mask: The partitioning of the ways expressed as a binary mask. A 0
166 * bit allows the core to evict cache lines from a way, while a
167 * 1 bit blocks the core from evicting any lines from that
168 * way. There must be at least one allowed way (0 bit) in the
169 * mask.
170 *
171 * If any ways are blocked for all cores and the HW blocks, then those
172 * ways will never have any cache lines evicted from them. All cores
173 * and the hardware blocks are free to read from all ways regardless
174 * of the partitioning.
175 */
176int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
177
178/**
179 * Return the L2 Cache way partitioning for the hw blocks.
180 *
181 * Returns The mask specifying the reserved way. 0 bits in mask indicates
182 * the cache 'ways' that a core can evict from.
183 * -1 on error
184 */
185int cvmx_l2c_get_hw_way_partition(void);
186
187/**
188 * Partitions the L2 cache for the hardware blocks.
189 *
190 * @mask: The partitioning of the ways expressed as a binary mask. A 0
191 * bit allows the core to evict cache lines from a way, while a
192 * 1 bit blocks the core from evicting any lines from that
193 * way. There must be at least one allowed way (0 bit) in the
194 * mask.
195 *
196 * If any ways are blocked for all cores and the HW blocks, then those
197 * ways will never have any cache lines evicted from them. All cores
198 * and the hardware blocks are free to read from all ways regardless
199 * of the partitioning.
200 */
201int cvmx_l2c_set_hw_way_partition(uint32_t mask);
202
203/**
204 * Locks a line in the L2 cache at the specified physical address
205 *
206 * @addr: physical address of line to lock
207 *
208 * Returns 0 on success,
209 * 1 if line not locked.
210 */
211int cvmx_l2c_lock_line(uint64_t addr);
212
213/**
214 * Locks a specified memory region in the L2 cache.
215 *
216 * Note that if not all lines can be locked, that means that all
217 * but one of the ways (associations) available to the locking
218 * core are locked. Having only 1 association available for
219 * normal caching may have a significant adverse affect on performance.
220 * Care should be taken to ensure that enough of the L2 cache is left
221 * unlocked to allow for normal caching of DRAM.
222 *
223 * @start: Physical address of the start of the region to lock
224 * @len: Length (in bytes) of region to lock
225 *
226 * Returns Number of requested lines that where not locked.
227 * 0 on success (all locked)
228 */
229int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
230
231/**
232 * Unlock and flush a cache line from the L2 cache.
233 * IMPORTANT: Must only be run by one core at a time due to use
234 * of L2C debug features.
235 * Note that this function will flush a matching but unlocked cache line.
236 * (If address is not in L2, no lines are flushed.)
237 *
238 * @address: Physical address to unlock
239 *
240 * Returns 0: line not unlocked
241 * 1: line unlocked
242 */
243int cvmx_l2c_unlock_line(uint64_t address);
244
245/**
246 * Unlocks a region of memory that is locked in the L2 cache
247 *
248 * @start: start physical address
249 * @len: length (in bytes) to unlock
250 *
251 * Returns Number of locked lines that the call unlocked
252 */
253int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
254
255/**
256 * Read the L2 controller tag for a given location in L2
257 *
258 * @association:
259 * Which association to read line from
260 * @index: Which way to read from.
261 *
262 * Returns l2c tag structure for line requested.
263 */
264union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
265
266/* Wrapper around deprecated old function name */
267static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
268 uint32_t index)
269{
270 return cvmx_l2c_get_tag(association, index);
271}
272
273/**
274 * Returns the cache index for a given physical address
275 *
276 * @addr: physical address
277 *
278 * Returns L2 cache index
279 */
280uint32_t cvmx_l2c_address_to_index(uint64_t addr);
281
282/**
283 * Flushes (and unlocks) the entire L2 cache.
284 * IMPORTANT: Must only be run by one core at a time due to use
285 * of L2C debug features.
286 */
287void cvmx_l2c_flush(void);
288
289/**
290 *
291 * Returns Returns the size of the L2 cache in bytes,
292 * -1 on error (unrecognized model)
293 */
294int cvmx_l2c_get_cache_size_bytes(void);
295
296/**
297 * Return the number of sets in the L2 Cache
298 *
299 * Returns
300 */
301int cvmx_l2c_get_num_sets(void);
302
303/**
304 * Return log base 2 of the number of sets in the L2 cache
305 * Returns
306 */
307int cvmx_l2c_get_set_bits(void);
308/**
309 * Return the number of associations in the L2 Cache
310 *
311 * Returns
312 */
313int cvmx_l2c_get_num_assoc(void);
314
315/**
316 * Flush a line from the L2 cache
317 * This should only be called from one core at a time, as this routine
318 * sets the core to the 'debug' core in order to flush the line.
319 *
320 * @assoc: Association (or way) to flush
321 * @index: Index to flush
322 */
323void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
324
325#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
new file mode 100644
index 000000000000..38aefa1bab9d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Packet buffer defines.
30 */
31
32#ifndef __CVMX_PACKET_H__
33#define __CVMX_PACKET_H__
34
35/**
36 * This structure defines a buffer pointer on Octeon
37 */
38union cvmx_buf_ptr {
39 void *ptr;
40 uint64_t u64;
41 struct {
42 /* if set, invert the "free" pick of the overall
43 * packet. HW always sets this bit to 0 on inbound
44 * packet */
45 uint64_t i:1;
46
47 /* Indicates the amount to back up to get to the
48 * buffer start in cache lines. In most cases this is
49 * less than one complete cache line, so the value is
50 * zero */
51 uint64_t back:4;
52 /* The pool that the buffer came from / goes to */
53 uint64_t pool:3;
54 /* The size of the segment pointed to by addr (in bytes) */
55 uint64_t size:16;
56 /* Pointer to the first byte of the data, NOT buffer */
57 uint64_t addr:40;
58 } s;
59};
60
61#endif /* __CVMX_PACKET_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
new file mode 100644
index 000000000000..2fbf0871df11
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -0,0 +1,232 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Implementation of spinlocks for Octeon CVMX. Although similar in
30 * function to Linux kernel spinlocks, they are not compatible.
31 * Octeon CVMX spinlocks are only used to synchronize with the boot
32 * monitor and other non-Linux programs running in the system.
33 */
34
35#ifndef __CVMX_SPINLOCK_H__
36#define __CVMX_SPINLOCK_H__
37
38#include "cvmx-asm.h"
39
40/* Spinlocks for Octeon */
41
42/* define these to enable recursive spinlock debugging */
43/*#define CVMX_SPINLOCK_DEBUG */
44
45/**
46 * Spinlocks for Octeon CVMX
47 */
48typedef struct {
49 volatile uint32_t value;
50} cvmx_spinlock_t;
51
52/* note - macros not expanded in inline ASM, so values hardcoded */
53#define CVMX_SPINLOCK_UNLOCKED_VAL 0
54#define CVMX_SPINLOCK_LOCKED_VAL 1
55
56#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL}
57
58/**
59 * Initialize a spinlock
60 *
61 * @lock: Lock to initialize
62 */
63static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
64{
65 lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
66}
67
68/**
69 * Return non-zero if the spinlock is currently locked
70 *
71 * @lock: Lock to check
72 * Returns Non-zero if locked
73 */
74static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
75{
76 return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
77}
78
79/**
80 * Releases lock
81 *
82 * @lock: pointer to lock structure
83 */
84static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
85{
86 CVMX_SYNCWS;
87 lock->value = 0;
88 CVMX_SYNCWS;
89}
90
91/**
92 * Attempts to take the lock, but does not spin if lock is not available.
93 * May take some time to acquire the lock even if it is available
94 * due to the ll/sc not succeeding.
95 *
96 * @lock: pointer to lock structure
97 *
98 * Returns 0: lock successfully taken
99 * 1: lock not taken, held by someone else
100 * These return values match the Linux semantics.
101 */
102
103static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
104{
105 unsigned int tmp;
106
107 __asm__ __volatile__(".set noreorder \n"
108 "1: ll %[tmp], %[val] \n"
109 /* if lock held, fail immediately */
110 " bnez %[tmp], 2f \n"
111 " li %[tmp], 1 \n"
112 " sc %[tmp], %[val] \n"
113 " beqz %[tmp], 1b \n"
114 " li %[tmp], 0 \n"
115 "2: \n"
116 ".set reorder \n" :
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
118 : : "memory");
119
120 return tmp != 0; /* normalize to 0 or 1 */
121}
122
123/**
124 * Gets lock, spins until lock is taken
125 *
126 * @lock: pointer to lock structure
127 */
128static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
129{
130 unsigned int tmp;
131
132 __asm__ __volatile__(".set noreorder \n"
133 "1: ll %[tmp], %[val] \n"
134 " bnez %[tmp], 1b \n"
135 " li %[tmp], 1 \n"
136 " sc %[tmp], %[val] \n"
137 " beqz %[tmp], 1b \n"
138 " nop \n"
139 ".set reorder \n" :
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
141 : : "memory");
142
143}
144
145/** ********************************************************************
146 * Bit spinlocks
147 * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
148 * The rest of the bits in the word are left undisturbed. This enables more
149 * compact data structures as only 1 bit is consumed for the lock.
150 *
151 */
152
153/**
154 * Gets lock, spins until lock is taken
155 * Preserves the low 31 bits of the 32 bit
156 * word used for the lock.
157 *
158 *
159 * @word: word to lock bit 31 of
160 */
161static inline void cvmx_spinlock_bit_lock(uint32_t *word)
162{
163 unsigned int tmp;
164 unsigned int sav;
165
166 __asm__ __volatile__(".set noreorder \n"
167 ".set noat \n"
168 "1: ll %[tmp], %[val] \n"
169 " bbit1 %[tmp], 31, 1b \n"
170 " li $at, 1 \n"
171 " ins %[tmp], $at, 31, 1 \n"
172 " sc %[tmp], %[val] \n"
173 " beqz %[tmp], 1b \n"
174 " nop \n"
175 ".set at \n"
176 ".set reorder \n" :
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
178 : : "memory");
179
180}
181
182/**
183 * Attempts to get lock, returns immediately with success/failure
184 * Preserves the low 31 bits of the 32 bit
185 * word used for the lock.
186 *
187 *
188 * @word: word to lock bit 31 of
189 * Returns 0: lock successfully taken
190 * 1: lock not taken, held by someone else
191 * These return values match the Linux semantics.
192 */
193static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
194{
195 unsigned int tmp;
196
197 __asm__ __volatile__(".set noreorder\n\t"
198 ".set noat\n"
199 "1: ll %[tmp], %[val] \n"
200 /* if lock held, fail immediately */
201 " bbit1 %[tmp], 31, 2f \n"
202 " li $at, 1 \n"
203 " ins %[tmp], $at, 31, 1 \n"
204 " sc %[tmp], %[val] \n"
205 " beqz %[tmp], 1b \n"
206 " li %[tmp], 0 \n"
207 "2: \n"
208 ".set at \n"
209 ".set reorder \n" :
210 [val] "+m"(*word), [tmp] "=&r"(tmp)
211 : : "memory");
212
213 return tmp != 0; /* normalize to 0 or 1 */
214}
215
216/**
217 * Releases bit lock
218 *
219 * Unconditionally clears bit 31 of the lock word. Note that this is
220 * done non-atomically, as this implementation assumes that the rest
221 * of the bits in the word are protected by the lock.
222 *
223 * @word: word to unlock bit 31 in
224 */
225static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
226{
227 CVMX_SYNCWS;
228 *word &= ~(1UL << 31);
229 CVMX_SYNCWS;
230}
231
232#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
new file mode 100644
index 000000000000..61dd5741afe4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -0,0 +1,152 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board information obtained by the bootloader.
30 */
31
32#ifndef __CVMX_SYSINFO_H__
33#define __CVMX_SYSINFO_H__
34
35#define OCTEON_SERIAL_LEN 20
36/**
37 * Structure describing application specific information.
38 * __cvmx_app_init() populates this from the cvmx boot descriptor.
39 * This structure is private to simple executive applications, so
40 * no versioning is required.
41 *
42 * This structure must be provided with some fields set in order to
43 * use simple executive functions in other applications (Linux kernel,
44 * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is
45 * provided to set the required values in these cases.
46 */
47struct cvmx_sysinfo {
48 /* System wide variables */
49 /* installed DRAM in system, in bytes */
50 uint64_t system_dram_size;
51
52 /* ptr to memory descriptor block */
53 void *phy_mem_desc_ptr;
54
55
56 /* Application image specific variables */
57 /* stack top address (virtual) */
58 uint64_t stack_top;
59 /* heap base address (virtual) */
60 uint64_t heap_base;
61 /* stack size in bytes */
62 uint32_t stack_size;
63 /* heap size in bytes */
64 uint32_t heap_size;
65 /* coremask defining cores running application */
66 uint32_t core_mask;
67 /* Deprecated, use cvmx_coremask_first_core() to select init core */
68 uint32_t init_core;
69
70 /* exception base address, as set by bootloader */
71 uint64_t exception_base_addr;
72
73 /* cpu clock speed in hz */
74 uint32_t cpu_clock_hz;
75
76 /* dram data rate in hz (data rate = 2 * clock rate */
77 uint32_t dram_data_rate_hz;
78
79
80 uint16_t board_type;
81 uint8_t board_rev_major;
82 uint8_t board_rev_minor;
83 uint8_t mac_addr_base[6];
84 uint8_t mac_addr_count;
85 char board_serial_number[OCTEON_SERIAL_LEN];
86 /*
87 * Several boards support compact flash on the Octeon boot
88 * bus. The CF memory spaces may be mapped to different
89 * addresses on different boards. These values will be 0 if
90 * CF is not present. Note that these addresses are physical
91 * addresses, and it is up to the application to use the
92 * proper addressing mode (XKPHYS, KSEG0, etc.)
93 */
94 uint64_t compact_flash_common_base_addr;
95 uint64_t compact_flash_attribute_base_addr;
96 /*
97 * Base address of the LED display (as on EBT3000 board) This
98 * will be 0 if LED display not present. Note that this
99 * address is a physical address, and it is up to the
100 * application to use the proper addressing mode (XKPHYS,
101 * KSEG0, etc.)
102 */
103 uint64_t led_display_base_addr;
104 /* DFA reference clock in hz (if applicable)*/
105 uint32_t dfa_ref_clock_hz;
106 /* configuration flags from bootloader */
107 uint32_t bootloader_config_flags;
108
109 /* Uart number used for console */
110 uint8_t console_uart_num;
111};
112
113/**
114 * This function returns the system/board information as obtained
115 * by the bootloader.
116 *
117 *
118 * Returns Pointer to the boot information structure
119 *
120 */
121
122extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
123
124/**
125 * This function is used in non-simple executive environments (such as
126 * Linux kernel, u-boot, etc.) to configure the minimal fields that
127 * are required to use simple executive files directly.
128 *
129 * Locking (if required) must be handled outside of this
130 * function
131 *
132 * @phy_mem_desc_ptr: Pointer to global physical memory descriptor
133 * (bootmem descriptor) @board_type: Octeon board
134 * type enumeration
135 *
136 * @board_rev_major:
137 * Board major revision
138 * @board_rev_minor:
139 * Board minor revision
140 * @cpu_clock_hz:
141 * CPU clock freqency in hertz
142 *
143 * Returns 0: Failure
144 * 1: success
145 */
146extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
147 uint16_t board_type,
148 uint8_t board_rev_major,
149 uint8_t board_rev_minor,
150 uint32_t cpu_clock_hz);
151
152#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
new file mode 100644
index 000000000000..03fddfa3e928
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -0,0 +1,505 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34#include "cvmx-asm.h"
35#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h"
37
38#include "cvmx-ciu-defs.h"
39#include "cvmx-gpio-defs.h"
40#include "cvmx-iob-defs.h"
41#include "cvmx-ipd-defs.h"
42#include "cvmx-l2c-defs.h"
43#include "cvmx-l2d-defs.h"
44#include "cvmx-l2t-defs.h"
45#include "cvmx-led-defs.h"
46#include "cvmx-mio-defs.h"
47#include "cvmx-pow-defs.h"
48
49#include "cvmx-bootinfo.h"
50#include "cvmx-bootmem.h"
51#include "cvmx-l2c.h"
52
53#ifndef CVMX_ENABLE_DEBUG_PRINTS
54#define CVMX_ENABLE_DEBUG_PRINTS 1
55#endif
56
57#if CVMX_ENABLE_DEBUG_PRINTS
58#define cvmx_dprintf printk
59#else
60#define cvmx_dprintf(...) {}
61#endif
62
63#define CVMX_MAX_CORES (16)
64#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
65#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
66#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
67#define CAST64(v) ((long long)(long)(v))
68#define CASTPTR(type, v) ((type *)(long)(v))
69
70/*
71 * Returns processor ID, different Linux and simple exec versions
72 * provided in the cvmx-app-init*.c files.
73 */
74static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
75static inline uint32_t cvmx_get_proc_id(void)
76{
77 uint32_t id;
78 asm("mfc0 %0, $15,0" : "=r"(id));
79 return id;
80}
81
82/* turn the variable name into a string */
83#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
84#define CVMX_TMP_STR2(x) #x
85
86/**
87 * Builds a bit mask given the required size in bits.
88 *
89 * @bits: Number of bits in the mask
90 * Returns The mask
91 */ static inline uint64_t cvmx_build_mask(uint64_t bits)
92{
93 return ~((~0x0ull) << bits);
94}
95
96/**
97 * Builds a memory address for I/O based on the Major and Sub DID.
98 *
99 * @major_did: 5 bit major did
100 * @sub_did: 3 bit sub did
101 * Returns I/O base address
102 */
103static inline uint64_t cvmx_build_io_address(uint64_t major_did,
104 uint64_t sub_did)
105{
106 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
107}
108
109/**
110 * Perform mask and shift to place the supplied value into
111 * the supplied bit rage.
112 *
113 * Example: cvmx_build_bits(39,24,value)
114 * <pre>
115 * 6 5 4 3 3 2 1
116 * 3 5 7 9 1 3 5 7 0
117 * +-------+-------+-------+-------+-------+-------+-------+------+
118 * 000000000000000000000000___________value000000000000000000000000
119 * </pre>
120 *
121 * @high_bit: Highest bit value can occupy (inclusive) 0-63
122 * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
123 * @value: Value to use
124 * Returns Value masked and shifted
125 */
126static inline uint64_t cvmx_build_bits(uint64_t high_bit,
127 uint64_t low_bit, uint64_t value)
128{
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130}
131
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/**
154 * Convert a memory pointer (void*) into a hardware compatable
155 * memory address (uint64_t). Octeon hardware widgets don't
156 * understand logical addresses.
157 *
158 * @ptr: C style memory pointer
159 * Returns Hardware physical address
160 */
161static inline uint64_t cvmx_ptr_to_phys(void *ptr)
162{
163 if (sizeof(void *) == 8) {
164 /*
165 * We're running in 64 bit mode. Normally this means
166 * that we can use 40 bits of address space (the
167 * hardware limit). Unfortunately there is one case
168 * were we need to limit this to 30 bits, sign
169 * extended 32 bit. Although these are 64 bits wide,
170 * only 30 bits can be used.
171 */
172 if ((CAST64(ptr) >> 62) == 3)
173 return CAST64(ptr) & cvmx_build_mask(30);
174 else
175 return CAST64(ptr) & cvmx_build_mask(40);
176 } else {
177 return (long)(ptr) & 0x1fffffff;
178 }
179}
180
181/**
182 * Convert a hardware physical address (uint64_t) into a
183 * memory pointer (void *).
184 *
185 * @physical_address:
186 * Hardware physical address to memory
187 * Returns Pointer to memory
188 */
189static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
190{
191 if (sizeof(void *) == 8) {
192 /* Just set the top bit, avoiding any TLB uglyness */
193 return CASTPTR(void,
194 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
195 physical_address));
196 } else {
197 return CASTPTR(void,
198 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
199 physical_address));
200 }
201}
202
203/* The following #if controls the definition of the macro
204 CVMX_BUILD_WRITE64. This macro is used to build a store operation to
205 a full 64bit address. With a 64bit ABI, this can be done with a simple
206 pointer access. 32bit ABIs require more complicated assembly */
207
208/* We have a full 64bit ABI. Writing to a 64bit address can be done with
209 a simple volatile pointer */
210#define CVMX_BUILD_WRITE64(TYPE, ST) \
211static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
212{ \
213 *CASTPTR(volatile TYPE##_t, addr) = val; \
214}
215
216
217/* The following #if controls the definition of the macro
218 CVMX_BUILD_READ64. This macro is used to build a load operation from
219 a full 64bit address. With a 64bit ABI, this can be done with a simple
220 pointer access. 32bit ABIs require more complicated assembly */
221
222/* We have a full 64bit ABI. Writing to a 64bit address can be done with
223 a simple volatile pointer */
224#define CVMX_BUILD_READ64(TYPE, LT) \
225static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
226{ \
227 return *CASTPTR(volatile TYPE##_t, addr); \
228}
229
230
231/* The following defines 8 functions for writing to a 64bit address. Each
232 takes two arguments, the address and the value to write.
233 cvmx_write64_int64 cvmx_write64_uint64
234 cvmx_write64_int32 cvmx_write64_uint32
235 cvmx_write64_int16 cvmx_write64_uint16
236 cvmx_write64_int8 cvmx_write64_uint8 */
237CVMX_BUILD_WRITE64(int64, "sd");
238CVMX_BUILD_WRITE64(int32, "sw");
239CVMX_BUILD_WRITE64(int16, "sh");
240CVMX_BUILD_WRITE64(int8, "sb");
241CVMX_BUILD_WRITE64(uint64, "sd");
242CVMX_BUILD_WRITE64(uint32, "sw");
243CVMX_BUILD_WRITE64(uint16, "sh");
244CVMX_BUILD_WRITE64(uint8, "sb");
245#define cvmx_write64 cvmx_write64_uint64
246
247/* The following defines 8 functions for reading from a 64bit address. Each
248 takes the address as the only argument
249 cvmx_read64_int64 cvmx_read64_uint64
250 cvmx_read64_int32 cvmx_read64_uint32
251 cvmx_read64_int16 cvmx_read64_uint16
252 cvmx_read64_int8 cvmx_read64_uint8 */
253CVMX_BUILD_READ64(int64, "ld");
254CVMX_BUILD_READ64(int32, "lw");
255CVMX_BUILD_READ64(int16, "lh");
256CVMX_BUILD_READ64(int8, "lb");
257CVMX_BUILD_READ64(uint64, "ld");
258CVMX_BUILD_READ64(uint32, "lw");
259CVMX_BUILD_READ64(uint16, "lhu");
260CVMX_BUILD_READ64(uint8, "lbu");
261#define cvmx_read64 cvmx_read64_uint64
262
263
264static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
265{
266 cvmx_write64(csr_addr, val);
267
268 /*
269 * Perform an immediate read after every write to an RSL
270 * register to force the write to complete. It doesn't matter
271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
272 * because it is fast and harmless.
273 */
274 if ((csr_addr >> 40) == (0x800118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276}
277
278static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
279{
280 cvmx_write64(io_addr, val);
281
282}
283
284static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
285{
286 uint64_t val = cvmx_read64(csr_addr);
287 return val;
288}
289
290
291static inline void cvmx_send_single(uint64_t data)
292{
293 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
294 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
295}
296
297static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
298{
299 union {
300 uint64_t u64;
301 struct {
302 uint64_t scraddr:8;
303 uint64_t len:8;
304 uint64_t addr:48;
305 } s;
306 } addr;
307 addr.u64 = csr_addr;
308 addr.s.scraddr = scraddr >> 3;
309 addr.s.len = 1;
310 cvmx_send_single(addr.u64);
311}
312
313/* Return true if Octeon is CN38XX pass 1 */
314static inline int cvmx_octeon_is_pass1(void)
315{
316#if OCTEON_IS_COMMON_BINARY()
317 return 0; /* Pass 1 isn't supported for common binaries */
318#else
319/* Now that we know we're built for a specific model, only check CN38XX */
320#if OCTEON_IS_MODEL(OCTEON_CN38XX)
321 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
322#else
323 return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
324#endif
325#endif
326}
327
328static inline unsigned int cvmx_get_core_num(void)
329{
330 unsigned int core_num;
331 CVMX_RDHWRNV(core_num, 0);
332 return core_num;
333}
334
335/**
336 * Returns the number of bits set in the provided value.
337 * Simple wrapper for POP instruction.
338 *
339 * @val: 32 bit value to count set bits in
340 *
341 * Returns Number of bits set
342 */
343static inline uint32_t cvmx_pop(uint32_t val)
344{
345 uint32_t pop;
346 CVMX_POP(pop, val);
347 return pop;
348}
349
350/**
351 * Returns the number of bits set in the provided value.
352 * Simple wrapper for DPOP instruction.
353 *
354 * @val: 64 bit value to count set bits in
355 *
356 * Returns Number of bits set
357 */
358static inline int cvmx_dpop(uint64_t val)
359{
360 int pop;
361 CVMX_DPOP(pop, val);
362 return pop;
363}
364
365/**
366 * Provide current cycle counter as a return value
367 *
368 * Returns current cycle counter
369 */
370
371static inline uint64_t cvmx_get_cycle(void)
372{
373 uint64_t cycle;
374 CVMX_RDHWR(cycle, 31);
375 return cycle;
376}
377
378/**
379 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion
382 *
383 * Returns Global chip cycle count since chip reset.
384 */
385static inline uint64_t cvmx_get_cycle_global(void)
386{
387 if (cvmx_octeon_is_pass1())
388 return 0;
389 else
390 return cvmx_read64(CVMX_IPD_CLK_COUNT);
391}
392
393/**
394 * This macro spins on a field waiting for it to reach a value. It
395 * is common in code to need to wait for a specific field in a CSR
396 * to match a specific value. Conceptually this macro expands to:
397 *
398 * 1) read csr at "address" with a csr typedef of "type"
399 * 2) Check if ("type".s."field" "op" "value")
400 * 3) If #2 isn't true loop to #1 unless too much time has passed.
401 */
402#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
403 ( \
404{ \
405 int result; \
406 do { \
407 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
408 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
409 type c; \
410 while (1) { \
411 c.u64 = cvmx_read_csr(address); \
412 if ((c.s.field) op(value)) { \
413 result = 0; \
414 break; \
415 } else if (cvmx_get_cycle() > done) { \
416 result = -1; \
417 break; \
418 } else \
419 cvmx_wait(100); \
420 } \
421 } while (0); \
422 result; \
423})
424
425/***************************************************************************/
426
427static inline void cvmx_reset_octeon(void)
428{
429 union cvmx_ciu_soft_rst ciu_soft_rst;
430 ciu_soft_rst.u64 = 0;
431 ciu_soft_rst.s.soft_rst = 1;
432 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
433}
434
435/* Return the number of cores available in the chip */
436static inline uint32_t cvmx_octeon_num_cores(void)
437{
438 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
439 return cvmx_pop(ciu_fuse);
440}
441
442/**
443 * Read a byte of fuse data
444 * @byte_addr: address to read
445 *
446 * Returns fuse value: 0 or 1
447 */
448static uint8_t cvmx_fuse_read_byte(int byte_addr)
449{
450 union cvmx_mio_fus_rcmd read_cmd;
451
452 read_cmd.u64 = 0;
453 read_cmd.s.addr = byte_addr;
454 read_cmd.s.pend = 1;
455 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
456 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
457 && read_cmd.s.pend)
458 ;
459 return read_cmd.s.dat;
460}
461
462/**
463 * Read a single fuse bit
464 *
465 * @fuse: Fuse number (0-1024)
466 *
467 * Returns fuse value: 0 or 1
468 */
469static inline int cvmx_fuse_read(int fuse)
470{
471 return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
472}
473
474static inline int cvmx_octeon_model_CN36XX(void)
475{
476 return OCTEON_IS_MODEL(OCTEON_CN38XX)
477 && !cvmx_octeon_is_pass1()
478 && cvmx_fuse_read(264);
479}
480
481static inline int cvmx_octeon_zip_present(void)
482{
483 return octeon_has_feature(OCTEON_FEATURE_ZIP);
484}
485
486static inline int cvmx_octeon_dfa_present(void)
487{
488 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
489 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
490 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
491 return 0;
492 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
493 return 0;
494 else if (cvmx_octeon_is_pass1())
495 return 1;
496 else
497 return !cvmx_fuse_read(120);
498}
499
500static inline int cvmx_octeon_crypto_present(void)
501{
502 return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
503}
504
505#endif /* __CVMX_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
new file mode 100644
index 000000000000..04fac684069c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -0,0 +1,119 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining checks for different Octeon features.
30 */
31
32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__
34
35enum octeon_feature {
36 /*
37 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad).
39 */
40 OCTEON_FEATURE_SAAD,
41 /* Does this Octeon support the ZIP offload engine? */
42 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO,
45 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE,
47 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY,
50 /* Octeon has a LED controller for banks of external LEDs */
51 OCTEON_FEATURE_LED_CONTROLLER,
52 /* Octeon has a trace buffer */
53 OCTEON_FEATURE_TRA,
54 /* Octeon has a management port */
55 OCTEON_FEATURE_MGMT_PORT,
56 /* Octeon has a raid unit */
57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB,
60};
61
62static inline int cvmx_fuse_read(int fuse);
63
64/**
65 * Determine if the current Octeon supports a specific feature. These
66 * checks have been optimized to be fairly quick, but they should still
67 * be kept out of fast path code.
68 *
69 * @feature: Feature to check for. This should always be a constant so the
70 * compiler can remove the switch statement through optimization.
71 *
72 * Returns Non zero if the feature exists. Zero if the feature does not
73 * exist.
74 */
75static inline int octeon_has_feature(enum octeon_feature feature)
76{
77 switch (feature) {
78 case OCTEON_FEATURE_SAAD:
79 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
80
81 case OCTEON_FEATURE_ZIP:
82 if (OCTEON_IS_MODEL(OCTEON_CN30XX)
83 || OCTEON_IS_MODEL(OCTEON_CN50XX)
84 || OCTEON_IS_MODEL(OCTEON_CN52XX))
85 return 0;
86 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
87 return 1;
88 else
89 return !cvmx_fuse_read(121);
90
91 case OCTEON_FEATURE_CRYPTO:
92 return !cvmx_fuse_read(90);
93
94 case OCTEON_FEATURE_PCIE:
95 return OCTEON_IS_MODEL(OCTEON_CN56XX)
96 || OCTEON_IS_MODEL(OCTEON_CN52XX);
97
98 case OCTEON_FEATURE_KEY_MEMORY:
99 case OCTEON_FEATURE_LED_CONTROLLER:
100 return OCTEON_IS_MODEL(OCTEON_CN38XX)
101 || OCTEON_IS_MODEL(OCTEON_CN58XX)
102 || OCTEON_IS_MODEL(OCTEON_CN56XX);
103 case OCTEON_FEATURE_TRA:
104 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
105 || OCTEON_IS_MODEL(OCTEON_CN50XX));
106 case OCTEON_FEATURE_MGMT_PORT:
107 return OCTEON_IS_MODEL(OCTEON_CN56XX)
108 || OCTEON_IS_MODEL(OCTEON_CN52XX);
109 case OCTEON_FEATURE_RAID:
110 return OCTEON_IS_MODEL(OCTEON_CN56XX)
111 || OCTEON_IS_MODEL(OCTEON_CN52XX);
112 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX));
115 }
116 return 0;
117}
118
119#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
new file mode 100644
index 000000000000..cf50336eca2e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -0,0 +1,321 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__
37
38/* NOTE: These must match what is checked in common-config.mk */
39/* Defines to represent the different versions of Octeon. */
40
41/*
42 * IMPORTANT: When the default pass is updated for an Octeon Model,
43 * the corresponding change must also be made in the oct-sim script.
44 */
45
46/*
47 * The defines below should be used with the OCTEON_IS_MODEL() macro
48 * to determine what model of chip the software is running on. Models
49 * ending in 'XX' match multiple models (families), while specific
50 * models match only that model. If a pass (revision) is specified,
51 * then only that revision will be matched. Care should be taken when
52 * checking for both specific models and families that the specific
53 * models are checked for first. While these defines are similar to
54 * the processor ID, they are not intended to be used by anything
55 * other that the OCTEON_IS_MODEL framework, and the values are
56 * subject to change at anytime without notice.
57 *
58 * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
59 * macros should be used outside of this file. All other macros are
60 * for internal use only, and may change without notice.
61 */
62
63/* Flag bits in top byte */
64/* Ignores revision in model checks */
65#define OM_IGNORE_REVISION 0x01000000
66/* Check submodels */
67#define OM_CHECK_SUBMODEL 0x02000000
68/* Match all models previous than the one specified */
69#define OM_MATCH_PREVIOUS_MODELS 0x04000000
70/* Ignores the minor revison on newer parts */
71#define OM_IGNORE_MINOR_REVISION 0x08000000
72#define OM_FLAG_MASK 0xff000000
73
74/*
75 * CN5XXX models with new revision encoding
76 */
77#define OCTEON_CN58XX_PASS1_0 0x000d0300
78#define OCTEON_CN58XX_PASS1_1 0x000d0301
79#define OCTEON_CN58XX_PASS1_2 0x000d0303
80#define OCTEON_CN58XX_PASS2_0 0x000d0308
81#define OCTEON_CN58XX_PASS2_1 0x000d0309
82#define OCTEON_CN58XX_PASS2_2 0x000d030a
83#define OCTEON_CN58XX_PASS2_3 0x000d030b
84
85#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
86#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \
87 | OM_IGNORE_MINOR_REVISION)
88#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
89 | OM_IGNORE_MINOR_REVISION)
90#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
91#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
92
93#define OCTEON_CN56XX_PASS1_0 0x000d0400
94#define OCTEON_CN56XX_PASS1_1 0x000d0401
95#define OCTEON_CN56XX_PASS2_0 0x000d0408
96#define OCTEON_CN56XX_PASS2_1 0x000d0409
97
98#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
99#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \
100 | OM_IGNORE_MINOR_REVISION)
101#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
102 | OM_IGNORE_MINOR_REVISION)
103#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
104#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
105
106#define OCTEON_CN57XX OCTEON_CN56XX
107#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1
108#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2
109
110#define OCTEON_CN55XX OCTEON_CN56XX
111#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1
112#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2
113
114#define OCTEON_CN54XX OCTEON_CN56XX
115#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1
116#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2
117
118#define OCTEON_CN50XX_PASS1_0 0x000d0600
119
120#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
121#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \
122 | OM_IGNORE_MINOR_REVISION)
123#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
124
125/*
126 * NOTE: Octeon CN5000F model is not identifiable using the
127 * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
128 */
129
130#define OCTEON_CN52XX_PASS1_0 0x000d0700
131#define OCTEON_CN52XX_PASS2_0 0x000d0708
132
133#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
134#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \
135 | OM_IGNORE_MINOR_REVISION)
136#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
137 | OM_IGNORE_MINOR_REVISION)
138#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
139#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
140
141/*
142 * CN3XXX models with old revision enconding
143 */
144#define OCTEON_CN38XX_PASS1 0x000d0000
145#define OCTEON_CN38XX_PASS2 0x000d0001
146#define OCTEON_CN38XX_PASS3 0x000d0003
147#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
148
149#define OCTEON_CN36XX OCTEON_CN38XX
150#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2
151#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3
152
153/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
154#define OCTEON_CN31XX_PASS1 0x000d0100
155#define OCTEON_CN31XX_PASS1_1 0x000d0102
156#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
157
158/*
159 * This model is only used for internal checks, it is not a valid
160 * model for the OCTEON_MODEL environment variable. This matches the
161 * CN3010 and CN3005 but NOT the CN3020.
162 */
163#define OCTEON_CN30XX_PASS1 0x000d0200
164#define OCTEON_CN30XX_PASS1_1 0x000d0202
165#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
166
167#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
168#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
169#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
170#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
171 | OM_CHECK_SUBMODEL)
172
173#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
174#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
177 | OM_CHECK_SUBMODEL)
178
179#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
180#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
183 | OM_CHECK_SUBMODEL)
184
185
186
187/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
188#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
189 | OM_MATCH_PREVIOUS_MODELS \
190 | OM_IGNORE_REVISION)
191
192/* The revision byte (low byte) has two different encodings.
193 * CN3XXX:
194 *
195 * bits
196 * <7:5>: reserved (0)
197 * <4>: alternate package
198 * <3:0>: revision
199 *
200 * CN5XXX:
201 *
202 * bits
203 * <7>: reserved (0)
204 * <6>: alternate package
205 * <5:3>: major revision
206 * <2:0>: minor revision
207 *
208 */
209
210/* Masks used for the various types of model/family/revision matching */
211#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
212#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
213#define OCTEON_38XX_MODEL_MASK 0x00ffff10
214#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
215 | OCTEON_38XX_MODEL_MASK)
216
217/* CN5XXX and later use different layout of bits in the revision ID field */
218#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
219#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
220#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
221#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
222 | OCTEON_58XX_MODEL_MASK)
223#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
224 & 0x00fffff8)
225
226#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
227
228/* NOTE: This is for internal (to this file) use only. */
229static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
230 uint32_t chip_model)
231{
232 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
233
234 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
235 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
236 __OCTEON_MATCH_MASK__(chip_model, arg_model,
237 OCTEON_38XX_MODEL_MASK))
238 return 1;
239 if (((arg_model & OM_FLAG_MASK) == 0) &&
240 __OCTEON_MATCH_MASK__(chip_model, arg_model,
241 OCTEON_38XX_FAMILY_REV_MASK))
242 return 1;
243 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
244 __OCTEON_MATCH_MASK__(chip_model, arg_model,
245 OCTEON_38XX_FAMILY_MASK))
246 return 1;
247 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
248 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
249 OCTEON_38XX_MODEL_REV_MASK))
250 return 1;
251 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
252 ((chip_model & OCTEON_38XX_MODEL_MASK) <
253 (arg_model & OCTEON_38XX_MODEL_MASK)))
254 return 1;
255 } else {
256 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
257 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
258 OCTEON_58XX_MODEL_MASK))
259 return 1;
260 if (((arg_model & OM_FLAG_MASK) == 0) &&
261 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
262 OCTEON_58XX_FAMILY_REV_MASK))
263 return 1;
264 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
265 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
266 OCTEON_58XX_MODEL_MINOR_REV_MASK))
267 return 1;
268 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
269 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
270 OCTEON_58XX_FAMILY_MASK))
271 return 1;
272 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
273 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
274 OCTEON_58XX_MODEL_REV_MASK))
275 return 1;
276 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
277 ((chip_model & OCTEON_58XX_MODEL_MASK) <
278 (arg_model & OCTEON_58XX_MODEL_MASK)))
279 return 1;
280 }
281 return 0;
282}
283
284/* forward declarations */
285static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
286static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
287
288/* NOTE: This for internal use only!!!!! */
289static inline int __octeon_is_model_runtime__(uint32_t model)
290{
291 uint32_t cpuid = cvmx_get_proc_id();
292
293 /*
294 * Check for special case of mismarked 3005 samples. We only
295 * need to check if the sub model isn't being ignored.
296 */
297 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
298 if (cpuid == OCTEON_CN3010_PASS1 \
299 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
300 cpuid |= 0x10;
301 }
302 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
303}
304
305/*
306 * The OCTEON_IS_MODEL macro should be used for all Octeon model
307 * checking done in a program. This should be kept runtime if at all
308 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
309 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
310 * support is required.
311 */
312#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
313#define OCTEON_IS_COMMON_BINARY() 1
314#undef OCTEON_MODEL
315
316const char *octeon_model_get_string(uint32_t chip_id);
317const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
318
319#include "octeon-feature.h"
320
321#endif /* __OCTEON_MODEL_H__ */
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