MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.

These are the rest of the new files needed to add OCTEON processor
support to the Linux kernel.  Other than Makefile and Kconfig which
should be obvious, we have:

csrc-octeon.c   -- Clock source driver for OCTEON.
dma-octeon.c    -- Helper functions for mapping DMA memory.
flash_setup.c   -- Register on-board flash with the MTD subsystem.
octeon-irq.c    -- OCTEON interrupt controller managment.
octeon-memcpy.S -- Optimized memcpy() implementation.
serial.c        -- Register 8250 platform driver and early console.
setup.c         -- Early architecture initialization.
smp.c           -- OCTEON SMP support.
octeon_switch.S -- Scheduler context switch for OCTEON.
c-octeon.c      -- OCTEON cache controller support.
cex-oct.S       -- OCTEON cache exception handler.

asm/mach-cavium-octeon/*.h -- Architecture include files.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/cavium-octeon/Kconfig
 create mode 100644 arch/mips/cavium-octeon/Makefile
 create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c
 create mode 100644 arch/mips/cavium-octeon/dma-octeon.c
 create mode 100644 arch/mips/cavium-octeon/flash_setup.c
 create mode 100644 arch/mips/cavium-octeon/octeon-irq.c
 create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S
 create mode 100644 arch/mips/cavium-octeon/serial.c
 create mode 100644 arch/mips/cavium-octeon/setup.c
 create mode 100644 arch/mips/cavium-octeon/smp.c
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
 create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
 create mode 100644 arch/mips/include/asm/octeon/octeon.h
 create mode 100644 arch/mips/kernel/octeon_switch.S
 create mode 100644 arch/mips/mm/c-octeon.c
 create mode 100644 arch/mips/mm/cex-oct.S

6 files changed, 791 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..04ce6e6569da
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,78 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Cavium Networks
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
+
+#include <linux/types.h>
+#include <asm/mipsregs.h>
+
+/*
+ * Cavium Octeons are MIPS64v2 processors
+ */
+#define cpu_dcache_line_size()  128
+#define cpu_icache_line_size()  128
+
+
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        0
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             0
+#define cpu_has_counter         1
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+
+/*
+ * We should disable LL/SC on non SMP systems as it is faster to
+ * disable interrupts for atomic access than a LL/SC.  Unfortunatly we
+ * cannot as this breaks asm/futex.h
+ */
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_64bits          1
+#define cpu_has_octeon_cache    1
+#define cpu_has_saa             octeon_has_saa()
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        1
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_vint            0
+#define cpu_has_veic            0
+#define ARCH_HAS_READ_CURRENT_TIMER 1
+#define ARCH_HAS_IRQ_PER_CPU    1
+#define ARCH_HAS_SPINLOCK_PREFETCH 1
+#define spin_lock_prefetch(x) prefetch(x)
+#define PREFETCH_STRIDE 128
+
+static inline int read_current_timer(unsigned long *result)
+{
+        asm volatile ("rdhwr %0,$31\n"
+#ifndef CONFIG_64BIT
+                      "\tsll %0, 0"
+#endif
+                      : "=r" (*result));
+        return 0;
+}
+
+static inline int octeon_has_saa(void)
+{
+        int id;
+        asm volatile ("mfc0 %0, $15,0" : "=r" (id));
+        return id >= 0x000d0300;
+}
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
new file mode 100644
index 000000000000..f30fce92aabb
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
+ *
+ *
+ * Similar to mach-generic/dma-coherence.h except
+ * plat_device_is_coherent hard coded to return 1.
+ *
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
+#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
+
+struct device;
+
+dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
+void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+        size_t size)
+{
+        return octeon_map_dma_mem(dev, addr, size);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
+{
+        return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+{
+        return dma_addr;
+}
+
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+{
+        octeon_unmap_dma_mem(dev, dma_addr);
+}
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+        return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+        mb();
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+        return 1;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+                                         dma_addr_t dma_addr)
+{
+        return dma_addr == -1;
+}
+
+#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 000000000000..d32220fbf4f1
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,244 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#ifndef __OCTEON_IRQ_H__
+#define __OCTEON_IRQ_H__
+
+#define NR_IRQS OCTEON_IRQ_LAST
+#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
+
+/* 0 - 7 represent the i8259 master */
+#define OCTEON_IRQ_I8259M0      0
+#define OCTEON_IRQ_I8259M1      1
+#define OCTEON_IRQ_I8259M2      2
+#define OCTEON_IRQ_I8259M3      3
+#define OCTEON_IRQ_I8259M4      4
+#define OCTEON_IRQ_I8259M5      5
+#define OCTEON_IRQ_I8259M6      6
+#define OCTEON_IRQ_I8259M7      7
+/* 8 - 15 represent the i8259 slave */
+#define OCTEON_IRQ_I8259S0      8
+#define OCTEON_IRQ_I8259S1      9
+#define OCTEON_IRQ_I8259S2      10
+#define OCTEON_IRQ_I8259S3      11
+#define OCTEON_IRQ_I8259S4      12
+#define OCTEON_IRQ_I8259S5      13
+#define OCTEON_IRQ_I8259S6      14
+#define OCTEON_IRQ_I8259S7      15
+/* 16 - 23 represent the 8 MIPS standard interrupt sources */
+#define OCTEON_IRQ_SW0          16
+#define OCTEON_IRQ_SW1          17
+#define OCTEON_IRQ_CIU0         18
+#define OCTEON_IRQ_CIU1         19
+#define OCTEON_IRQ_CIU4         20
+#define OCTEON_IRQ_5            21
+#define OCTEON_IRQ_PERF         22
+#define OCTEON_IRQ_TIMER        23
+/* 24 - 87 represent the sources in CIU_INTX_EN0 */
+#define OCTEON_IRQ_WORKQ0       24
+#define OCTEON_IRQ_WORKQ1       25
+#define OCTEON_IRQ_WORKQ2       26
+#define OCTEON_IRQ_WORKQ3       27
+#define OCTEON_IRQ_WORKQ4       28
+#define OCTEON_IRQ_WORKQ5       29
+#define OCTEON_IRQ_WORKQ6       30
+#define OCTEON_IRQ_WORKQ7       31
+#define OCTEON_IRQ_WORKQ8       32
+#define OCTEON_IRQ_WORKQ9       33
+#define OCTEON_IRQ_WORKQ10      34
+#define OCTEON_IRQ_WORKQ11      35
+#define OCTEON_IRQ_WORKQ12      36
+#define OCTEON_IRQ_WORKQ13      37
+#define OCTEON_IRQ_WORKQ14      38
+#define OCTEON_IRQ_WORKQ15      39
+#define OCTEON_IRQ_GPIO0        40
+#define OCTEON_IRQ_GPIO1        41
+#define OCTEON_IRQ_GPIO2        42
+#define OCTEON_IRQ_GPIO3        43
+#define OCTEON_IRQ_GPIO4        44
+#define OCTEON_IRQ_GPIO5        45
+#define OCTEON_IRQ_GPIO6        46
+#define OCTEON_IRQ_GPIO7        47
+#define OCTEON_IRQ_GPIO8        48
+#define OCTEON_IRQ_GPIO9        49
+#define OCTEON_IRQ_GPIO10       50
+#define OCTEON_IRQ_GPIO11       51
+#define OCTEON_IRQ_GPIO12       52
+#define OCTEON_IRQ_GPIO13       53
+#define OCTEON_IRQ_GPIO14       54
+#define OCTEON_IRQ_GPIO15       55
+#define OCTEON_IRQ_MBOX0        56
+#define OCTEON_IRQ_MBOX1        57
+#define OCTEON_IRQ_UART0        58
+#define OCTEON_IRQ_UART1        59
+#define OCTEON_IRQ_PCI_INT0     60
+#define OCTEON_IRQ_PCI_INT1     61
+#define OCTEON_IRQ_PCI_INT2     62
+#define OCTEON_IRQ_PCI_INT3     63
+#define OCTEON_IRQ_PCI_MSI0     64
+#define OCTEON_IRQ_PCI_MSI1     65
+#define OCTEON_IRQ_PCI_MSI2     66
+#define OCTEON_IRQ_PCI_MSI3     67
+#define OCTEON_IRQ_RESERVED68   68      /* Summary of CIU_INT_SUM1 */
+#define OCTEON_IRQ_TWSI         69
+#define OCTEON_IRQ_RML          70
+#define OCTEON_IRQ_TRACE        71
+#define OCTEON_IRQ_GMX_DRP0     72
+#define OCTEON_IRQ_GMX_DRP1     73
+#define OCTEON_IRQ_IPD_DRP      74
+#define OCTEON_IRQ_KEY_ZERO     75
+#define OCTEON_IRQ_TIMER0       76
+#define OCTEON_IRQ_TIMER1       77
+#define OCTEON_IRQ_TIMER2       78
+#define OCTEON_IRQ_TIMER3       79
+#define OCTEON_IRQ_USB0         80
+#define OCTEON_IRQ_PCM          81
+#define OCTEON_IRQ_MPI          82
+#define OCTEON_IRQ_TWSI2        83
+#define OCTEON_IRQ_POWIQ        84
+#define OCTEON_IRQ_IPDPPTHR     85
+#define OCTEON_IRQ_MII0         86
+#define OCTEON_IRQ_BOOTDMA      87
+/* 88 - 151 represent the sources in CIU_INTX_EN1 */
+#define OCTEON_IRQ_WDOG0        88
+#define OCTEON_IRQ_WDOG1        89
+#define OCTEON_IRQ_WDOG2        90
+#define OCTEON_IRQ_WDOG3        91
+#define OCTEON_IRQ_WDOG4        92
+#define OCTEON_IRQ_WDOG5        93
+#define OCTEON_IRQ_WDOG6        94
+#define OCTEON_IRQ_WDOG7        95
+#define OCTEON_IRQ_WDOG8        96
+#define OCTEON_IRQ_WDOG9        97
+#define OCTEON_IRQ_WDOG10       98
+#define OCTEON_IRQ_WDOG11       99
+#define OCTEON_IRQ_WDOG12       100
+#define OCTEON_IRQ_WDOG13       101
+#define OCTEON_IRQ_WDOG14       102
+#define OCTEON_IRQ_WDOG15       103
+#define OCTEON_IRQ_UART2        104
+#define OCTEON_IRQ_USB1         105
+#define OCTEON_IRQ_MII1         106
+#define OCTEON_IRQ_RESERVED107  107
+#define OCTEON_IRQ_RESERVED108  108
+#define OCTEON_IRQ_RESERVED109  109
+#define OCTEON_IRQ_RESERVED110  110
+#define OCTEON_IRQ_RESERVED111  111
+#define OCTEON_IRQ_RESERVED112  112
+#define OCTEON_IRQ_RESERVED113  113
+#define OCTEON_IRQ_RESERVED114  114
+#define OCTEON_IRQ_RESERVED115  115
+#define OCTEON_IRQ_RESERVED116  116
+#define OCTEON_IRQ_RESERVED117  117
+#define OCTEON_IRQ_RESERVED118  118
+#define OCTEON_IRQ_RESERVED119  119
+#define OCTEON_IRQ_RESERVED120  120
+#define OCTEON_IRQ_RESERVED121  121
+#define OCTEON_IRQ_RESERVED122  122
+#define OCTEON_IRQ_RESERVED123  123
+#define OCTEON_IRQ_RESERVED124  124
+#define OCTEON_IRQ_RESERVED125  125
+#define OCTEON_IRQ_RESERVED126  126
+#define OCTEON_IRQ_RESERVED127  127
+#define OCTEON_IRQ_RESERVED128  128
+#define OCTEON_IRQ_RESERVED129  129
+#define OCTEON_IRQ_RESERVED130  130
+#define OCTEON_IRQ_RESERVED131  131
+#define OCTEON_IRQ_RESERVED132  132
+#define OCTEON_IRQ_RESERVED133  133
+#define OCTEON_IRQ_RESERVED134  134
+#define OCTEON_IRQ_RESERVED135  135
+#define OCTEON_IRQ_RESERVED136  136
+#define OCTEON_IRQ_RESERVED137  137
+#define OCTEON_IRQ_RESERVED138  138
+#define OCTEON_IRQ_RESERVED139  139
+#define OCTEON_IRQ_RESERVED140  140
+#define OCTEON_IRQ_RESERVED141  141
+#define OCTEON_IRQ_RESERVED142  142
+#define OCTEON_IRQ_RESERVED143  143
+#define OCTEON_IRQ_RESERVED144  144
+#define OCTEON_IRQ_RESERVED145  145
+#define OCTEON_IRQ_RESERVED146  146
+#define OCTEON_IRQ_RESERVED147  147
+#define OCTEON_IRQ_RESERVED148  148
+#define OCTEON_IRQ_RESERVED149  149
+#define OCTEON_IRQ_RESERVED150  150
+#define OCTEON_IRQ_RESERVED151  151
+
+#ifdef CONFIG_PCI_MSI
+/* 152 - 215 represent the MSI interrupts 0-63 */
+#define OCTEON_IRQ_MSI_BIT0     152
+#define OCTEON_IRQ_MSI_BIT1     153
+#define OCTEON_IRQ_MSI_BIT2     154
+#define OCTEON_IRQ_MSI_BIT3     155
+#define OCTEON_IRQ_MSI_BIT4     156
+#define OCTEON_IRQ_MSI_BIT5     157
+#define OCTEON_IRQ_MSI_BIT6     158
+#define OCTEON_IRQ_MSI_BIT7     159
+#define OCTEON_IRQ_MSI_BIT8     160
+#define OCTEON_IRQ_MSI_BIT9     161
+#define OCTEON_IRQ_MSI_BIT10    162
+#define OCTEON_IRQ_MSI_BIT11    163
+#define OCTEON_IRQ_MSI_BIT12    164
+#define OCTEON_IRQ_MSI_BIT13    165
+#define OCTEON_IRQ_MSI_BIT14    166
+#define OCTEON_IRQ_MSI_BIT15    167
+#define OCTEON_IRQ_MSI_BIT16    168
+#define OCTEON_IRQ_MSI_BIT17    169
+#define OCTEON_IRQ_MSI_BIT18    170
+#define OCTEON_IRQ_MSI_BIT19    171
+#define OCTEON_IRQ_MSI_BIT20    172
+#define OCTEON_IRQ_MSI_BIT21    173
+#define OCTEON_IRQ_MSI_BIT22    174
+#define OCTEON_IRQ_MSI_BIT23    175
+#define OCTEON_IRQ_MSI_BIT24    176
+#define OCTEON_IRQ_MSI_BIT25    177
+#define OCTEON_IRQ_MSI_BIT26    178
+#define OCTEON_IRQ_MSI_BIT27    179
+#define OCTEON_IRQ_MSI_BIT28    180
+#define OCTEON_IRQ_MSI_BIT29    181
+#define OCTEON_IRQ_MSI_BIT30    182
+#define OCTEON_IRQ_MSI_BIT31    183
+#define OCTEON_IRQ_MSI_BIT32    184
+#define OCTEON_IRQ_MSI_BIT33    185
+#define OCTEON_IRQ_MSI_BIT34    186
+#define OCTEON_IRQ_MSI_BIT35    187
+#define OCTEON_IRQ_MSI_BIT36    188
+#define OCTEON_IRQ_MSI_BIT37    189
+#define OCTEON_IRQ_MSI_BIT38    190
+#define OCTEON_IRQ_MSI_BIT39    191
+#define OCTEON_IRQ_MSI_BIT40    192
+#define OCTEON_IRQ_MSI_BIT41    193
+#define OCTEON_IRQ_MSI_BIT42    194
+#define OCTEON_IRQ_MSI_BIT43    195
+#define OCTEON_IRQ_MSI_BIT44    196
+#define OCTEON_IRQ_MSI_BIT45    197
+#define OCTEON_IRQ_MSI_BIT46    198
+#define OCTEON_IRQ_MSI_BIT47    199
+#define OCTEON_IRQ_MSI_BIT48    200
+#define OCTEON_IRQ_MSI_BIT49    201
+#define OCTEON_IRQ_MSI_BIT50    202
+#define OCTEON_IRQ_MSI_BIT51    203
+#define OCTEON_IRQ_MSI_BIT52    204
+#define OCTEON_IRQ_MSI_BIT53    205
+#define OCTEON_IRQ_MSI_BIT54    206
+#define OCTEON_IRQ_MSI_BIT55    207
+#define OCTEON_IRQ_MSI_BIT56    208
+#define OCTEON_IRQ_MSI_BIT57    209
+#define OCTEON_IRQ_MSI_BIT58    210
+#define OCTEON_IRQ_MSI_BIT59    211
+#define OCTEON_IRQ_MSI_BIT60    212
+#define OCTEON_IRQ_MSI_BIT61    213
+#define OCTEON_IRQ_MSI_BIT62    214
+#define OCTEON_IRQ_MSI_BIT63    215
+
+#define OCTEON_IRQ_LAST         216
+#else
+#define OCTEON_IRQ_LAST         152
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 000000000000..0b2b5eb22e9b
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,131 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2008 Cavium Networks, Inc
+ */
+#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
+
+
+#define CP0_CYCLE_COUNTER $9, 6
+#define CP0_CVMCTL_REG $9, 7
+#define CP0_CVMMEMCTL_REG $11,7
+#define CP0_PRID_REG $15, 0
+#define CP0_PRID_OCTEON_PASS1 0x000d0000
+#define CP0_PRID_OCTEON_CN30XX 0x000d0200
+
+.macro  kernel_entry_setup
+        # Registers set by bootloader:
+        # (only 32 bits set by bootloader, all addresses are physical
+        # addresses, and need to have the appropriate memory region set
+        # by the kernel
+        # a0 = argc
+        # a1 = argv (kseg0 compat addr)
+        # a2 = 1 if init core, zero otherwise
+        # a3 = address of boot descriptor block
+        .set push
+        .set arch=octeon
+        # Read the cavium mem control register
+        dmfc0   v0, CP0_CVMMEMCTL_REG
+        # Clear the lower 6 bits, the CVMSEG size
+        dins    v0, $0, 0, 6
+        ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+        dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
+        dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
+#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
+        # Disable unaligned load/store support but leave HW fixup enabled
+        or  v0, v0, 0x5001
+        xor v0, v0, 0x1001
+#else
+        # Disable unaligned load/store and HW fixup support
+        or  v0, v0, 0x5001
+        xor v0, v0, 0x5001
+#endif
+        # Read the processor ID register
+        mfc0 v1, CP0_PRID_REG
+        # Disable instruction prefetching (Octeon Pass1 errata)
+        or  v0, v0, 0x2000
+        # Skip reenable of prefetching for Octeon Pass1
+        beq v1, CP0_PRID_OCTEON_PASS1, skip
+        nop
+        # Reenable instruction prefetching, not on Pass1
+        xor v0, v0, 0x2000
+        # Strip off pass number off of processor id
+        srl v1, 8
+        sll v1, 8
+        # CN30XX needs some extra stuff turned off for better performance
+        bne v1, CP0_PRID_OCTEON_CN30XX, skip
+        nop
+        # CN30XX Use random Icache replacement
+        or  v0, v0, 0x400
+        # CN30XX Disable instruction prefetching
+        or  v0, v0, 0x2000
+skip:
+        # Write the cavium control register
+        dmtc0   v0, CP0_CVMCTL_REG
+        sync
+        # Flush dcache after config change
+        cache   9, 0($0)
+        # Get my core id
+        rdhwr   v0, $0
+        # Jump the master to kernel_entry
+        bne     a2, zero, octeon_main_processor
+        nop
+
+#ifdef CONFIG_SMP
+
+        #
+        # All cores other than the master need to wait here for SMP bootstrap
+        # to begin
+        #
+
+        # This is the variable where the next core to boot os stored
+        PTR_LA  t0, octeon_processor_boot
+octeon_spin_wait_boot:
+        # Get the core id of the next to be booted
+        LONG_L  t1, (t0)
+        # Keep looping if it isn't me
+        bne t1, v0, octeon_spin_wait_boot
+        nop
+        # Get my GP from the global variable
+        PTR_LA  t0, octeon_processor_gp
+        LONG_L  gp, (t0)
+        # Get my SP from the global variable
+        PTR_LA  t0, octeon_processor_sp
+        LONG_L  sp, (t0)
+        # Set the SP global variable to zero so the master knows we've started
+        LONG_S  zero, (t0)
+#ifdef __OCTEON__
+        syncw
+        syncw
+#else
+        sync
+#endif
+        # Jump to the normal Linux SMP entry point
+        j   smp_bootstrap
+        nop
+#else /* CONFIG_SMP */
+
+        #
+        # Someone tried to boot SMP with a non SMP kernel. All extra cores
+        # will halt here.
+        #
+octeon_wait_forever:
+        wait
+        b   octeon_wait_forever
+        nop
+
+#endif /* CONFIG_SMP */
+octeon_main_processor:
+        .set pop
+.endm
+
+/*
+ * Do SMP slave processor setup necessary before we can savely execute C code.
+ */
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
new file mode 100644
index 000000000000..c4712d7cc81d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
+ */
+#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
new file mode 100644
index 000000000000..edc676084cda
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -0,0 +1,248 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2008 Cavium Networks
+ */
+#ifndef __ASM_OCTEON_OCTEON_H
+#define __ASM_OCTEON_OCTEON_H
+
+#include "cvmx.h"
+
+extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
+                                                uint64_t alignment,
+                                                uint64_t min_addr,
+                                                uint64_t max_addr,
+                                                int do_locking);
+extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
+                                  int do_locking);
+extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
+                                        uint64_t min_addr, uint64_t max_addr,
+                                        int do_locking);
+extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+                                        char *name);
+extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                              uint64_t max_addr, uint64_t align,
+                                              char *name);
+extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+                                                char *name);
+extern int octeon_bootmem_free_named(char *name);
+extern void octeon_bootmem_lock(void);
+extern void octeon_bootmem_unlock(void);
+
+extern int octeon_is_simulation(void);
+extern int octeon_is_pci_host(void);
+extern int octeon_usb_is_ref_clk(void);
+extern uint64_t octeon_get_clock_rate(void);
+extern const char *octeon_board_type_string(void);
+extern const char *octeon_get_pci_interrupts(void);
+extern int octeon_get_southbridge_interrupt(void);
+extern int octeon_get_boot_coremask(void);
+extern int octeon_get_boot_num_arguments(void);
+extern const char *octeon_get_boot_argument(int arg);
+extern void octeon_hal_setup_reserved32(void);
+extern void octeon_user_io_init(void);
+struct octeon_cop2_state;
+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
+extern void octeon_crypto_disable(struct octeon_cop2_state *state,
+                                  unsigned long flags);
+
+extern void octeon_init_cvmcount(void);
+
+#define OCTEON_ARGV_MAX_ARGS    64
+#define OCTOEN_SERIAL_LEN       20
+
+struct octeon_boot_descriptor {
+        /* Start of block referenced by assembly code - do not change! */
+        uint32_t desc_version;
+        uint32_t desc_size;
+        uint64_t stack_top;
+        uint64_t heap_base;
+        uint64_t heap_end;
+        /* Only used by bootloader */
+        uint64_t entry_point;
+        uint64_t desc_vaddr;
+        /* End of This block referenced by assembly code - do not change! */
+        uint32_t exception_base_addr;
+        uint32_t stack_size;
+        uint32_t heap_size;
+        /* Argc count for application. */
+        uint32_t argc;
+        uint32_t argv[OCTEON_ARGV_MAX_ARGS];
+
+#define  BOOT_FLAG_INIT_CORE            (1 << 0)
+#define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
+#define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
+        /* If set, use uart1 for console */
+#define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
+        /* If set, use PCI console */
+#define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
+        /* Call exit on break on serial port */
+#define  OCTEON_BL_FLAG_BREAK           (1 << 5)
+
+        uint32_t flags;
+        uint32_t core_mask;
+        /* DRAM size in megabyes. */
+        uint32_t dram_size;
+        /* physical address of free memory descriptor block. */
+        uint32_t phy_mem_desc_addr;
+        /* used to pass flags from app to debugger. */
+        uint32_t debugger_flags_base_addr;
+        /* CPU clock speed, in hz. */
+        uint32_t eclock_hz;
+        /* DRAM clock speed, in hz. */
+        uint32_t dclock_hz;
+        /* SPI4 clock in hz. */
+        uint32_t spi_clock_hz;
+        uint16_t board_type;
+        uint8_t board_rev_major;
+        uint8_t board_rev_minor;
+        uint16_t chip_type;
+        uint8_t chip_rev_major;
+        uint8_t chip_rev_minor;
+        char board_serial_number[OCTOEN_SERIAL_LEN];
+        uint8_t mac_addr_base[6];
+        uint8_t mac_addr_count;
+        uint64_t cvmx_desc_vaddr;
+};
+
+union octeon_cvmemctl {
+        uint64_t u64;
+        struct {
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t tlbbist:1;
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t l1cbist:1;
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t l1dbist:1;
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t dcmbist:1;
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t ptgbist:1;
+                /* RO 1 = BIST fail, 0 = BIST pass */
+                uint64_t wbfbist:1;
+                /* Reserved */
+                uint64_t reserved:22;
+                /* R/W If set, marked write-buffer entries time out
+                 * the same as as other entries; if clear, marked
+                 * write-buffer entries use the maximum timeout. */
+                uint64_t dismarkwblongto:1;
+                /* R/W If set, a merged store does not clear the
+                 * write-buffer entry timeout state. */
+                uint64_t dismrgclrwbto:1;
+                /* R/W Two bits that are the MSBs of the resultant
+                 * CVMSEG LM word location for an IOBDMA. The other 8
+                 * bits come from the SCRADDR field of the IOBDMA. */
+                uint64_t iobdmascrmsb:2;
+                /* R/W If set, SYNCWS and SYNCS only order marked
+                 * stores; if clear, SYNCWS and SYNCS only order
+                 * unmarked stores. SYNCWSMARKED has no effect when
+                 * DISSYNCWS is set. */
+                uint64_t syncwsmarked:1;
+                /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
+                 * SYNC. */
+                uint64_t dissyncws:1;
+                /* R/W If set, no stall happens on write buffer
+                 * full. */
+                uint64_t diswbfst:1;
+                /* R/W If set (and SX set), supervisor-level
+                 * loads/stores can use XKPHYS addresses with
+                 * VA<48>==0 */
+                uint64_t xkmemenas:1;
+                /* R/W If set (and UX set), user-level loads/stores
+                 * can use XKPHYS addresses with VA<48>==0 */
+                uint64_t xkmemenau:1;
+                /* R/W If set (and SX set), supervisor-level
+                 * loads/stores can use XKPHYS addresses with
+                 * VA<48>==1 */
+                uint64_t xkioenas:1;
+                /* R/W If set (and UX set), user-level loads/stores
+                 * can use XKPHYS addresses with VA<48>==1 */
+                uint64_t xkioenau:1;
+                /* R/W If set, all stores act as SYNCW (NOMERGE must
+                 * be set when this is set) RW, reset to 0. */
+                uint64_t allsyncw:1;
+                /* R/W If set, no stores merge, and all stores reach
+                 * the coherent bus in order. */
+                uint64_t nomerge:1;
+                /* R/W Selects the bit in the counter used for DID
+                 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
+                 * 214. Actual time-out is between 1x and 2x this
+                 * interval. For example, with DIDTTO=3, expiration
+                 * interval is between 16K and 32K. */
+                uint64_t didtto:2;
+                /* R/W If set, the (mem) CSR clock never turns off. */
+                uint64_t csrckalwys:1;
+                /* R/W If set, mclk never turns off. */
+                uint64_t mclkalwys:1;
+                /* R/W Selects the bit in the counter used for write
+                 * buffer flush time-outs (WBFLT+11) is the bit
+                 * position in an internal counter used to determine
+                 * expiration. The write buffer expires between 1x and
+                 * 2x this interval. For example, with WBFLT = 0, a
+                 * write buffer expires between 2K and 4K cycles after
+                 * the write buffer entry is allocated. */
+                uint64_t wbfltime:3;
+                /* R/W If set, do not put Istream in the L2 cache. */
+                uint64_t istrnol2:1;
+                /* R/W The write buffer threshold. */
+                uint64_t wbthresh:4;
+                /* Reserved */
+                uint64_t reserved2:2;
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * kernel/debug mode. */
+                uint64_t cvmsegenak:1;
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * supervisor mode. */
+                uint64_t cvmsegenas:1;
+                /* R/W If set, CVMSEG is available for loads/stores in
+                 * user mode. */
+                uint64_t cvmsegenau:1;
+                /* R/W Size of local memory in cache blocks, 54 (6912
+                 * bytes) is max legal value. */
+                uint64_t lmemsz:6;
+        } s;
+};
+
+struct octeon_cf_data {
+        unsigned long   base_region_bias;
+        unsigned int    base_region;    /* The chip select region used by CF */
+        int             is16bit;        /* 0 - 8bit, !0 - 16bit */
+        int             dma_engine;     /* -1 for no DMA */
+};
+
+extern void octeon_write_lcd(const char *s);
+extern void octeon_check_cpu_bist(void);
+extern int octeon_get_boot_debug_flag(void);
+extern int octeon_get_boot_uart(void);
+
+struct uart_port;
+extern unsigned int octeon_serial_in(struct uart_port *, int);
+extern void octeon_serial_out(struct uart_port *, int, int);
+
+/**
+ * Write a 32bit value to the Octeon NPI register space
+ *
+ * @address: Address to write to
+ * @val:     Value to write
+ */
+static inline void octeon_npi_write32(uint64_t address, uint32_t val)
+{
+        cvmx_write64_uint32(address ^ 4, val);
+        cvmx_read64_uint32(address ^ 4);
+}
+
+
+/**
+ * Read a 32bit value from the Octeon NPI register space
+ *
+ * @address: Address to read
+ * Returns The result
+ */
+static inline uint32_t octeon_npi_read32(uint64_t address)
+{
+        return cvmx_read64_uint32(address ^ 4);
+}
+
+#endif /* __ASM_OCTEON_OCTEON_H */