MIPS: math-emu: Add mfhc1 & mthc1 support.

This patch adds support for the mfhc1 & mthc1 instructions to the FPU
emulator. These instructions were introduced in release 2 of the MIPS32
& MIPS64 architectures and allow access to the most significant 32 bits
of a 64-bit FP register.

[ralf@linux-mips.org: Fix ifdef hell added by original patch.]

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6112/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index e5a676e3d3c0..0ee96563e6f0 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -98,8 +98,9 @@ enum rt_op {
  */
 enum cop_op {
         mfc_op        = 0x00, dmfc_op       = 0x01,
-        cfc_op        = 0x02, mtc_op        = 0x04,
-        dmtc_op       = 0x05, ctc_op        = 0x06,
+        cfc_op        = 0x02, mfhc_op       = 0x03,
+        mtc_op        = 0x04, dmtc_op       = 0x05,
+        ctc_op        = 0x06, mthc_op       = 0x07,
         bc_op         = 0x08, cop_op        = 0x10,
         copm_op       = 0x18
 };