diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-05-09 11:57:30 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-05-09 11:57:30 -0400 |
commit | b22d1b6a91ca4260f869e349179ae53f18c664db (patch) | |
tree | 6ac6c2bd202100727638f02ae5037ec78144e8d5 /arch/mips/include/asm | |
parent | 5e0e61dd2c89c673f89fb57dcd3cc746dc0c1706 (diff) | |
parent | 0ab2b7d08ea7226dc72ff0f8c05f470566facf7c (diff) |
Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r-- | arch/mips/include/asm/asm.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/branch.h | 40 | ||||
-rw-r--r-- | arch/mips/include/asm/dma-coherence.h | 15 | ||||
-rw-r--r-- | arch/mips/include/asm/dma-mapping.h | 1 | ||||
-rw-r--r-- | arch/mips/include/asm/fpu_emulator.h | 6 | ||||
-rw-r--r-- | arch/mips/include/asm/fw/fw.h | 47 | ||||
-rw-r--r-- | arch/mips/include/asm/gic.h | 16 | ||||
-rw-r--r-- | arch/mips/include/asm/inst.h | 12 | ||||
-rw-r--r-- | arch/mips/include/asm/kvm_host.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-generic/dma-coherence.h | 5 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h | 4 | ||||
-rw-r--r-- | arch/mips/include/asm/mips-boards/generic.h | 3 | ||||
-rw-r--r-- | arch/mips/include/asm/mips-boards/prom.h | 47 | ||||
-rw-r--r-- | arch/mips/include/asm/mipsregs.h | 19 | ||||
-rw-r--r-- | arch/mips/include/asm/mmu_context.h | 95 | ||||
-rw-r--r-- | arch/mips/include/asm/stackframe.h | 12 | ||||
-rw-r--r-- | arch/mips/include/asm/time.h | 8 | ||||
-rw-r--r-- | arch/mips/include/asm/uaccess.h | 14 | ||||
-rw-r--r-- | arch/mips/include/asm/uasm.h | 84 |
19 files changed, 297 insertions, 135 deletions
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 164a21e65b42..879691d194af 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h | |||
@@ -296,6 +296,7 @@ symbol = value | |||
296 | #define LONG_SUBU subu | 296 | #define LONG_SUBU subu |
297 | #define LONG_L lw | 297 | #define LONG_L lw |
298 | #define LONG_S sw | 298 | #define LONG_S sw |
299 | #define LONG_SP swp | ||
299 | #define LONG_SLL sll | 300 | #define LONG_SLL sll |
300 | #define LONG_SLLV sllv | 301 | #define LONG_SLLV sllv |
301 | #define LONG_SRL srl | 302 | #define LONG_SRL srl |
@@ -318,6 +319,7 @@ symbol = value | |||
318 | #define LONG_SUBU dsubu | 319 | #define LONG_SUBU dsubu |
319 | #define LONG_L ld | 320 | #define LONG_L ld |
320 | #define LONG_S sd | 321 | #define LONG_S sd |
322 | #define LONG_SP sdp | ||
321 | #define LONG_SLL dsll | 323 | #define LONG_SLL dsll |
322 | #define LONG_SLLV dsllv | 324 | #define LONG_SLLV dsllv |
323 | #define LONG_SRL dsrl | 325 | #define LONG_SRL dsrl |
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h index 888766ae1f85..e28a3e0eb3cb 100644 --- a/arch/mips/include/asm/branch.h +++ b/arch/mips/include/asm/branch.h | |||
@@ -11,6 +11,14 @@ | |||
11 | #include <asm/ptrace.h> | 11 | #include <asm/ptrace.h> |
12 | #include <asm/inst.h> | 12 | #include <asm/inst.h> |
13 | 13 | ||
14 | extern int __isa_exception_epc(struct pt_regs *regs); | ||
15 | extern int __compute_return_epc(struct pt_regs *regs); | ||
16 | extern int __compute_return_epc_for_insn(struct pt_regs *regs, | ||
17 | union mips_instruction insn); | ||
18 | extern int __microMIPS_compute_return_epc(struct pt_regs *regs); | ||
19 | extern int __MIPS16e_compute_return_epc(struct pt_regs *regs); | ||
20 | |||
21 | |||
14 | static inline int delay_slot(struct pt_regs *regs) | 22 | static inline int delay_slot(struct pt_regs *regs) |
15 | { | 23 | { |
16 | return regs->cp0_cause & CAUSEF_BD; | 24 | return regs->cp0_cause & CAUSEF_BD; |
@@ -18,20 +26,27 @@ static inline int delay_slot(struct pt_regs *regs) | |||
18 | 26 | ||
19 | static inline unsigned long exception_epc(struct pt_regs *regs) | 27 | static inline unsigned long exception_epc(struct pt_regs *regs) |
20 | { | 28 | { |
21 | if (!delay_slot(regs)) | 29 | if (likely(!delay_slot(regs))) |
22 | return regs->cp0_epc; | 30 | return regs->cp0_epc; |
23 | 31 | ||
32 | if (get_isa16_mode(regs->cp0_epc)) | ||
33 | return __isa_exception_epc(regs); | ||
34 | |||
24 | return regs->cp0_epc + 4; | 35 | return regs->cp0_epc + 4; |
25 | } | 36 | } |
26 | 37 | ||
27 | #define BRANCH_LIKELY_TAKEN 0x0001 | 38 | #define BRANCH_LIKELY_TAKEN 0x0001 |
28 | 39 | ||
29 | extern int __compute_return_epc(struct pt_regs *regs); | ||
30 | extern int __compute_return_epc_for_insn(struct pt_regs *regs, | ||
31 | union mips_instruction insn); | ||
32 | |||
33 | static inline int compute_return_epc(struct pt_regs *regs) | 40 | static inline int compute_return_epc(struct pt_regs *regs) |
34 | { | 41 | { |
42 | if (get_isa16_mode(regs->cp0_epc)) { | ||
43 | if (cpu_has_mmips) | ||
44 | return __microMIPS_compute_return_epc(regs); | ||
45 | if (cpu_has_mips16) | ||
46 | return __MIPS16e_compute_return_epc(regs); | ||
47 | return regs->cp0_epc; | ||
48 | } | ||
49 | |||
35 | if (!delay_slot(regs)) { | 50 | if (!delay_slot(regs)) { |
36 | regs->cp0_epc += 4; | 51 | regs->cp0_epc += 4; |
37 | return 0; | 52 | return 0; |
@@ -40,4 +55,19 @@ static inline int compute_return_epc(struct pt_regs *regs) | |||
40 | return __compute_return_epc(regs); | 55 | return __compute_return_epc(regs); |
41 | } | 56 | } |
42 | 57 | ||
58 | static inline int MIPS16e_compute_return_epc(struct pt_regs *regs, | ||
59 | union mips16e_instruction *inst) | ||
60 | { | ||
61 | if (likely(!delay_slot(regs))) { | ||
62 | if (inst->ri.opcode == MIPS16e_extend_op) { | ||
63 | regs->cp0_epc += 4; | ||
64 | return 0; | ||
65 | } | ||
66 | regs->cp0_epc += 2; | ||
67 | return 0; | ||
68 | } | ||
69 | |||
70 | return __MIPS16e_compute_return_epc(regs); | ||
71 | } | ||
72 | |||
43 | #endif /* _ASM_BRANCH_H */ | 73 | #endif /* _ASM_BRANCH_H */ |
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h new file mode 100644 index 000000000000..242cbb3ca582 --- /dev/null +++ b/arch/mips/include/asm/dma-coherence.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
7 | * | ||
8 | */ | ||
9 | #ifndef __ASM_DMA_COHERENCE_H | ||
10 | #define __ASM_DMA_COHERENCE_H | ||
11 | |||
12 | extern int coherentio; | ||
13 | extern int hw_coherentio; | ||
14 | |||
15 | #endif | ||
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index f8fc74b6cb47..84238c574d5e 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h | |||
@@ -2,6 +2,7 @@ | |||
2 | #define _ASM_DMA_MAPPING_H | 2 | #define _ASM_DMA_MAPPING_H |
3 | 3 | ||
4 | #include <asm/scatterlist.h> | 4 | #include <asm/scatterlist.h> |
5 | #include <asm/dma-coherence.h> | ||
5 | #include <asm/cache.h> | 6 | #include <asm/cache.h> |
6 | #include <asm-generic/dma-coherent.h> | 7 | #include <asm-generic/dma-coherent.h> |
7 | 8 | ||
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 3b4092705567..2abb587d5ab4 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h | |||
@@ -54,6 +54,12 @@ do { \ | |||
54 | extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, | 54 | extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, |
55 | unsigned long cpc); | 55 | unsigned long cpc); |
56 | extern int do_dsemulret(struct pt_regs *xcp); | 56 | extern int do_dsemulret(struct pt_regs *xcp); |
57 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, | ||
58 | struct mips_fpu_struct *ctx, int has_fpu, | ||
59 | void *__user *fault_addr); | ||
60 | int process_fpemu_return(int sig, void __user *fault_addr); | ||
61 | int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, | ||
62 | unsigned long *contpc); | ||
57 | 63 | ||
58 | /* | 64 | /* |
59 | * Instruction inserted following the badinst to further tag the sequence | 65 | * Instruction inserted following the badinst to further tag the sequence |
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h new file mode 100644 index 000000000000..d6c50a7e9ede --- /dev/null +++ b/arch/mips/include/asm/fw/fw.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2012 MIPS Technologies, Inc. | ||
7 | */ | ||
8 | #ifndef __ASM_FW_H_ | ||
9 | #define __ASM_FW_H_ | ||
10 | |||
11 | #include <asm/bootinfo.h> /* For cleaner code... */ | ||
12 | |||
13 | enum fw_memtypes { | ||
14 | fw_dontuse, | ||
15 | fw_code, | ||
16 | fw_free, | ||
17 | }; | ||
18 | |||
19 | typedef struct { | ||
20 | unsigned long base; /* Within KSEG0 */ | ||
21 | unsigned int size; /* bytes */ | ||
22 | enum fw_memtypes type; /* fw_memtypes */ | ||
23 | } fw_memblock_t; | ||
24 | |||
25 | /* Maximum number of memory block descriptors. */ | ||
26 | #define FW_MAX_MEMBLOCKS 32 | ||
27 | |||
28 | extern int fw_argc; | ||
29 | extern int *_fw_argv; | ||
30 | extern int *_fw_envp; | ||
31 | |||
32 | /* | ||
33 | * Most firmware like YAMON, PMON, etc. pass arguments and environment | ||
34 | * variables as 32-bit pointers. These take care of sign extension. | ||
35 | */ | ||
36 | #define fw_argv(index) ((char *)(long)_fw_argv[(index)]) | ||
37 | #define fw_envp(index) ((char *)(long)_fw_envp[(index)]) | ||
38 | |||
39 | extern void fw_init_cmdline(void); | ||
40 | extern char *fw_getcmdline(void); | ||
41 | extern fw_memblock_t *fw_getmdesc(void); | ||
42 | extern void fw_meminit(void); | ||
43 | extern char *fw_getenv(char *name); | ||
44 | extern unsigned long fw_getenvl(char *name); | ||
45 | extern void fw_init_early_console(char port); | ||
46 | |||
47 | #endif /* __ASM_FW_H_ */ | ||
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index bdc9786ab5a7..7153b32de18e 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h | |||
@@ -202,7 +202,7 @@ | |||
202 | #define GIC_VPE_WD_COUNT0_OFS 0x0094 | 202 | #define GIC_VPE_WD_COUNT0_OFS 0x0094 |
203 | #define GIC_VPE_WD_INITIAL0_OFS 0x0098 | 203 | #define GIC_VPE_WD_INITIAL0_OFS 0x0098 |
204 | #define GIC_VPE_COMPARE_LO_OFS 0x00a0 | 204 | #define GIC_VPE_COMPARE_LO_OFS 0x00a0 |
205 | #define GIC_VPE_COMPARE_HI 0x00a4 | 205 | #define GIC_VPE_COMPARE_HI_OFS 0x00a4 |
206 | 206 | ||
207 | #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 | 207 | #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 |
208 | #define GIC_VPE_EIC_SS(intr) \ | 208 | #define GIC_VPE_EIC_SS(intr) \ |
@@ -359,7 +359,11 @@ struct gic_shared_intr_map { | |||
359 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ | 359 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ |
360 | #define GIC_PIN_TO_VEC_OFFSET (1) | 360 | #define GIC_PIN_TO_VEC_OFFSET (1) |
361 | 361 | ||
362 | extern int gic_present; | 362 | #include <linux/clocksource.h> |
363 | #include <linux/irq.h> | ||
364 | |||
365 | extern unsigned int gic_present; | ||
366 | extern unsigned int gic_frequency; | ||
363 | extern unsigned long _gic_base; | 367 | extern unsigned long _gic_base; |
364 | extern unsigned int gic_irq_base; | 368 | extern unsigned int gic_irq_base; |
365 | extern unsigned int gic_irq_flags[]; | 369 | extern unsigned int gic_irq_flags[]; |
@@ -368,18 +372,20 @@ extern struct gic_shared_intr_map gic_shared_intr_map[]; | |||
368 | extern void gic_init(unsigned long gic_base_addr, | 372 | extern void gic_init(unsigned long gic_base_addr, |
369 | unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, | 373 | unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, |
370 | unsigned int intrmap_size, unsigned int irqbase); | 374 | unsigned int intrmap_size, unsigned int irqbase); |
371 | |||
372 | extern void gic_clocksource_init(unsigned int); | 375 | extern void gic_clocksource_init(unsigned int); |
373 | extern unsigned int gic_get_int(void); | 376 | extern unsigned int gic_compare_int (void); |
377 | extern cycle_t gic_read_count(void); | ||
378 | extern cycle_t gic_read_compare(void); | ||
379 | extern void gic_write_compare(cycle_t cnt); | ||
374 | extern void gic_send_ipi(unsigned int intr); | 380 | extern void gic_send_ipi(unsigned int intr); |
375 | extern unsigned int plat_ipi_call_int_xlate(unsigned int); | 381 | extern unsigned int plat_ipi_call_int_xlate(unsigned int); |
376 | extern unsigned int plat_ipi_resched_int_xlate(unsigned int); | 382 | extern unsigned int plat_ipi_resched_int_xlate(unsigned int); |
377 | extern void gic_bind_eic_interrupt(int irq, int set); | 383 | extern void gic_bind_eic_interrupt(int irq, int set); |
378 | extern unsigned int gic_get_timer_pending(void); | 384 | extern unsigned int gic_get_timer_pending(void); |
385 | extern unsigned int gic_get_int(void); | ||
379 | extern void gic_enable_interrupt(int irq_vec); | 386 | extern void gic_enable_interrupt(int irq_vec); |
380 | extern void gic_disable_interrupt(int irq_vec); | 387 | extern void gic_disable_interrupt(int irq_vec); |
381 | extern void gic_irq_ack(struct irq_data *d); | 388 | extern void gic_irq_ack(struct irq_data *d); |
382 | extern void gic_finish_irq(struct irq_data *d); | 389 | extern void gic_finish_irq(struct irq_data *d); |
383 | extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); | 390 | extern void gic_platform_init(int irqs, struct irq_chip *irq_controller); |
384 | |||
385 | #endif /* _ASM_GICREGS_H */ | 391 | #endif /* _ASM_GICREGS_H */ |
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index f1eadf764071..22912f78401c 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h | |||
@@ -73,4 +73,16 @@ | |||
73 | 73 | ||
74 | typedef unsigned int mips_instruction; | 74 | typedef unsigned int mips_instruction; |
75 | 75 | ||
76 | /* microMIPS instruction decode structure. Do NOT export!!! */ | ||
77 | struct mm_decoded_insn { | ||
78 | mips_instruction insn; | ||
79 | mips_instruction next_insn; | ||
80 | int pc_inc; | ||
81 | int next_pc_inc; | ||
82 | int micro_mips_mode; | ||
83 | }; | ||
84 | |||
85 | /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */ | ||
86 | extern const int reg16to32[]; | ||
87 | |||
76 | #endif /* _ASM_INST_H */ | 88 | #endif /* _ASM_INST_H */ |
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 143875c6c95a..e68781e18387 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h | |||
@@ -336,7 +336,7 @@ enum emulation_result { | |||
336 | #define VPN2_MASK 0xffffe000 | 336 | #define VPN2_MASK 0xffffe000 |
337 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G)) | 337 | #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G)) |
338 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) | 338 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) |
339 | #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK) | 339 | #define TLB_ASID(x) (ASID_MASK((x).tlb_hi)) |
340 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V)) | 340 | #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V)) |
341 | 341 | ||
342 | struct kvm_mips_tlb { | 342 | struct kvm_mips_tlb { |
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h index 9c95177f7a7e..fe23034aaf72 100644 --- a/arch/mips/include/asm/mach-generic/dma-coherence.h +++ b/arch/mips/include/asm/mach-generic/dma-coherence.h | |||
@@ -61,9 +61,8 @@ static inline int plat_device_is_coherent(struct device *dev) | |||
61 | { | 61 | { |
62 | #ifdef CONFIG_DMA_COHERENT | 62 | #ifdef CONFIG_DMA_COHERENT |
63 | return 1; | 63 | return 1; |
64 | #endif | 64 | #else |
65 | #ifdef CONFIG_DMA_NONCOHERENT | 65 | return coherentio; |
66 | return 0; | ||
67 | #endif | 66 | #endif |
68 | } | 67 | } |
69 | 68 | ||
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h index 193c0912d38e..bfbd7035d4c5 100644 --- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h | |||
@@ -28,7 +28,11 @@ | |||
28 | /* #define cpu_has_prefetch ? */ | 28 | /* #define cpu_has_prefetch ? */ |
29 | #define cpu_has_mcheck 1 | 29 | #define cpu_has_mcheck 1 |
30 | /* #define cpu_has_ejtag ? */ | 30 | /* #define cpu_has_ejtag ? */ |
31 | #ifdef CONFIG_CPU_MICROMIPS | ||
32 | #define cpu_has_llsc 0 | ||
33 | #else | ||
31 | #define cpu_has_llsc 1 | 34 | #define cpu_has_llsc 1 |
35 | #endif | ||
32 | /* #define cpu_has_vtag_icache ? */ | 36 | /* #define cpu_has_vtag_icache ? */ |
33 | /* #define cpu_has_dc_aliases ? */ | 37 | /* #define cpu_has_dc_aliases ? */ |
34 | /* #define cpu_has_ic_fills_f_dc ? */ | 38 | /* #define cpu_has_ic_fills_f_dc ? */ |
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 44a09a64160a..bd9746fbe4af 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h | |||
@@ -83,4 +83,7 @@ extern void mips_pcibios_init(void); | |||
83 | #define mips_pcibios_init() do { } while (0) | 83 | #define mips_pcibios_init() do { } while (0) |
84 | #endif | 84 | #endif |
85 | 85 | ||
86 | extern void mips_scroll_message(void); | ||
87 | extern void mips_display_message(const char *str); | ||
88 | |||
86 | #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ | 89 | #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ |
diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h deleted file mode 100644 index e7aed3e4ff58..000000000000 --- a/arch/mips/include/asm/mips-boards/prom.h +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * Carsten Langgaard, carstenl@mips.com | ||
3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | ||
4 | * | ||
5 | * ######################################################################## | ||
6 | * | ||
7 | * This program is free software; you can distribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License (Version 2) as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
14 | * for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
19 | * | ||
20 | * ######################################################################## | ||
21 | * | ||
22 | * MIPS boards bootprom interface for the Linux kernel. | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #ifndef _MIPS_PROM_H | ||
27 | #define _MIPS_PROM_H | ||
28 | |||
29 | extern char *prom_getcmdline(void); | ||
30 | extern char *prom_getenv(char *name); | ||
31 | extern void prom_init_cmdline(void); | ||
32 | extern void prom_meminit(void); | ||
33 | extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); | ||
34 | extern void mips_display_message(const char *str); | ||
35 | extern void mips_display_word(unsigned int num); | ||
36 | extern void mips_scroll_message(void); | ||
37 | extern int get_ethernet_addr(char *ethernet_addr); | ||
38 | |||
39 | /* Memory descriptor management. */ | ||
40 | #define PROM_MAX_PMEMBLOCKS 32 | ||
41 | struct prom_pmemblock { | ||
42 | unsigned long base; /* Within KSEG0. */ | ||
43 | unsigned int size; /* In bytes. */ | ||
44 | unsigned int type; /* free or prom memory */ | ||
45 | }; | ||
46 | |||
47 | #endif /* !(_MIPS_PROM_H) */ | ||
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0da44d422f5b..87e6207b05e4 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
@@ -596,6 +596,7 @@ | |||
596 | #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) | 596 | #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) |
597 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) | 597 | #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) |
598 | #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) | 598 | #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) |
599 | #define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) | ||
599 | #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) | 600 | #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) |
600 | 601 | ||
601 | #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) | 602 | #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) |
@@ -623,6 +624,24 @@ | |||
623 | #ifndef __ASSEMBLY__ | 624 | #ifndef __ASSEMBLY__ |
624 | 625 | ||
625 | /* | 626 | /* |
627 | * Macros for handling the ISA mode bit for microMIPS. | ||
628 | */ | ||
629 | #define get_isa16_mode(x) ((x) & 0x1) | ||
630 | #define msk_isa16_mode(x) ((x) & ~0x1) | ||
631 | #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) | ||
632 | |||
633 | /* | ||
634 | * microMIPS instructions can be 16-bit or 32-bit in length. This | ||
635 | * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. | ||
636 | */ | ||
637 | static inline int mm_insn_16bit(u16 insn) | ||
638 | { | ||
639 | u16 opcode = (insn >> 10) & 0x7; | ||
640 | |||
641 | return (opcode >= 1 && opcode <= 3) ? 1 : 0; | ||
642 | } | ||
643 | |||
644 | /* | ||
626 | * Functions to access the R10000 performance counters. These are basically | 645 | * Functions to access the R10000 performance counters. These are basically |
627 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit | 646 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit |
628 | * performance counter number encoded into bits 1 ... 5 of the instruction. | 647 | * performance counter number encoded into bits 1 ... 5 of the instruction. |
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index 820116067c10..1554721e4808 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h | |||
@@ -67,45 +67,68 @@ extern unsigned long pgd_current[]; | |||
67 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) | 67 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
68 | #endif | 68 | #endif |
69 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ | 69 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
70 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | ||
71 | 70 | ||
72 | #define ASID_INC 0x40 | 71 | #define ASID_INC(asid) \ |
73 | #define ASID_MASK 0xfc0 | 72 | ({ \ |
74 | 73 | unsigned long __asid = asid; \ | |
75 | #elif defined(CONFIG_CPU_R8000) | 74 | __asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \ |
76 | 75 | ".section\t__asid_inc,\"a\"\n\t" \ | |
77 | #define ASID_INC 0x10 | 76 | ".word\t1b\n\t" \ |
78 | #define ASID_MASK 0xff0 | 77 | ".previous" \ |
79 | 78 | :"=r" (__asid) \ | |
80 | #elif defined(CONFIG_MIPS_MT_SMTC) | 79 | :"0" (__asid)); \ |
81 | 80 | __asid; \ | |
82 | #define ASID_INC 0x1 | 81 | }) |
83 | extern unsigned long smtc_asid_mask; | 82 | #define ASID_MASK(asid) \ |
84 | #define ASID_MASK (smtc_asid_mask) | 83 | ({ \ |
85 | #define HW_ASID_MASK 0xff | 84 | unsigned long __asid = asid; \ |
86 | /* End SMTC/34K debug hack */ | 85 | __asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \ |
87 | #else /* FIXME: not correct for R6000 */ | 86 | ".section\t__asid_mask,\"a\"\n\t" \ |
88 | 87 | ".word\t1b\n\t" \ | |
89 | #define ASID_INC 0x1 | 88 | ".previous" \ |
90 | #define ASID_MASK 0xff | 89 | :"=r" (__asid) \ |
90 | :"r" (__asid)); \ | ||
91 | __asid; \ | ||
92 | }) | ||
93 | #define ASID_VERSION_MASK \ | ||
94 | ({ \ | ||
95 | unsigned long __asid; \ | ||
96 | __asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \ | ||
97 | ".section\t__asid_version_mask,\"a\"\n\t" \ | ||
98 | ".word\t1b\n\t" \ | ||
99 | ".previous" \ | ||
100 | :"=r" (__asid)); \ | ||
101 | __asid; \ | ||
102 | }) | ||
103 | #define ASID_FIRST_VERSION \ | ||
104 | ({ \ | ||
105 | unsigned long __asid = asid; \ | ||
106 | __asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \ | ||
107 | ".section\t__asid_first_version,\"a\"\n\t" \ | ||
108 | ".word\t1b\n\t" \ | ||
109 | ".previous" \ | ||
110 | :"=r" (__asid)); \ | ||
111 | __asid; \ | ||
112 | }) | ||
113 | |||
114 | #define ASID_FIRST_VERSION_R3000 0x1000 | ||
115 | #define ASID_FIRST_VERSION_R4000 0x100 | ||
116 | #define ASID_FIRST_VERSION_R8000 0x1000 | ||
117 | #define ASID_FIRST_VERSION_RM9000 0x1000 | ||
91 | 118 | ||
119 | #ifdef CONFIG_MIPS_MT_SMTC | ||
120 | #define SMTC_HW_ASID_MASK 0xff | ||
121 | extern unsigned int smtc_asid_mask; | ||
92 | #endif | 122 | #endif |
93 | 123 | ||
94 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) | 124 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
95 | #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) | 125 | #define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm))) |
96 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) | 126 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) |
97 | 127 | ||
98 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | 128 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) |
99 | { | 129 | { |
100 | } | 130 | } |
101 | 131 | ||
102 | /* | ||
103 | * All unused by hardware upper bits will be considered | ||
104 | * as a software asid extension. | ||
105 | */ | ||
106 | #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) | ||
107 | #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) | ||
108 | |||
109 | #ifndef CONFIG_MIPS_MT_SMTC | 132 | #ifndef CONFIG_MIPS_MT_SMTC |
110 | /* Normal, classic MIPS get_new_mmu_context */ | 133 | /* Normal, classic MIPS get_new_mmu_context */ |
111 | static inline void | 134 | static inline void |
@@ -114,7 +137,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |||
114 | extern void kvm_local_flush_tlb_all(void); | 137 | extern void kvm_local_flush_tlb_all(void); |
115 | unsigned long asid = asid_cache(cpu); | 138 | unsigned long asid = asid_cache(cpu); |
116 | 139 | ||
117 | if (! ((asid += ASID_INC) & ASID_MASK) ) { | 140 | if (!ASID_MASK((asid = ASID_INC(asid)))) { |
118 | if (cpu_has_vtag_icache) | 141 | if (cpu_has_vtag_icache) |
119 | flush_icache_all(); | 142 | flush_icache_all(); |
120 | #ifdef CONFIG_VIRTUALIZATION | 143 | #ifdef CONFIG_VIRTUALIZATION |
@@ -177,7 +200,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
177 | * free up the ASID value for use and flush any old | 200 | * free up the ASID value for use and flush any old |
178 | * instances of it from the TLB. | 201 | * instances of it from the TLB. |
179 | */ | 202 | */ |
180 | oldasid = (read_c0_entryhi() & ASID_MASK); | 203 | oldasid = ASID_MASK(read_c0_entryhi()); |
181 | if(smtc_live_asid[mytlb][oldasid]) { | 204 | if(smtc_live_asid[mytlb][oldasid]) { |
182 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 205 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
183 | if(smtc_live_asid[mytlb][oldasid] == 0) | 206 | if(smtc_live_asid[mytlb][oldasid] == 0) |
@@ -188,7 +211,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
188 | * having ASID_MASK smaller than the hardware maximum, | 211 | * having ASID_MASK smaller than the hardware maximum, |
189 | * make sure no "soft" bits become "hard"... | 212 | * make sure no "soft" bits become "hard"... |
190 | */ | 213 | */ |
191 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | | 214 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | |
192 | cpu_asid(cpu, next)); | 215 | cpu_asid(cpu, next)); |
193 | ehb(); /* Make sure it propagates to TCStatus */ | 216 | ehb(); /* Make sure it propagates to TCStatus */ |
194 | evpe(mtflags); | 217 | evpe(mtflags); |
@@ -241,15 +264,15 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) | |||
241 | #ifdef CONFIG_MIPS_MT_SMTC | 264 | #ifdef CONFIG_MIPS_MT_SMTC |
242 | /* See comments for similar code above */ | 265 | /* See comments for similar code above */ |
243 | mtflags = dvpe(); | 266 | mtflags = dvpe(); |
244 | oldasid = read_c0_entryhi() & ASID_MASK; | 267 | oldasid = ASID_MASK(read_c0_entryhi()); |
245 | if(smtc_live_asid[mytlb][oldasid]) { | 268 | if(smtc_live_asid[mytlb][oldasid]) { |
246 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 269 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
247 | if(smtc_live_asid[mytlb][oldasid] == 0) | 270 | if(smtc_live_asid[mytlb][oldasid] == 0) |
248 | smtc_flush_tlb_asid(oldasid); | 271 | smtc_flush_tlb_asid(oldasid); |
249 | } | 272 | } |
250 | /* See comments for similar code above */ | 273 | /* See comments for similar code above */ |
251 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | | 274 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | |
252 | cpu_asid(cpu, next)); | 275 | cpu_asid(cpu, next)); |
253 | ehb(); /* Make sure it propagates to TCStatus */ | 276 | ehb(); /* Make sure it propagates to TCStatus */ |
254 | evpe(mtflags); | 277 | evpe(mtflags); |
255 | #else | 278 | #else |
@@ -286,14 +309,14 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) | |||
286 | #ifdef CONFIG_MIPS_MT_SMTC | 309 | #ifdef CONFIG_MIPS_MT_SMTC |
287 | /* See comments for similar code above */ | 310 | /* See comments for similar code above */ |
288 | prevvpe = dvpe(); | 311 | prevvpe = dvpe(); |
289 | oldasid = (read_c0_entryhi() & ASID_MASK); | 312 | oldasid = ASID_MASK(read_c0_entryhi()); |
290 | if (smtc_live_asid[mytlb][oldasid]) { | 313 | if (smtc_live_asid[mytlb][oldasid]) { |
291 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); | 314 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
292 | if(smtc_live_asid[mytlb][oldasid] == 0) | 315 | if(smtc_live_asid[mytlb][oldasid] == 0) |
293 | smtc_flush_tlb_asid(oldasid); | 316 | smtc_flush_tlb_asid(oldasid); |
294 | } | 317 | } |
295 | /* See comments for similar code above */ | 318 | /* See comments for similar code above */ |
296 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 319 | write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) |
297 | | cpu_asid(cpu, mm)); | 320 | | cpu_asid(cpu, mm)); |
298 | ehb(); /* Make sure it propagates to TCStatus */ | 321 | ehb(); /* Make sure it propagates to TCStatus */ |
299 | evpe(prevvpe); | 322 | evpe(prevvpe); |
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index c99384018161..a89d1b10d027 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h | |||
@@ -139,7 +139,7 @@ | |||
139 | 1: move ra, k0 | 139 | 1: move ra, k0 |
140 | li k0, 3 | 140 | li k0, 3 |
141 | mtc0 k0, $22 | 141 | mtc0 k0, $22 |
142 | #endif /* CONFIG_CPU_LOONGSON2F */ | 142 | #endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ |
143 | #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) | 143 | #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) |
144 | lui k1, %hi(kernelsp) | 144 | lui k1, %hi(kernelsp) |
145 | #else | 145 | #else |
@@ -189,6 +189,7 @@ | |||
189 | LONG_S $0, PT_R0(sp) | 189 | LONG_S $0, PT_R0(sp) |
190 | mfc0 v1, CP0_STATUS | 190 | mfc0 v1, CP0_STATUS |
191 | LONG_S $2, PT_R2(sp) | 191 | LONG_S $2, PT_R2(sp) |
192 | LONG_S v1, PT_STATUS(sp) | ||
192 | #ifdef CONFIG_MIPS_MT_SMTC | 193 | #ifdef CONFIG_MIPS_MT_SMTC |
193 | /* | 194 | /* |
194 | * Ideally, these instructions would be shuffled in | 195 | * Ideally, these instructions would be shuffled in |
@@ -200,21 +201,20 @@ | |||
200 | LONG_S k0, PT_TCSTATUS(sp) | 201 | LONG_S k0, PT_TCSTATUS(sp) |
201 | #endif /* CONFIG_MIPS_MT_SMTC */ | 202 | #endif /* CONFIG_MIPS_MT_SMTC */ |
202 | LONG_S $4, PT_R4(sp) | 203 | LONG_S $4, PT_R4(sp) |
203 | LONG_S $5, PT_R5(sp) | ||
204 | LONG_S v1, PT_STATUS(sp) | ||
205 | mfc0 v1, CP0_CAUSE | 204 | mfc0 v1, CP0_CAUSE |
206 | LONG_S $6, PT_R6(sp) | 205 | LONG_S $5, PT_R5(sp) |
207 | LONG_S $7, PT_R7(sp) | ||
208 | LONG_S v1, PT_CAUSE(sp) | 206 | LONG_S v1, PT_CAUSE(sp) |
207 | LONG_S $6, PT_R6(sp) | ||
209 | MFC0 v1, CP0_EPC | 208 | MFC0 v1, CP0_EPC |
209 | LONG_S $7, PT_R7(sp) | ||
210 | #ifdef CONFIG_64BIT | 210 | #ifdef CONFIG_64BIT |
211 | LONG_S $8, PT_R8(sp) | 211 | LONG_S $8, PT_R8(sp) |
212 | LONG_S $9, PT_R9(sp) | 212 | LONG_S $9, PT_R9(sp) |
213 | #endif | 213 | #endif |
214 | LONG_S v1, PT_EPC(sp) | ||
214 | LONG_S $25, PT_R25(sp) | 215 | LONG_S $25, PT_R25(sp) |
215 | LONG_S $28, PT_R28(sp) | 216 | LONG_S $28, PT_R28(sp) |
216 | LONG_S $31, PT_R31(sp) | 217 | LONG_S $31, PT_R31(sp) |
217 | LONG_S v1, PT_EPC(sp) | ||
218 | ori $28, sp, _THREAD_MASK | 218 | ori $28, sp, _THREAD_MASK |
219 | xori $28, _THREAD_MASK | 219 | xori $28, _THREAD_MASK |
220 | #ifdef CONFIG_CPU_CAVIUM_OCTEON | 220 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index debc8009bd58..2d7b9df4542d 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h | |||
@@ -52,13 +52,15 @@ extern int (*perf_irq)(void); | |||
52 | */ | 52 | */ |
53 | extern unsigned int __weak get_c0_compare_int(void); | 53 | extern unsigned int __weak get_c0_compare_int(void); |
54 | extern int r4k_clockevent_init(void); | 54 | extern int r4k_clockevent_init(void); |
55 | extern int smtc_clockevent_init(void); | ||
56 | extern int gic_clockevent_init(void); | ||
55 | 57 | ||
56 | static inline int mips_clockevent_init(void) | 58 | static inline int mips_clockevent_init(void) |
57 | { | 59 | { |
58 | #ifdef CONFIG_MIPS_MT_SMTC | 60 | #ifdef CONFIG_MIPS_MT_SMTC |
59 | extern int smtc_clockevent_init(void); | ||
60 | |||
61 | return smtc_clockevent_init(); | 61 | return smtc_clockevent_init(); |
62 | #elif defined(CONFIG_CEVT_GIC) | ||
63 | return (gic_clockevent_init() | r4k_clockevent_init()); | ||
62 | #elif defined(CONFIG_CEVT_R4K) | 64 | #elif defined(CONFIG_CEVT_R4K) |
63 | return r4k_clockevent_init(); | 65 | return r4k_clockevent_init(); |
64 | #else | 66 | #else |
@@ -69,9 +71,7 @@ static inline int mips_clockevent_init(void) | |||
69 | /* | 71 | /* |
70 | * Initialize the count register as a clocksource | 72 | * Initialize the count register as a clocksource |
71 | */ | 73 | */ |
72 | #ifdef CONFIG_CSRC_R4K | ||
73 | extern int init_r4k_clocksource(void); | 74 | extern int init_r4k_clocksource(void); |
74 | #endif | ||
75 | 75 | ||
76 | static inline int init_mips_clocksource(void) | 76 | static inline int init_mips_clocksource(void) |
77 | { | 77 | { |
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index b46caab453a5..f3fa3750f577 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h | |||
@@ -270,6 +270,7 @@ do { \ | |||
270 | __asm__ __volatile__( \ | 270 | __asm__ __volatile__( \ |
271 | "1: " insn " %1, %3 \n" \ | 271 | "1: " insn " %1, %3 \n" \ |
272 | "2: \n" \ | 272 | "2: \n" \ |
273 | " .insn \n" \ | ||
273 | " .section .fixup,\"ax\" \n" \ | 274 | " .section .fixup,\"ax\" \n" \ |
274 | "3: li %0, %4 \n" \ | 275 | "3: li %0, %4 \n" \ |
275 | " j 2b \n" \ | 276 | " j 2b \n" \ |
@@ -296,7 +297,9 @@ do { \ | |||
296 | __asm__ __volatile__( \ | 297 | __asm__ __volatile__( \ |
297 | "1: lw %1, (%3) \n" \ | 298 | "1: lw %1, (%3) \n" \ |
298 | "2: lw %D1, 4(%3) \n" \ | 299 | "2: lw %D1, 4(%3) \n" \ |
299 | "3: .section .fixup,\"ax\" \n" \ | 300 | "3: \n" \ |
301 | " .insn \n" \ | ||
302 | " .section .fixup,\"ax\" \n" \ | ||
300 | "4: li %0, %4 \n" \ | 303 | "4: li %0, %4 \n" \ |
301 | " move %1, $0 \n" \ | 304 | " move %1, $0 \n" \ |
302 | " move %D1, $0 \n" \ | 305 | " move %D1, $0 \n" \ |
@@ -364,6 +367,7 @@ do { \ | |||
364 | __asm__ __volatile__( \ | 367 | __asm__ __volatile__( \ |
365 | "1: " insn " %z2, %3 # __put_user_asm\n" \ | 368 | "1: " insn " %z2, %3 # __put_user_asm\n" \ |
366 | "2: \n" \ | 369 | "2: \n" \ |
370 | " .insn \n" \ | ||
367 | " .section .fixup,\"ax\" \n" \ | 371 | " .section .fixup,\"ax\" \n" \ |
368 | "3: li %0, %4 \n" \ | 372 | "3: li %0, %4 \n" \ |
369 | " j 2b \n" \ | 373 | " j 2b \n" \ |
@@ -382,6 +386,7 @@ do { \ | |||
382 | "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ | 386 | "1: sw %2, (%3) # __put_user_asm_ll32 \n" \ |
383 | "2: sw %D2, 4(%3) \n" \ | 387 | "2: sw %D2, 4(%3) \n" \ |
384 | "3: \n" \ | 388 | "3: \n" \ |
389 | " .insn \n" \ | ||
385 | " .section .fixup,\"ax\" \n" \ | 390 | " .section .fixup,\"ax\" \n" \ |
386 | "4: li %0, %4 \n" \ | 391 | "4: li %0, %4 \n" \ |
387 | " j 3b \n" \ | 392 | " j 3b \n" \ |
@@ -533,6 +538,7 @@ do { \ | |||
533 | __asm__ __volatile__( \ | 538 | __asm__ __volatile__( \ |
534 | "1: " insn " %1, %3 \n" \ | 539 | "1: " insn " %1, %3 \n" \ |
535 | "2: \n" \ | 540 | "2: \n" \ |
541 | " .insn \n" \ | ||
536 | " .section .fixup,\"ax\" \n" \ | 542 | " .section .fixup,\"ax\" \n" \ |
537 | "3: li %0, %4 \n" \ | 543 | "3: li %0, %4 \n" \ |
538 | " j 2b \n" \ | 544 | " j 2b \n" \ |
@@ -558,7 +564,9 @@ do { \ | |||
558 | "1: ulw %1, (%3) \n" \ | 564 | "1: ulw %1, (%3) \n" \ |
559 | "2: ulw %D1, 4(%3) \n" \ | 565 | "2: ulw %D1, 4(%3) \n" \ |
560 | " move %0, $0 \n" \ | 566 | " move %0, $0 \n" \ |
561 | "3: .section .fixup,\"ax\" \n" \ | 567 | "3: \n" \ |
568 | " .insn \n" \ | ||
569 | " .section .fixup,\"ax\" \n" \ | ||
562 | "4: li %0, %4 \n" \ | 570 | "4: li %0, %4 \n" \ |
563 | " move %1, $0 \n" \ | 571 | " move %1, $0 \n" \ |
564 | " move %D1, $0 \n" \ | 572 | " move %D1, $0 \n" \ |
@@ -625,6 +633,7 @@ do { \ | |||
625 | __asm__ __volatile__( \ | 633 | __asm__ __volatile__( \ |
626 | "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ | 634 | "1: " insn " %z2, %3 # __put_user_unaligned_asm\n" \ |
627 | "2: \n" \ | 635 | "2: \n" \ |
636 | " .insn \n" \ | ||
628 | " .section .fixup,\"ax\" \n" \ | 637 | " .section .fixup,\"ax\" \n" \ |
629 | "3: li %0, %4 \n" \ | 638 | "3: li %0, %4 \n" \ |
630 | " j 2b \n" \ | 639 | " j 2b \n" \ |
@@ -643,6 +652,7 @@ do { \ | |||
643 | "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ | 652 | "1: sw %2, (%3) # __put_user_unaligned_asm_ll32 \n" \ |
644 | "2: sw %D2, 4(%3) \n" \ | 653 | "2: sw %D2, 4(%3) \n" \ |
645 | "3: \n" \ | 654 | "3: \n" \ |
655 | " .insn \n" \ | ||
646 | " .section .fixup,\"ax\" \n" \ | 656 | " .section .fixup,\"ax\" \n" \ |
647 | "4: li %0, %4 \n" \ | 657 | "4: li %0, %4 \n" \ |
648 | " j 3b \n" \ | 658 | " j 3b \n" \ |
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 058e941626a6..370d967725c2 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h | |||
@@ -6,7 +6,7 @@ | |||
6 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer | 6 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
7 | * Copyright (C) 2005 Maciej W. Rozycki | 7 | * Copyright (C) 2005 Maciej W. Rozycki |
8 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | 8 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
9 | * Copyright (C) 2012 MIPS Technologies, Inc. | 9 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/types.h> | 12 | #include <linux/types.h> |
@@ -22,44 +22,75 @@ | |||
22 | #define UASM_EXPORT_SYMBOL(sym) | 22 | #define UASM_EXPORT_SYMBOL(sym) |
23 | #endif | 23 | #endif |
24 | 24 | ||
25 | #define _UASM_ISA_CLASSIC 0 | ||
26 | #define _UASM_ISA_MICROMIPS 1 | ||
27 | |||
28 | #ifndef UASM_ISA | ||
29 | #ifdef CONFIG_CPU_MICROMIPS | ||
30 | #define UASM_ISA _UASM_ISA_MICROMIPS | ||
31 | #else | ||
32 | #define UASM_ISA _UASM_ISA_CLASSIC | ||
33 | #endif | ||
34 | #endif | ||
35 | |||
36 | #if (UASM_ISA == _UASM_ISA_CLASSIC) | ||
37 | #ifdef CONFIG_CPU_MICROMIPS | ||
38 | #define ISAOPC(op) CL_uasm_i##op | ||
39 | #define ISAFUNC(x) CL_##x | ||
40 | #else | ||
41 | #define ISAOPC(op) uasm_i##op | ||
42 | #define ISAFUNC(x) x | ||
43 | #endif | ||
44 | #elif (UASM_ISA == _UASM_ISA_MICROMIPS) | ||
45 | #ifdef CONFIG_CPU_MICROMIPS | ||
46 | #define ISAOPC(op) uasm_i##op | ||
47 | #define ISAFUNC(x) x | ||
48 | #else | ||
49 | #define ISAOPC(op) MM_uasm_i##op | ||
50 | #define ISAFUNC(x) MM_##x | ||
51 | #endif | ||
52 | #else | ||
53 | #error Unsupported micro-assembler ISA!!! | ||
54 | #endif | ||
55 | |||
25 | #define Ip_u1u2u3(op) \ | 56 | #define Ip_u1u2u3(op) \ |
26 | void __uasminit \ | 57 | void __uasminit \ |
27 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) | 58 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) |
28 | 59 | ||
29 | #define Ip_u2u1u3(op) \ | 60 | #define Ip_u2u1u3(op) \ |
30 | void __uasminit \ | 61 | void __uasminit \ |
31 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) | 62 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) |
32 | 63 | ||
33 | #define Ip_u3u1u2(op) \ | 64 | #define Ip_u3u1u2(op) \ |
34 | void __uasminit \ | 65 | void __uasminit \ |
35 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) | 66 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c) |
36 | 67 | ||
37 | #define Ip_u1u2s3(op) \ | 68 | #define Ip_u1u2s3(op) \ |
38 | void __uasminit \ | 69 | void __uasminit \ |
39 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) | 70 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) |
40 | 71 | ||
41 | #define Ip_u2s3u1(op) \ | 72 | #define Ip_u2s3u1(op) \ |
42 | void __uasminit \ | 73 | void __uasminit \ |
43 | uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) | 74 | ISAOPC(op)(u32 **buf, unsigned int a, signed int b, unsigned int c) |
44 | 75 | ||
45 | #define Ip_u2u1s3(op) \ | 76 | #define Ip_u2u1s3(op) \ |
46 | void __uasminit \ | 77 | void __uasminit \ |
47 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) | 78 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, signed int c) |
48 | 79 | ||
49 | #define Ip_u2u1msbu3(op) \ | 80 | #define Ip_u2u1msbu3(op) \ |
50 | void __uasminit \ | 81 | void __uasminit \ |
51 | uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ | 82 | ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ |
52 | unsigned int d) | 83 | unsigned int d) |
53 | 84 | ||
54 | #define Ip_u1u2(op) \ | 85 | #define Ip_u1u2(op) \ |
55 | void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) | 86 | void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) |
56 | 87 | ||
57 | #define Ip_u1s2(op) \ | 88 | #define Ip_u1s2(op) \ |
58 | void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b) | 89 | void __uasminit ISAOPC(op)(u32 **buf, unsigned int a, signed int b) |
59 | 90 | ||
60 | #define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a) | 91 | #define Ip_u1(op) void __uasminit ISAOPC(op)(u32 **buf, unsigned int a) |
61 | 92 | ||
62 | #define Ip_0(op) void __uasminit uasm_i##op(u32 **buf) | 93 | #define Ip_0(op) void __uasminit ISAOPC(op)(u32 **buf) |
63 | 94 | ||
64 | Ip_u2u1s3(_addiu); | 95 | Ip_u2u1s3(_addiu); |
65 | Ip_u3u1u2(_addu); | 96 | Ip_u3u1u2(_addu); |
@@ -132,19 +163,20 @@ struct uasm_label { | |||
132 | int lab; | 163 | int lab; |
133 | }; | 164 | }; |
134 | 165 | ||
135 | void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); | 166 | void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, |
167 | int lid); | ||
136 | #ifdef CONFIG_64BIT | 168 | #ifdef CONFIG_64BIT |
137 | int uasm_in_compat_space_p(long addr); | 169 | int ISAFUNC(uasm_in_compat_space_p)(long addr); |
138 | #endif | 170 | #endif |
139 | int uasm_rel_hi(long val); | 171 | int ISAFUNC(uasm_rel_hi)(long val); |
140 | int uasm_rel_lo(long val); | 172 | int ISAFUNC(uasm_rel_lo)(long val); |
141 | void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); | 173 | void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr); |
142 | void UASM_i_LA(u32 **buf, unsigned int rs, long addr); | 174 | void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr); |
143 | 175 | ||
144 | #define UASM_L_LA(lb) \ | 176 | #define UASM_L_LA(lb) \ |
145 | static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ | 177 | static inline void __uasminit ISAFUNC(uasm_l##lb)(struct uasm_label **lab, u32 *addr) \ |
146 | { \ | 178 | { \ |
147 | uasm_build_label(lab, addr, label##lb); \ | 179 | ISAFUNC(uasm_build_label)(lab, addr, label##lb); \ |
148 | } | 180 | } |
149 | 181 | ||
150 | /* convenience macros for instructions */ | 182 | /* convenience macros for instructions */ |
@@ -196,27 +228,27 @@ static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, | |||
196 | unsigned int a2, unsigned int a3) | 228 | unsigned int a2, unsigned int a3) |
197 | { | 229 | { |
198 | if (a3 < 32) | 230 | if (a3 < 32) |
199 | uasm_i_drotr(p, a1, a2, a3); | 231 | ISAOPC(_drotr)(p, a1, a2, a3); |
200 | else | 232 | else |
201 | uasm_i_drotr32(p, a1, a2, a3 - 32); | 233 | ISAOPC(_drotr32)(p, a1, a2, a3 - 32); |
202 | } | 234 | } |
203 | 235 | ||
204 | static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, | 236 | static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, |
205 | unsigned int a2, unsigned int a3) | 237 | unsigned int a2, unsigned int a3) |
206 | { | 238 | { |
207 | if (a3 < 32) | 239 | if (a3 < 32) |
208 | uasm_i_dsll(p, a1, a2, a3); | 240 | ISAOPC(_dsll)(p, a1, a2, a3); |
209 | else | 241 | else |
210 | uasm_i_dsll32(p, a1, a2, a3 - 32); | 242 | ISAOPC(_dsll32)(p, a1, a2, a3 - 32); |
211 | } | 243 | } |
212 | 244 | ||
213 | static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, | 245 | static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1, |
214 | unsigned int a2, unsigned int a3) | 246 | unsigned int a2, unsigned int a3) |
215 | { | 247 | { |
216 | if (a3 < 32) | 248 | if (a3 < 32) |
217 | uasm_i_dsrl(p, a1, a2, a3); | 249 | ISAOPC(_dsrl)(p, a1, a2, a3); |
218 | else | 250 | else |
219 | uasm_i_dsrl32(p, a1, a2, a3 - 32); | 251 | ISAOPC(_dsrl32)(p, a1, a2, a3 - 32); |
220 | } | 252 | } |
221 | 253 | ||
222 | /* Handle relocations. */ | 254 | /* Handle relocations. */ |