diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2013-09-22 18:06:27 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2013-10-29 16:24:46 -0400 |
commit | 33afab80f0da8d7fc9e85297c86d3c46eeb185cd (patch) | |
tree | 5c26d8e575d7d904fde61a787c0fd1b7213db008 /arch/mips/include/asm | |
parent | 07217d75b7016a6422b3736c4a88b86aa6c0c7b1 (diff) |
MIPS: DECstation CPU feature overrides
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5877/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r-- | arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h new file mode 100644 index 000000000000..acce27fd2bb8 --- /dev/null +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * CPU feature overrides for DECstation systems. Two variations | ||
3 | * are generally applicable. | ||
4 | * | ||
5 | * Copyright (C) 2013 Maciej W. Rozycki | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License | ||
9 | * as published by the Free Software Foundation; either version | ||
10 | * 2 of the License, or (at your option) any later version. | ||
11 | */ | ||
12 | #ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H | ||
13 | #define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H | ||
14 | |||
15 | /* Generic ones first. */ | ||
16 | #define cpu_has_tlb 1 | ||
17 | #define cpu_has_tx39_cache 0 | ||
18 | #define cpu_has_fpu 1 | ||
19 | #define cpu_has_divec 0 | ||
20 | #define cpu_has_prefetch 0 | ||
21 | #define cpu_has_mcheck 0 | ||
22 | #define cpu_has_ejtag 0 | ||
23 | #define cpu_has_mips16 0 | ||
24 | #define cpu_has_mdmx 0 | ||
25 | #define cpu_has_mips3d 0 | ||
26 | #define cpu_has_smartmips 0 | ||
27 | #define cpu_has_rixi 0 | ||
28 | #define cpu_has_vtag_icache 0 | ||
29 | #define cpu_has_ic_fills_f_dc 0 | ||
30 | #define cpu_has_pindexed_dcache 0 | ||
31 | #define cpu_has_local_ebase 0 | ||
32 | #define cpu_icache_snoops_remote_store 1 | ||
33 | #define cpu_has_mips_4 0 | ||
34 | #define cpu_has_mips_5 0 | ||
35 | #define cpu_has_mips32r1 0 | ||
36 | #define cpu_has_mips32r2 0 | ||
37 | #define cpu_has_mips64r1 0 | ||
38 | #define cpu_has_mips64r2 0 | ||
39 | #define cpu_has_dsp 0 | ||
40 | #define cpu_has_mipsmt 0 | ||
41 | #define cpu_has_userlocal 0 | ||
42 | |||
43 | /* R3k-specific ones. */ | ||
44 | #ifdef CONFIG_CPU_R3000 | ||
45 | #define cpu_has_4kex 0 | ||
46 | #define cpu_has_3k_cache 1 | ||
47 | #define cpu_has_4k_cache 0 | ||
48 | #define cpu_has_32fpr 0 | ||
49 | #define cpu_has_counter 0 | ||
50 | #define cpu_has_watch 0 | ||
51 | #define cpu_has_vce 0 | ||
52 | #define cpu_has_cache_cdex_p 0 | ||
53 | #define cpu_has_cache_cdex_s 0 | ||
54 | #define cpu_has_llsc 0 | ||
55 | #define cpu_has_dc_aliases 0 | ||
56 | #define cpu_has_mips_2 0 | ||
57 | #define cpu_has_mips_3 0 | ||
58 | #define cpu_has_nofpuex 1 | ||
59 | #define cpu_has_inclusive_pcaches 0 | ||
60 | #define cpu_dcache_line_size() 4 | ||
61 | #define cpu_icache_line_size() 4 | ||
62 | #define cpu_scache_line_size() 0 | ||
63 | #endif /* CONFIG_CPU_R3000 */ | ||
64 | |||
65 | /* R4k-specific ones. */ | ||
66 | #ifdef CONFIG_CPU_R4X00 | ||
67 | #define cpu_has_4kex 1 | ||
68 | #define cpu_has_3k_cache 0 | ||
69 | #define cpu_has_4k_cache 1 | ||
70 | #define cpu_has_32fpr 1 | ||
71 | #define cpu_has_counter 1 | ||
72 | #define cpu_has_watch 1 | ||
73 | #define cpu_has_vce 1 | ||
74 | #define cpu_has_cache_cdex_p 1 | ||
75 | #define cpu_has_cache_cdex_s 1 | ||
76 | #define cpu_has_llsc 1 | ||
77 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) | ||
78 | #define cpu_has_mips_2 1 | ||
79 | #define cpu_has_mips_3 1 | ||
80 | #define cpu_has_nofpuex 0 | ||
81 | #define cpu_has_inclusive_pcaches 1 | ||
82 | #define cpu_dcache_line_size() 16 | ||
83 | #define cpu_icache_line_size() 16 | ||
84 | #define cpu_scache_line_size() 32 | ||
85 | #endif /* CONFIG_CPU_R4X00 */ | ||
86 | |||
87 | #endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ | ||