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authorIngo Molnar <mingo@elte.hu>2009-01-16 04:09:10 -0500
committerIngo Molnar <mingo@elte.hu>2009-01-16 04:09:10 -0500
commitaf2519fb2298cdf7540082c36f4d8c66bbff103f (patch)
tree1d290d28d42d42f9e693457762c4008988628060 /arch/mips/include/asm
parent961d7d0ee5150e0197cc81c2a8884ecb230276e2 (diff)
parent7cb36b6ccdca03bd87e8faca7fd920643dd1aec7 (diff)
Merge branch 'linus' into core/iommu
Conflicts: arch/ia64/include/asm/dma-mapping.h arch/ia64/include/asm/machvec.h arch/ia64/include/asm/machvec_sn2.h
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/Kbuild1
-rw-r--r--arch/mips/include/asm/byteorder.h2
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h14
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/io.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h89
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h5
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h78
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h64
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h244
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h131
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h26
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-lemote/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mipsregs.h22
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asm.h128
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h262
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h288
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ciu-defs.h1616
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gpio-defs.h219
-rw-r--r--arch/mips/include/asm/octeon/cvmx-iob-defs.h530
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd-defs.h877
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c-defs.h963
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h325
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2d-defs.h369
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2t-defs.h141
-rw-r--r--arch/mips/include/asm/octeon/cvmx-led-defs.h240
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h2004
-rw-r--r--arch/mips/include/asm/octeon/cvmx-packet.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow-defs.h698
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spinlock.h232
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sysinfo.h152
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h505
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h119
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h321
-rw-r--r--arch/mips/include/asm/octeon/octeon.h248
-rw-r--r--arch/mips/include/asm/processor.h69
-rw-r--r--arch/mips/include/asm/ptrace.h4
-rw-r--r--arch/mips/include/asm/smp.h3
-rw-r--r--arch/mips/include/asm/stackframe.h17
-rw-r--r--arch/mips/include/asm/time.h24
46 files changed, 11191 insertions, 53 deletions
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 023866c0c102..7897f05e3165 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,4 +1,3 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += cachectl.h sgidefs.h sysmips.h 3header-y += cachectl.h sgidefs.h sysmips.h
4header-y += swab.h
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
index 607b71830707..9579051ff1c7 100644
--- a/arch/mips/include/asm/byteorder.h
+++ b/arch/mips/include/asm/byteorder.h
@@ -8,8 +8,6 @@
8#ifndef _ASM_BYTEORDER_H 8#ifndef _ASM_BYTEORDER_H
9#define _ASM_BYTEORDER_H 9#define _ASM_BYTEORDER_H
10 10
11#include <asm/swab.h>
12
13#if defined(__MIPSEB__) 11#if defined(__MIPSEB__)
14#include <linux/byteorder/big_endian.h> 12#include <linux/byteorder/big_endian.h>
15#elif defined(__MIPSEL__) 13#elif defined(__MIPSEL__)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 12d12dfe73c0..a0d14f85b781 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
38#ifndef cpu_has_tx39_cache 38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif 40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
41#ifndef cpu_has_fpu 44#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786101d9..c018727c7ddc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_CAVIUM 0x0d0000
36 37
37 38
38/* 39/*
@@ -114,6 +115,18 @@
114#define PRID_IMP_BCM3302 0x9000 115#define PRID_IMP_BCM3302 0x9000
115 116
116/* 117/*
118 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
119 */
120
121#define PRID_IMP_CAVIUM_CN38XX 0x0000
122#define PRID_IMP_CAVIUM_CN31XX 0x0100
123#define PRID_IMP_CAVIUM_CN30XX 0x0200
124#define PRID_IMP_CAVIUM_CN58XX 0x0300
125#define PRID_IMP_CAVIUM_CN56XX 0x0400
126#define PRID_IMP_CAVIUM_CN50XX 0x0600
127#define PRID_IMP_CAVIUM_CN52XX 0x0700
128
129/*
117 * Definitions for 7:0 on legacy processors 130 * Definitions for 7:0 on legacy processors
118 */ 131 */
119 132
@@ -203,6 +216,7 @@ enum cpu_type_enum {
203 * MIPS64 class processors 216 * MIPS64 class processors
204 */ 217 */
205 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 218 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
219 CPU_CAVIUM_OCTEON,
206 220
207 CPU_LAST 221 CPU_LAST
208}; 222};
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f84c86..43baed16a109 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
42/* 42/*
43 * TLB hazards 43 * TLB hazards
44 */ 44 */
45#if defined(CONFIG_CPU_MIPSR2) 45#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
46 46
47/* 47/*
48 * MIPSR2 defines ehb for hazard avoidance 48 * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) 141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
142 142
143/* 143/*
144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 501a40b9f18d..436878e4e063 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
295#undef __IS_KSEG1 295#undef __IS_KSEG1
296} 296}
297 297
298#ifdef CONFIG_CPU_CAVIUM_OCTEON
299#define war_octeon_io_reorder_wmb() wmb()
300#else
301#define war_octeon_io_reorder_wmb() do { } while (0)
302#endif
303
298#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 304#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
299 \ 305 \
300static inline void pfx##write##bwlq(type val, \ 306static inline void pfx##write##bwlq(type val, \
@@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \
303 volatile type *__mem; \ 309 volatile type *__mem; \
304 type __val; \ 310 type __val; \
305 \ 311 \
312 war_octeon_io_reorder_wmb(); \
313 \
306 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
307 \ 315 \
308 __val = pfx##ioswab##bwlq(__mem, val); \ 316 __val = pfx##ioswab##bwlq(__mem, val); \
@@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
370 volatile type *__addr; \ 378 volatile type *__addr; \
371 type __val; \ 379 type __val; \
372 \ 380 \
381 war_octeon_io_reorder_wmb(); \
382 \
373 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 383 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
374 \ 384 \
375 __val = pfx##ioswab##bwlq(__addr, val); \ 385 __val = pfx##ioswab##bwlq(__addr, val); \
@@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
504#endif 514#endif
505 515
506 516
517#ifdef CONFIG_CPU_CAVIUM_OCTEON
518#define mmiowb() wmb()
519#else
507/* Depends on MIPS II instruction set */ 520/* Depends on MIPS II instruction set */
508#define mmiowb() asm volatile ("sync" ::: "memory") 521#define mmiowb() asm volatile ("sync" ::: "memory")
522#endif
509 523
510static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 524static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
511{ 525{
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 0d302bad4492..62f91f50b5b5 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -91,14 +91,57 @@ static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg; 91 return *(volatile u32 *)reg;
92} 92}
93 93
94/* Early Au1000 have a write-only SYS_CPUPLL register. */
95static inline int au1xxx_cpu_has_pll_wo(void)
96{
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104}
105
106/* does CPU need CONFIG[OD] set to fix tons of errata? */
107static inline int au1xxx_cpu_needs_config_od(void)
108{
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131}
94 132
95/* arch/mips/au1000/common/clocks.c */ 133/* arch/mips/au1000/common/clocks.c */
96extern void set_au1x00_speed(unsigned int new_freq); 134extern void set_au1x00_speed(unsigned int new_freq);
97extern unsigned int get_au1x00_speed(void); 135extern unsigned int get_au1x00_speed(void);
98extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 136extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
99extern unsigned long get_au1x00_uart_baud_base(void); 137extern unsigned long get_au1x00_uart_baud_base(void);
100extern void set_au1x00_lcd_clock(void); 138extern unsigned long au1xxx_calc_clock(void);
101extern unsigned int get_au1x00_lcd_clock(void); 139
140/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
141void au1xxx_save_and_sleep(void);
142void au_sleep(void);
143void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void);
102 145
103/* 146/*
104 * Every board describes its IRQ mapping with this table. 147 * Every board describes its IRQ mapping with this table.
@@ -109,10 +152,11 @@ struct au1xxx_irqmap {
109 int im_request; 152 int im_request;
110}; 153};
111 154
112/* 155/* core calls this function to let boards initialize other IRQ sources */
113 * init_IRQ looks for a table with this name. 156void board_init_irq(void);
114 */ 157
115extern struct au1xxx_irqmap au1xxx_irq_map[]; 158/* boards call this to register additional (GPIO) interrupts */
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
116 160
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 161#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118 162
@@ -505,15 +549,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
505 549
506#define IC1_TESTBIT 0xB1800080 550#define IC1_TESTBIT 0xB1800080
507 551
508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516
517/* Interrupt Numbers */ 552/* Interrupt Numbers */
518/* Au1000 */ 553/* Au1000 */
519#ifdef CONFIG_SOC_AU1000 554#ifdef CONFIG_SOC_AU1000
@@ -1525,6 +1560,10 @@ enum soc_au1200_ints {
1525#define SYS_SLPPWR 0xB1900078 1560#define SYS_SLPPWR 0xB1900078
1526#define SYS_SLEEP 0xB190007C 1561#define SYS_SLEEP 0xB190007C
1527 1562
1563#define SYS_WAKEMSK_D2 (1 << 9)
1564#define SYS_WAKEMSK_M2 (1 << 8)
1565#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1566
1528/* Clock Controller */ 1567/* Clock Controller */
1529#define SYS_FREQCTRL0 0xB1900020 1568#define SYS_FREQCTRL0 0xB1900020
1530# define SYS_FC_FRDIV2_BIT 22 1569# define SYS_FC_FRDIV2_BIT 22
@@ -1749,24 +1788,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1749 1788
1750#endif 1789#endif
1751 1790
1752/*
1753 * Processor information based on PRID.
1754 * Copied from PowerPC.
1755 */
1756#ifndef _LANGUAGE_ASSEMBLY
1757struct cpu_spec {
1758 /* CPU is matched via (PRID & prid_mask) == prid_value */
1759 unsigned int prid_mask;
1760 unsigned int prid_value;
1761
1762 char *cpu_name;
1763 unsigned char cpu_od; /* Set Config[OD] */
1764 unsigned char cpu_bclk; /* Enable BCLK switching */
1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1766};
1767
1768extern struct cpu_spec cpu_specs[];
1769extern struct cpu_spec *cur_cpu_spec[];
1770#endif
1771
1772#endif 1791#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 44a67bf05dc1..06f68f43800a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -357,6 +357,11 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); 357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
358extern void au1xxx_ddma_del_device(u32 devid); 358extern void au1xxx_ddma_del_device(u32 devid);
359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); 359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
360#ifdef CONFIG_PM
361void au1xxx_dbdma_suspend(void);
362void au1xxx_dbdma_resume(void);
363#endif
364
360 365
361/* 366/*
362 * Some compatibilty macros -- needed to make changes to API 367 * Some compatibilty macros -- needed to make changes to API
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..04ce6e6569da
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,78 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Cavium Networks
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
10
11#include <linux/types.h>
12#include <asm/mipsregs.h>
13
14/*
15 * Cavium Octeons are MIPS64v2 processors
16 */
17#define cpu_dcache_line_size() 128
18#define cpu_icache_line_size() 128
19
20
21#define cpu_has_4kex 1
22#define cpu_has_3k_cache 0
23#define cpu_has_4k_cache 0
24#define cpu_has_tx39_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29#define cpu_has_vce 0
30#define cpu_has_cache_cdex_p 0
31#define cpu_has_cache_cdex_s 0
32#define cpu_has_prefetch 1
33
34/*
35 * We should disable LL/SC on non SMP systems as it is faster to
36 * disable interrupts for atomic access than a LL/SC. Unfortunatly we
37 * cannot as this breaks asm/futex.h
38 */
39#define cpu_has_llsc 1
40#define cpu_has_vtag_icache 1
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_64bits 1
44#define cpu_has_octeon_cache 1
45#define cpu_has_saa octeon_has_saa()
46#define cpu_has_mips32r1 0
47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 1
50#define cpu_has_dsp 0
51#define cpu_has_mipsmt 0
52#define cpu_has_userlocal 0
53#define cpu_has_vint 0
54#define cpu_has_veic 0
55#define ARCH_HAS_READ_CURRENT_TIMER 1
56#define ARCH_HAS_IRQ_PER_CPU 1
57#define ARCH_HAS_SPINLOCK_PREFETCH 1
58#define spin_lock_prefetch(x) prefetch(x)
59#define PREFETCH_STRIDE 128
60
61static inline int read_current_timer(unsigned long *result)
62{
63 asm volatile ("rdhwr %0,$31\n"
64#ifndef CONFIG_64BIT
65 "\tsll %0, 0"
66#endif
67 : "=r" (*result));
68 return 0;
69}
70
71static inline int octeon_has_saa(void)
72{
73 int id;
74 asm volatile ("mfc0 %0, $15,0" : "=r" (id));
75 return id >= 0x000d0300;
76}
77
78#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
new file mode 100644
index 000000000000..f30fce92aabb
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 *
9 * Similar to mach-generic/dma-coherence.h except
10 * plat_device_is_coherent hard coded to return 1.
11 *
12 */
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15
16struct device;
17
18dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
19void octeon_unmap_dma_mem(struct device *, dma_addr_t);
20
21static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
22 size_t size)
23{
24 return octeon_map_dma_mem(dev, addr, size);
25}
26
27static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28 struct page *page)
29{
30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
31}
32
33static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
34{
35 return dma_addr;
36}
37
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
39{
40 octeon_unmap_dma_mem(dev, dma_addr);
41}
42
43static inline int plat_dma_supported(struct device *dev, u64 mask)
44{
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 mb();
51}
52
53static inline int plat_device_is_coherent(struct device *dev)
54{
55 return 1;
56}
57
58static inline int plat_dma_mapping_error(struct device *dev,
59 dma_addr_t dma_addr)
60{
61 return dma_addr == -1;
62}
63
64#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 000000000000..d32220fbf4f1
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,244 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __OCTEON_IRQ_H__
9#define __OCTEON_IRQ_H__
10
11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
14/* 0 - 7 represent the i8259 master */
15#define OCTEON_IRQ_I8259M0 0
16#define OCTEON_IRQ_I8259M1 1
17#define OCTEON_IRQ_I8259M2 2
18#define OCTEON_IRQ_I8259M3 3
19#define OCTEON_IRQ_I8259M4 4
20#define OCTEON_IRQ_I8259M5 5
21#define OCTEON_IRQ_I8259M6 6
22#define OCTEON_IRQ_I8259M7 7
23/* 8 - 15 represent the i8259 slave */
24#define OCTEON_IRQ_I8259S0 8
25#define OCTEON_IRQ_I8259S1 9
26#define OCTEON_IRQ_I8259S2 10
27#define OCTEON_IRQ_I8259S3 11
28#define OCTEON_IRQ_I8259S4 12
29#define OCTEON_IRQ_I8259S5 13
30#define OCTEON_IRQ_I8259S6 14
31#define OCTEON_IRQ_I8259S7 15
32/* 16 - 23 represent the 8 MIPS standard interrupt sources */
33#define OCTEON_IRQ_SW0 16
34#define OCTEON_IRQ_SW1 17
35#define OCTEON_IRQ_CIU0 18
36#define OCTEON_IRQ_CIU1 19
37#define OCTEON_IRQ_CIU4 20
38#define OCTEON_IRQ_5 21
39#define OCTEON_IRQ_PERF 22
40#define OCTEON_IRQ_TIMER 23
41/* 24 - 87 represent the sources in CIU_INTX_EN0 */
42#define OCTEON_IRQ_WORKQ0 24
43#define OCTEON_IRQ_WORKQ1 25
44#define OCTEON_IRQ_WORKQ2 26
45#define OCTEON_IRQ_WORKQ3 27
46#define OCTEON_IRQ_WORKQ4 28
47#define OCTEON_IRQ_WORKQ5 29
48#define OCTEON_IRQ_WORKQ6 30
49#define OCTEON_IRQ_WORKQ7 31
50#define OCTEON_IRQ_WORKQ8 32
51#define OCTEON_IRQ_WORKQ9 33
52#define OCTEON_IRQ_WORKQ10 34
53#define OCTEON_IRQ_WORKQ11 35
54#define OCTEON_IRQ_WORKQ12 36
55#define OCTEON_IRQ_WORKQ13 37
56#define OCTEON_IRQ_WORKQ14 38
57#define OCTEON_IRQ_WORKQ15 39
58#define OCTEON_IRQ_GPIO0 40
59#define OCTEON_IRQ_GPIO1 41
60#define OCTEON_IRQ_GPIO2 42
61#define OCTEON_IRQ_GPIO3 43
62#define OCTEON_IRQ_GPIO4 44
63#define OCTEON_IRQ_GPIO5 45
64#define OCTEON_IRQ_GPIO6 46
65#define OCTEON_IRQ_GPIO7 47
66#define OCTEON_IRQ_GPIO8 48
67#define OCTEON_IRQ_GPIO9 49
68#define OCTEON_IRQ_GPIO10 50
69#define OCTEON_IRQ_GPIO11 51
70#define OCTEON_IRQ_GPIO12 52
71#define OCTEON_IRQ_GPIO13 53
72#define OCTEON_IRQ_GPIO14 54
73#define OCTEON_IRQ_GPIO15 55
74#define OCTEON_IRQ_MBOX0 56
75#define OCTEON_IRQ_MBOX1 57
76#define OCTEON_IRQ_UART0 58
77#define OCTEON_IRQ_UART1 59
78#define OCTEON_IRQ_PCI_INT0 60
79#define OCTEON_IRQ_PCI_INT1 61
80#define OCTEON_IRQ_PCI_INT2 62
81#define OCTEON_IRQ_PCI_INT3 63
82#define OCTEON_IRQ_PCI_MSI0 64
83#define OCTEON_IRQ_PCI_MSI1 65
84#define OCTEON_IRQ_PCI_MSI2 66
85#define OCTEON_IRQ_PCI_MSI3 67
86#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
87#define OCTEON_IRQ_TWSI 69
88#define OCTEON_IRQ_RML 70
89#define OCTEON_IRQ_TRACE 71
90#define OCTEON_IRQ_GMX_DRP0 72
91#define OCTEON_IRQ_GMX_DRP1 73
92#define OCTEON_IRQ_IPD_DRP 74
93#define OCTEON_IRQ_KEY_ZERO 75
94#define OCTEON_IRQ_TIMER0 76
95#define OCTEON_IRQ_TIMER1 77
96#define OCTEON_IRQ_TIMER2 78
97#define OCTEON_IRQ_TIMER3 79
98#define OCTEON_IRQ_USB0 80
99#define OCTEON_IRQ_PCM 81
100#define OCTEON_IRQ_MPI 82
101#define OCTEON_IRQ_TWSI2 83
102#define OCTEON_IRQ_POWIQ 84
103#define OCTEON_IRQ_IPDPPTHR 85
104#define OCTEON_IRQ_MII0 86
105#define OCTEON_IRQ_BOOTDMA 87
106/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107#define OCTEON_IRQ_WDOG0 88
108#define OCTEON_IRQ_WDOG1 89
109#define OCTEON_IRQ_WDOG2 90
110#define OCTEON_IRQ_WDOG3 91
111#define OCTEON_IRQ_WDOG4 92
112#define OCTEON_IRQ_WDOG5 93
113#define OCTEON_IRQ_WDOG6 94
114#define OCTEON_IRQ_WDOG7 95
115#define OCTEON_IRQ_WDOG8 96
116#define OCTEON_IRQ_WDOG9 97
117#define OCTEON_IRQ_WDOG10 98
118#define OCTEON_IRQ_WDOG11 99
119#define OCTEON_IRQ_WDOG12 100
120#define OCTEON_IRQ_WDOG13 101
121#define OCTEON_IRQ_WDOG14 102
122#define OCTEON_IRQ_WDOG15 103
123#define OCTEON_IRQ_UART2 104
124#define OCTEON_IRQ_USB1 105
125#define OCTEON_IRQ_MII1 106
126#define OCTEON_IRQ_RESERVED107 107
127#define OCTEON_IRQ_RESERVED108 108
128#define OCTEON_IRQ_RESERVED109 109
129#define OCTEON_IRQ_RESERVED110 110
130#define OCTEON_IRQ_RESERVED111 111
131#define OCTEON_IRQ_RESERVED112 112
132#define OCTEON_IRQ_RESERVED113 113
133#define OCTEON_IRQ_RESERVED114 114
134#define OCTEON_IRQ_RESERVED115 115
135#define OCTEON_IRQ_RESERVED116 116
136#define OCTEON_IRQ_RESERVED117 117
137#define OCTEON_IRQ_RESERVED118 118
138#define OCTEON_IRQ_RESERVED119 119
139#define OCTEON_IRQ_RESERVED120 120
140#define OCTEON_IRQ_RESERVED121 121
141#define OCTEON_IRQ_RESERVED122 122
142#define OCTEON_IRQ_RESERVED123 123
143#define OCTEON_IRQ_RESERVED124 124
144#define OCTEON_IRQ_RESERVED125 125
145#define OCTEON_IRQ_RESERVED126 126
146#define OCTEON_IRQ_RESERVED127 127
147#define OCTEON_IRQ_RESERVED128 128
148#define OCTEON_IRQ_RESERVED129 129
149#define OCTEON_IRQ_RESERVED130 130
150#define OCTEON_IRQ_RESERVED131 131
151#define OCTEON_IRQ_RESERVED132 132
152#define OCTEON_IRQ_RESERVED133 133
153#define OCTEON_IRQ_RESERVED134 134
154#define OCTEON_IRQ_RESERVED135 135
155#define OCTEON_IRQ_RESERVED136 136
156#define OCTEON_IRQ_RESERVED137 137
157#define OCTEON_IRQ_RESERVED138 138
158#define OCTEON_IRQ_RESERVED139 139
159#define OCTEON_IRQ_RESERVED140 140
160#define OCTEON_IRQ_RESERVED141 141
161#define OCTEON_IRQ_RESERVED142 142
162#define OCTEON_IRQ_RESERVED143 143
163#define OCTEON_IRQ_RESERVED144 144
164#define OCTEON_IRQ_RESERVED145 145
165#define OCTEON_IRQ_RESERVED146 146
166#define OCTEON_IRQ_RESERVED147 147
167#define OCTEON_IRQ_RESERVED148 148
168#define OCTEON_IRQ_RESERVED149 149
169#define OCTEON_IRQ_RESERVED150 150
170#define OCTEON_IRQ_RESERVED151 151
171
172#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */
174#define OCTEON_IRQ_MSI_BIT0 152
175#define OCTEON_IRQ_MSI_BIT1 153
176#define OCTEON_IRQ_MSI_BIT2 154
177#define OCTEON_IRQ_MSI_BIT3 155
178#define OCTEON_IRQ_MSI_BIT4 156
179#define OCTEON_IRQ_MSI_BIT5 157
180#define OCTEON_IRQ_MSI_BIT6 158
181#define OCTEON_IRQ_MSI_BIT7 159
182#define OCTEON_IRQ_MSI_BIT8 160
183#define OCTEON_IRQ_MSI_BIT9 161
184#define OCTEON_IRQ_MSI_BIT10 162
185#define OCTEON_IRQ_MSI_BIT11 163
186#define OCTEON_IRQ_MSI_BIT12 164
187#define OCTEON_IRQ_MSI_BIT13 165
188#define OCTEON_IRQ_MSI_BIT14 166
189#define OCTEON_IRQ_MSI_BIT15 167
190#define OCTEON_IRQ_MSI_BIT16 168
191#define OCTEON_IRQ_MSI_BIT17 169
192#define OCTEON_IRQ_MSI_BIT18 170
193#define OCTEON_IRQ_MSI_BIT19 171
194#define OCTEON_IRQ_MSI_BIT20 172
195#define OCTEON_IRQ_MSI_BIT21 173
196#define OCTEON_IRQ_MSI_BIT22 174
197#define OCTEON_IRQ_MSI_BIT23 175
198#define OCTEON_IRQ_MSI_BIT24 176
199#define OCTEON_IRQ_MSI_BIT25 177
200#define OCTEON_IRQ_MSI_BIT26 178
201#define OCTEON_IRQ_MSI_BIT27 179
202#define OCTEON_IRQ_MSI_BIT28 180
203#define OCTEON_IRQ_MSI_BIT29 181
204#define OCTEON_IRQ_MSI_BIT30 182
205#define OCTEON_IRQ_MSI_BIT31 183
206#define OCTEON_IRQ_MSI_BIT32 184
207#define OCTEON_IRQ_MSI_BIT33 185
208#define OCTEON_IRQ_MSI_BIT34 186
209#define OCTEON_IRQ_MSI_BIT35 187
210#define OCTEON_IRQ_MSI_BIT36 188
211#define OCTEON_IRQ_MSI_BIT37 189
212#define OCTEON_IRQ_MSI_BIT38 190
213#define OCTEON_IRQ_MSI_BIT39 191
214#define OCTEON_IRQ_MSI_BIT40 192
215#define OCTEON_IRQ_MSI_BIT41 193
216#define OCTEON_IRQ_MSI_BIT42 194
217#define OCTEON_IRQ_MSI_BIT43 195
218#define OCTEON_IRQ_MSI_BIT44 196
219#define OCTEON_IRQ_MSI_BIT45 197
220#define OCTEON_IRQ_MSI_BIT46 198
221#define OCTEON_IRQ_MSI_BIT47 199
222#define OCTEON_IRQ_MSI_BIT48 200
223#define OCTEON_IRQ_MSI_BIT49 201
224#define OCTEON_IRQ_MSI_BIT50 202
225#define OCTEON_IRQ_MSI_BIT51 203
226#define OCTEON_IRQ_MSI_BIT52 204
227#define OCTEON_IRQ_MSI_BIT53 205
228#define OCTEON_IRQ_MSI_BIT54 206
229#define OCTEON_IRQ_MSI_BIT55 207
230#define OCTEON_IRQ_MSI_BIT56 208
231#define OCTEON_IRQ_MSI_BIT57 209
232#define OCTEON_IRQ_MSI_BIT58 210
233#define OCTEON_IRQ_MSI_BIT59 211
234#define OCTEON_IRQ_MSI_BIT60 212
235#define OCTEON_IRQ_MSI_BIT61 213
236#define OCTEON_IRQ_MSI_BIT62 214
237#define OCTEON_IRQ_MSI_BIT63 215
238
239#define OCTEON_IRQ_LAST 216
240#else
241#define OCTEON_IRQ_LAST 152
242#endif
243
244#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 000000000000..0b2b5eb22e9b
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,131 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2008 Cavium Networks, Inc
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
9#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
10
11
12#define CP0_CYCLE_COUNTER $9, 6
13#define CP0_CVMCTL_REG $9, 7
14#define CP0_CVMMEMCTL_REG $11,7
15#define CP0_PRID_REG $15, 0
16#define CP0_PRID_OCTEON_PASS1 0x000d0000
17#define CP0_PRID_OCTEON_CN30XX 0x000d0200
18
19.macro kernel_entry_setup
20 # Registers set by bootloader:
21 # (only 32 bits set by bootloader, all addresses are physical
22 # addresses, and need to have the appropriate memory region set
23 # by the kernel
24 # a0 = argc
25 # a1 = argv (kseg0 compat addr)
26 # a2 = 1 if init core, zero otherwise
27 # a3 = address of boot descriptor block
28 .set push
29 .set arch=octeon
30 # Read the cavium mem control register
31 dmfc0 v0, CP0_CVMMEMCTL_REG
32 # Clear the lower 6 bits, the CVMSEG size
33 dins v0, $0, 0, 6
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 # Disable unaligned load/store support but leave HW fixup enabled
39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001
41#else
42 # Disable unaligned load/store and HW fixup support
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
45#endif
46 # Read the processor ID register
47 mfc0 v1, CP0_PRID_REG
48 # Disable instruction prefetching (Octeon Pass1 errata)
49 or v0, v0, 0x2000
50 # Skip reenable of prefetching for Octeon Pass1
51 beq v1, CP0_PRID_OCTEON_PASS1, skip
52 nop
53 # Reenable instruction prefetching, not on Pass1
54 xor v0, v0, 0x2000
55 # Strip off pass number off of processor id
56 srl v1, 8
57 sll v1, 8
58 # CN30XX needs some extra stuff turned off for better performance
59 bne v1, CP0_PRID_OCTEON_CN30XX, skip
60 nop
61 # CN30XX Use random Icache replacement
62 or v0, v0, 0x400
63 # CN30XX Disable instruction prefetching
64 or v0, v0, 0x2000
65skip:
66 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG
68 sync
69 # Flush dcache after config change
70 cache 9, 0($0)
71 # Get my core id
72 rdhwr v0, $0
73 # Jump the master to kernel_entry
74 bne a2, zero, octeon_main_processor
75 nop
76
77#ifdef CONFIG_SMP
78
79 #
80 # All cores other than the master need to wait here for SMP bootstrap
81 # to begin
82 #
83
84 # This is the variable where the next core to boot os stored
85 PTR_LA t0, octeon_processor_boot
86octeon_spin_wait_boot:
87 # Get the core id of the next to be booted
88 LONG_L t1, (t0)
89 # Keep looping if it isn't me
90 bne t1, v0, octeon_spin_wait_boot
91 nop
92 # Get my GP from the global variable
93 PTR_LA t0, octeon_processor_gp
94 LONG_L gp, (t0)
95 # Get my SP from the global variable
96 PTR_LA t0, octeon_processor_sp
97 LONG_L sp, (t0)
98 # Set the SP global variable to zero so the master knows we've started
99 LONG_S zero, (t0)
100#ifdef __OCTEON__
101 syncw
102 syncw
103#else
104 sync
105#endif
106 # Jump to the normal Linux SMP entry point
107 j smp_bootstrap
108 nop
109#else /* CONFIG_SMP */
110
111 #
112 # Someone tried to boot SMP with a non SMP kernel. All extra cores
113 # will halt here.
114 #
115octeon_wait_forever:
116 wait
117 b octeon_wait_forever
118 nop
119
120#endif /* CONFIG_SMP */
121octeon_main_processor:
122 .set pop
123.endm
124
125/*
126 * Do SMP slave processor setup necessary before we can savely execute C code.
127 */
128 .macro smp_slave_setup
129 .endm
130
131#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
new file mode 100644
index 000000000000..c4712d7cc81d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
8 */
9#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
10#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0
25
26#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 76e04e7feb84..36c611b6c597 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -28,10 +28,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
28 return dma_addr; 28 return dma_addr;
29} 29}
30 30
31static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 31static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
32{ 32{
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37#ifdef CONFIG_DMA_COHERENT 61#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index ed7e6222dc15..4c21bfca10c3 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -38,10 +38,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
38 return dma_addr & ~(0xffUL << 56); 38 return dma_addr & ~(0xffUL << 56);
39} 39}
40 40
41static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 41static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
42{ 42{
43} 43}
44 44
45static inline int plat_dma_supported(struct device *dev, u64 mask)
46{
47 /*
48 * we fall back to GFP_DMA when the mask isn't all 1s,
49 * so we can't guarantee allocations that must be
50 * within a tighter range than GFP_DMA..
51 */
52 if (mask < DMA_BIT_MASK(24))
53 return 0;
54
55 return 1;
56}
57
58static inline void plat_extra_sync_for_device(struct device *dev)
59{
60 return;
61}
62
63static inline int plat_dma_mapping_error(struct device *dev,
64 dma_addr_t dma_addr)
65{
66 return 0;
67}
68
45static inline int plat_device_is_coherent(struct device *dev) 69static inline int plat_device_is_coherent(struct device *dev)
46{ 70{
47 return 1; /* IP27 non-cohernet mode is unsupported */ 71 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index a5511ebb2d53..7ae40f4b1c80 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -60,10 +60,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
60 return addr; 60 return addr;
61} 61}
62 62
63static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 63static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
64{ 64{
65} 65}
66 66
67static inline int plat_dma_supported(struct device *dev, u64 mask)
68{
69 /*
70 * we fall back to GFP_DMA when the mask isn't all 1s,
71 * so we can't guarantee allocations that must be
72 * within a tighter range than GFP_DMA..
73 */
74 if (mask < DMA_BIT_MASK(24))
75 return 0;
76
77 return 1;
78}
79
80static inline void plat_extra_sync_for_device(struct device *dev)
81{
82 return;
83}
84
85static inline int plat_dma_mapping_error(struct device *dev,
86 dma_addr_t dma_addr)
87{
88 return 0;
89}
90
67static inline int plat_device_is_coherent(struct device *dev) 91static inline int plat_device_is_coherent(struct device *dev)
68{ 92{
69 return 0; /* IP32 is non-cohernet */ 93 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index d66979a124a8..1c7cd27efa7b 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -27,11 +27,35 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
27 return vdma_log2phys(dma_addr); 27 return vdma_log2phys(dma_addr);
28} 28}
29 29
30static void plat_unmap_dma_mem(dma_addr_t dma_addr) 30static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
31{ 31{
32 vdma_free(dma_addr); 32 vdma_free(dma_addr);
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37 return 0; 61 return 0;
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 7e914777ebc4..38fad7dfe7da 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -30,10 +30,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
30 return dma_addr & 0x7fffffff; 30 return dma_addr & 0x7fffffff;
31} 31}
32 32
33static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 33static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
34{ 34{
35} 35}
36 36
37static inline int plat_dma_supported(struct device *dev, u64 mask)
38{
39 /*
40 * we fall back to GFP_DMA when the mask isn't all 1s,
41 * so we can't guarantee allocations that must be
42 * within a tighter range than GFP_DMA..
43 */
44 if (mask < DMA_BIT_MASK(24))
45 return 0;
46
47 return 1;
48}
49
50static inline void plat_extra_sync_for_device(struct device *dev)
51{
52 return;
53}
54
55static inline int plat_dma_mapping_error(struct device *dev,
56 dma_addr_t dma_addr)
57{
58 return 0;
59}
60
37static inline int plat_device_is_coherent(struct device *dev) 61static inline int plat_device_is_coherent(struct device *dev)
38{ 62{
39 return 0; 63 return 0;
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9316324d070d..0417516503f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1000,6 +1000,26 @@ do { \
1000#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1000#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1002 1002
1003
1004/* Cavium OCTEON (cnMIPS) */
1005#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1006#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1007
1008#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1009#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1010
1011#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1012#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1013/*
1014 * The cacheerr registers are not standardized. On OCTEON, they are
1015 * 64 bits wide.
1016 */
1017#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1018#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1019
1020#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1021#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1022
1003/* 1023/*
1004 * Macros to access the floating point coprocessor control registers 1024 * Macros to access the floating point coprocessor control registers
1005 */ 1025 */
@@ -1008,6 +1028,8 @@ do { \
1008 __asm__ __volatile__( \ 1028 __asm__ __volatile__( \
1009 ".set\tpush\n\t" \ 1029 ".set\tpush\n\t" \
1010 ".set\treorder\n\t" \ 1030 ".set\treorder\n\t" \
1031 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1032 ".set\tmips1\n\t" \
1011 "cfc1\t%0,"STR(source)"\n\t" \ 1033 "cfc1\t%0,"STR(source)"\n\t" \
1012 ".set\tpop" \ 1034 ".set\tpop" \
1013 : "=r" (__res)); \ 1035 : "=r" (__res)); \
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index e2e09b2cd265..d94085a3eafb 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr)
116#define MODULE_PROC_FAMILY "SB1 " 116#define MODULE_PROC_FAMILY "SB1 "
117#elif defined CONFIG_CPU_LOONGSON2 117#elif defined CONFIG_CPU_LOONGSON2
118#define MODULE_PROC_FAMILY "LOONGSON2 " 118#define MODULE_PROC_FAMILY "LOONGSON2 "
119#elif defined CONFIG_CPU_CAVIUM_OCTEON
120#define MODULE_PROC_FAMILY "OCTEON "
119#else 121#else
120#error MODULE_PROC_FAMILY undefined for your processor configuration 122#error MODULE_PROC_FAMILY undefined for your processor configuration
121#endif 123#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
new file mode 100644
index 000000000000..b21d3fc1ef91
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -0,0 +1,128 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This is file defines ASM primitives for the executive.
31 */
32#ifndef __CVMX_ASM_H__
33#define __CVMX_ASM_H__
34
35#include "octeon-model.h"
36
37/* other useful stuff */
38#define CVMX_SYNC asm volatile ("sync" : : : "memory")
39/* String version of SYNCW macro for using in inline asm constructs */
40#define CVMX_SYNCW_STR "syncw\nsyncw\n"
41#ifdef __OCTEON__
42
43/* Deprecated, will be removed in future release */
44#define CVMX_SYNCIO asm volatile ("nop")
45
46#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
47
48/* Deprecated, will be removed in future release */
49#define CVMX_SYNCIOALL asm volatile ("nop")
50
51/*
52 * We actually use two syncw instructions in a row when we need a write
53 * memory barrier. This is because the CN3XXX series of Octeons have
54 * errata Core-401. This can cause a single syncw to not enforce
55 * ordering under very rare conditions. Even if it is rare, better safe
56 * than sorry.
57 */
58#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
59
60/*
61 * Define new sync instructions to be normal SYNC instructions for
62 * operating systems that use threads.
63 */
64#define CVMX_SYNCWS CVMX_SYNCW
65#define CVMX_SYNCS CVMX_SYNC
66#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
67#else
68/*
69 * Not using a Cavium compiler, always use the slower sync so the
70 * assembler stays happy.
71 */
72/* Deprecated, will be removed in future release */
73#define CVMX_SYNCIO asm volatile ("nop")
74
75#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
76
77/* Deprecated, will be removed in future release */
78#define CVMX_SYNCIOALL asm volatile ("nop")
79
80#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
81#define CVMX_SYNCWS CVMX_SYNCW
82#define CVMX_SYNCS CVMX_SYNC
83#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
84#endif
85
86/*
87 * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
88 * (actually old value or zero) until that byte is stored to (by this or
89 * another processor. Note that the value of each byte is not only
90 * unpredictable, but may also change again - up until the point when one
91 * of the cores stores to the byte.
92 */
93#define CVMX_PREPARE_FOR_STORE(address, offset) \
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
95 [rbase] "d" (address))
96/*
97 * This is a command headed to the L2 controller to tell it to clear
98 * its dirty bit for a block. Basically, SW is telling HW that the
99 * current version of the block will not be used.
100 */
101#define CVMX_DONT_WRITE_BACK(address, offset) \
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
103 [rbase] "d" (address))
104
105/* flush stores, invalidate entire icache */
106#define CVMX_ICACHE_INVALIDATE \
107 { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
108
109/* flush stores, invalidate entire icache */
110#define CVMX_ICACHE_INVALIDATE2 \
111 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
112
113/* complete prefetches, invalidate entire dcache */
114#define CVMX_DCACHE_INVALIDATE \
115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
116
117
118#define CVMX_POP(result, input) \
119 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
120#define CVMX_DPOP(result, input) \
121 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
122
123/* some new cop0-like stuff */
124#define CVMX_RDHWR(result, regstr) \
125 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
126#define CVMX_RDHWRNV(result, regstr) \
127 asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
128#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
new file mode 100644
index 000000000000..692989acd8a9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -0,0 +1,262 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Header file containing the ABI with the bootloader.
30 */
31
32#ifndef __CVMX_BOOTINFO_H__
33#define __CVMX_BOOTINFO_H__
34
35/*
36 * Current major and minor versions of the CVMX bootinfo block that is
37 * passed from the bootloader to the application. This is versioned
38 * so that applications can properly handle multiple bootloader
39 * versions.
40 */
41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2
43
44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
46/*
47 * This structure is populated by the bootloader. For binary
48 * compatibility the only changes that should be made are
49 * adding members to the end of the structure, and the minor
50 * version should be incremented at that time.
51 * If an incompatible change is made, the major version
52 * must be incremented, and the minor version should be reset
53 * to 0.
54 */
55struct cvmx_bootinfo {
56 uint32_t major_version;
57 uint32_t minor_version;
58
59 uint64_t stack_top;
60 uint64_t heap_base;
61 uint64_t heap_end;
62 uint64_t desc_vaddr;
63
64 uint32_t exception_base_addr;
65 uint32_t stack_size;
66 uint32_t flags;
67 uint32_t core_mask;
68 /* DRAM size in megabytes */
69 uint32_t dram_size;
70 /* physical address of free memory descriptor block*/
71 uint32_t phy_mem_desc_addr;
72 /* used to pass flags from app to debugger */
73 uint32_t debugger_flags_base_addr;
74
75 /* CPU clock speed, in hz */
76 uint32_t eclock_hz;
77
78 /* DRAM clock speed, in hz */
79 uint32_t dclock_hz;
80
81 uint32_t reserved0;
82 uint16_t board_type;
83 uint8_t board_rev_major;
84 uint8_t board_rev_minor;
85 uint16_t reserved1;
86 uint8_t reserved2;
87 uint8_t reserved3;
88 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
89 uint8_t mac_addr_base[6];
90 uint8_t mac_addr_count;
91#if (CVMX_BOOTINFO_MIN_VER >= 1)
92 /*
93 * Several boards support compact flash on the Octeon boot
94 * bus. The CF memory spaces may be mapped to different
95 * addresses on different boards. These are the physical
96 * addresses, so care must be taken to use the correct
97 * XKPHYS/KSEG0 addressing depending on the application's
98 * ABI. These values will be 0 if CF is not present.
99 */
100 uint64_t compact_flash_common_base_addr;
101 uint64_t compact_flash_attribute_base_addr;
102 /*
103 * Base address of the LED display (as on EBT3000 board)
104 * This will be 0 if LED display not present.
105 */
106 uint64_t led_display_base_addr;
107#endif
108#if (CVMX_BOOTINFO_MIN_VER >= 2)
109 /* DFA reference clock in hz (if applicable)*/
110 uint32_t dfa_ref_clock_hz;
111
112 /*
113 * flags indicating various configuration options. These
114 * flags supercede the 'flags' variable and should be used
115 * instead if available.
116 */
117 uint32_t config_flags;
118#endif
119
120};
121
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
123#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
124#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
125#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
126/* This flag is set if the TLB mappings are not contained in the
127 * 0x10000000 - 0x20000000 boot bus region. */
128#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
129#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
130
131#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
132
133/* Type defines for board and chip types */
134enum cvmx_board_types_enum {
135 CVMX_BOARD_TYPE_NULL = 0,
136 CVMX_BOARD_TYPE_SIM = 1,
137 CVMX_BOARD_TYPE_EBT3000 = 2,
138 CVMX_BOARD_TYPE_KODAMA = 3,
139 CVMX_BOARD_TYPE_NIAGARA = 4,
140 CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
141 CVMX_BOARD_TYPE_THUNDER = 6,
142 CVMX_BOARD_TYPE_TRANTOR = 7,
143 CVMX_BOARD_TYPE_EBH3000 = 8,
144 CVMX_BOARD_TYPE_EBH3100 = 9,
145 CVMX_BOARD_TYPE_HIKARI = 10,
146 CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
147 CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
148 CVMX_BOARD_TYPE_KBP = 13,
149 /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
150 CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
151 CVMX_BOARD_TYPE_EBT5800 = 15,
152 CVMX_BOARD_TYPE_NICPRO2 = 16,
153 CVMX_BOARD_TYPE_EBH5600 = 17,
154 CVMX_BOARD_TYPE_EBH5601 = 18,
155 CVMX_BOARD_TYPE_EBH5200 = 19,
156 CVMX_BOARD_TYPE_BBGW_REF = 20,
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_MAX,
161
162 /*
163 * The range from CVMX_BOARD_TYPE_MAX to
164 * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
165 * SDK use.
166 */
167
168 /*
169 * Set aside a range for customer boards. These numbers are managed
170 * by Cavium.
171 */
172 CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
173 CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
174 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
175 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
176 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
177 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
178
179 /*
180 * Set aside a range for customer private use. The SDK won't
181 * use any numbers in this range.
182 */
183 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
184 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
185
186 /* The remaining range is reserved for future use. */
187};
188
189enum cvmx_chip_types_enum {
190 CVMX_CHIP_TYPE_NULL = 0,
191 CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
192 CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
193 CVMX_CHIP_TYPE_MAX,
194};
195
196/* Compatability alias for NAC38 name change, planned to be removed
197 * from SDK 1.7 */
198#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
199
200/* Functions to return string based on type */
201#define ENUM_BRD_TYPE_CASE(x) \
202 case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
203static inline const char *cvmx_board_type_to_string(enum
204 cvmx_board_types_enum type)
205{
206 switch (type) {
207 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
208 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
209 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
210 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
211 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
212 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
213 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
214 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
215 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
216 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
217 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
218 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
219 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
220 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
221 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
222 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
223 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
224 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
225 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
226 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
227 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232
233 /* Customer boards listed here */
234 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
240
241 /* Customer private range */
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
244 }
245 return "Unsupported Board";
246}
247
248#define ENUM_CHIP_TYPE_CASE(x) \
249 case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
250static inline const char *cvmx_chip_type_to_string(enum
251 cvmx_chip_types_enum type)
252{
253 switch (type) {
254 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
255 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
256 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
257 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
258 }
259 return "Unsupported Chip";
260}
261
262#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
new file mode 100644
index 000000000000..1cbe4b55889d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -0,0 +1,288 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#ifndef __CVMX_BOOTMEM_H__
34#define __CVMX_BOOTMEM_H__
35/* Must be multiple of 8, changing breaks ABI */
36#define CVMX_BOOTMEM_NAME_LEN 128
37
38/* Can change without breaking ABI */
39#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
40
41/* minimum alignment of bootmem alloced blocks */
42#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
43
44/* Flags for cvmx_bootmem_phy_mem* functions */
45/* Allocate from end of block instead of beginning */
46#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0)
47
48/* Don't do any locking. */
49#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1)
50
51/* First bytes of each free physical block of memory contain this structure,
52 * which is used to maintain the free memory list. Since the bootloader is
53 * only 32 bits, there is a union providing 64 and 32 bit versions. The
54 * application init code converts addresses to 64 bit addresses before the
55 * application starts.
56 */
57struct cvmx_bootmem_block_header {
58 /*
59 * Note: these are referenced from assembly routines in the
60 * bootloader, so this structure should not be changed
61 * without changing those routines as well.
62 */
63 uint64_t next_block_addr;
64 uint64_t size;
65
66};
67
68/*
69 * Structure for named memory blocks. Number of descriptors available
70 * can be changed without affecting compatiblity, but name length
71 * changes require a bump in the bootmem descriptor version Note: This
72 * structure must be naturally 64 bit aligned, as a single memory
73 * image will be used by both 32 and 64 bit programs.
74 */
75struct cvmx_bootmem_named_block_desc {
76 /* Base address of named block */
77 uint64_t base_addr;
78 /*
79 * Size actually allocated for named block (may differ from
80 * requested).
81 */
82 uint64_t size;
83 /* name of named block */
84 char name[CVMX_BOOTMEM_NAME_LEN];
85};
86
87/* Current descriptor versions */
88/* CVMX bootmem descriptor major version */
89#define CVMX_BOOTMEM_DESC_MAJ_VER 3
90
91/* CVMX bootmem descriptor minor version */
92#define CVMX_BOOTMEM_DESC_MIN_VER 0
93
94/* First three members of cvmx_bootmem_desc_t are left in original
95 * positions for backwards compatibility.
96 */
97struct cvmx_bootmem_desc {
98 /* spinlock to control access to list */
99 uint32_t lock;
100 /* flags for indicating various conditions */
101 uint32_t flags;
102 uint64_t head_addr;
103
104 /* Incremented when incompatible changes made */
105 uint32_t major_version;
106
107 /*
108 * Incremented changed when compatible changes made, reset to
109 * zero when major incremented.
110 */
111 uint32_t minor_version;
112
113 uint64_t app_data_addr;
114 uint64_t app_data_size;
115
116 /* number of elements in named blocks array */
117 uint32_t named_block_num_blocks;
118
119 /* length of name array in bootmem blocks */
120 uint32_t named_block_name_len;
121 /* address of named memory block descriptors */
122 uint64_t named_block_array_addr;
123
124};
125
126/**
127 * Initialize the boot alloc memory structures. This is
128 * normally called inside of cvmx_user_app_init()
129 *
130 * @mem_desc_ptr: Address of the free memory list
131 */
132extern int cvmx_bootmem_init(void *mem_desc_ptr);
133
134/**
135 * Allocate a block of memory from the free list that was passed
136 * to the application by the bootloader.
137 * This is an allocate-only algorithm, so freeing memory is not possible.
138 *
139 * @size: Size in bytes of block to allocate
140 * @alignment: Alignment required - must be power of 2
141 *
142 * Returns pointer to block of memory, NULL on error
143 */
144extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
145
146/**
147 * Allocate a block of memory from the free list that was
148 * passed to the application by the bootloader at a specific
149 * address. This is an allocate-only algorithm, so
150 * freeing memory is not possible. Allocation will fail if
151 * memory cannot be allocated at the specified address.
152 *
153 * @size: Size in bytes of block to allocate
154 * @address: Physical address to allocate memory at. If this memory is not
155 * available, the allocation fails.
156 * @alignment: Alignment required - must be power of 2
157 * Returns pointer to block of memory, NULL on error
158 */
159extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
160 uint64_t alignment);
161
162/**
163 * Allocate a block of memory from the free list that was
164 * passed to the application by the bootloader within a specified
165 * address range. This is an allocate-only algorithm, so
166 * freeing memory is not possible. Allocation will fail if
167 * memory cannot be allocated in the requested range.
168 *
169 * @size: Size in bytes of block to allocate
170 * @min_addr: defines the minimum address of the range
171 * @max_addr: defines the maximum address of the range
172 * @alignment: Alignment required - must be power of 2
173 * Returns pointer to block of memory, NULL on error
174 */
175extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
176 uint64_t min_addr, uint64_t max_addr);
177
178/**
179 * Frees a previously allocated named bootmem block.
180 *
181 * @name: name of block to free
182 *
183 * Returns 0 on failure,
184 * !0 on success
185 */
186extern int cvmx_bootmem_free_named(char *name);
187
188/**
189 * Finds a named bootmem block by name.
190 *
191 * @name: name of block to free
192 *
193 * Returns pointer to named block descriptor on success
194 * 0 on failure
195 */
196struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
197
198/**
199 * Allocates a block of physical memory from the free list, at
200 * (optional) requested address and alignment.
201 *
202 * @req_size: size of region to allocate. All requests are rounded up
203 * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
204 *
205 * @address_min: Minimum address that block can occupy.
206 *
207 * @address_max: Specifies the maximum address_min (inclusive) that
208 * the allocation can use.
209 *
210 * @alignment: Requested alignment of the block. If this alignment
211 * cannot be met, the allocation fails. This must be a
212 * power of 2. (Note: Alignment of
213 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
214 * internally enforced. Requested alignments of less than
215 * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
216 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
217 *
218 * @flags: Flags to control options for the allocation.
219 *
220 * Returns physical address of block allocated, or -1 on failure
221 */
222int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
223 uint64_t address_max, uint64_t alignment,
224 uint32_t flags);
225
226/**
227 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table.
229 *
230 * @name: Name of memory block to find. If NULL pointer given, then
231 * finds unused descriptor, if available.
232 *
233 * @flags: Flags to control options for the allocation.
234 *
235 * Returns Pointer to memory block descriptor, NULL if not found.
236 * If NULL returned when name parameter is NULL, then no memory
237 * block descriptors are available.
238 */
239struct cvmx_bootmem_named_block_desc *
240cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
241
242/**
243 * Frees a named block.
244 *
245 * @name: name of block to free
246 * @flags: flags for passing options
247 *
248 * Returns 0 on failure
249 * 1 on success
250 */
251int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
252
253/**
254 * Frees a block to the bootmem allocator list. This must
255 * be used with care, as the size provided must match the size
256 * of the block that was allocated, or the list will become
257 * corrupted.
258 *
259 * IMPORTANT: This is only intended to be used as part of named block
260 * frees and initial population of the free memory list.
261 * *
262 *
263 * @phy_addr: physical address of block
264 * @size: size of block in bytes.
265 * @flags: flags for passing options
266 *
267 * Returns 1 on success,
268 * 0 on failure
269 */
270int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
271
272/**
273 * Locks the bootmem allocator. This is useful in certain situations
274 * where multiple allocations must be made without being interrupted.
275 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
276 *
277 */
278void cvmx_bootmem_lock(void);
279
280/**
281 * Unlocks the bootmem allocator. This is useful in certain situations
282 * where multiple allocations must be made without being interrupted.
283 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
284 *
285 */
286void cvmx_bootmem_unlock(void);
287
288#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
new file mode 100644
index 000000000000..f8f05b7764b7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -0,0 +1,1616 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_CIU_DEFS_H__
29#define __CVMX_CIU_DEFS_H__
30
31#define CVMX_CIU_BIST \
32 CVMX_ADD_IO_SEG(0x0001070000000730ull)
33#define CVMX_CIU_DINT \
34 CVMX_ADD_IO_SEG(0x0001070000000720ull)
35#define CVMX_CIU_FUSE \
36 CVMX_ADD_IO_SEG(0x0001070000000728ull)
37#define CVMX_CIU_GSTOP \
38 CVMX_ADD_IO_SEG(0x0001070000000710ull)
39#define CVMX_CIU_INTX_EN0(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
41#define CVMX_CIU_INTX_EN0_W1C(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
43#define CVMX_CIU_INTX_EN0_W1S(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
45#define CVMX_CIU_INTX_EN1(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
47#define CVMX_CIU_INTX_EN1_W1C(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
49#define CVMX_CIU_INTX_EN1_W1S(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
51#define CVMX_CIU_INTX_EN4_0(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
53#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
55#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
57#define CVMX_CIU_INTX_EN4_1(offset) \
58 CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
59#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
60 CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
61#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
62 CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
63#define CVMX_CIU_INTX_SUM0(offset) \
64 CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
65#define CVMX_CIU_INTX_SUM4(offset) \
66 CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
67#define CVMX_CIU_INT_SUM1 \
68 CVMX_ADD_IO_SEG(0x0001070000000108ull)
69#define CVMX_CIU_MBOX_CLRX(offset) \
70 CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
71#define CVMX_CIU_MBOX_SETX(offset) \
72 CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
73#define CVMX_CIU_NMI \
74 CVMX_ADD_IO_SEG(0x0001070000000718ull)
75#define CVMX_CIU_PCI_INTA \
76 CVMX_ADD_IO_SEG(0x0001070000000750ull)
77#define CVMX_CIU_PP_DBG \
78 CVMX_ADD_IO_SEG(0x0001070000000708ull)
79#define CVMX_CIU_PP_POKEX(offset) \
80 CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
81#define CVMX_CIU_PP_RST \
82 CVMX_ADD_IO_SEG(0x0001070000000700ull)
83#define CVMX_CIU_QLM_DCOK \
84 CVMX_ADD_IO_SEG(0x0001070000000760ull)
85#define CVMX_CIU_QLM_JTGC \
86 CVMX_ADD_IO_SEG(0x0001070000000768ull)
87#define CVMX_CIU_QLM_JTGD \
88 CVMX_ADD_IO_SEG(0x0001070000000770ull)
89#define CVMX_CIU_SOFT_BIST \
90 CVMX_ADD_IO_SEG(0x0001070000000738ull)
91#define CVMX_CIU_SOFT_PRST \
92 CVMX_ADD_IO_SEG(0x0001070000000748ull)
93#define CVMX_CIU_SOFT_PRST1 \
94 CVMX_ADD_IO_SEG(0x0001070000000758ull)
95#define CVMX_CIU_SOFT_RST \
96 CVMX_ADD_IO_SEG(0x0001070000000740ull)
97#define CVMX_CIU_TIMX(offset) \
98 CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
99#define CVMX_CIU_WDOGX(offset) \
100 CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
101
102union cvmx_ciu_bist {
103 uint64_t u64;
104 struct cvmx_ciu_bist_s {
105 uint64_t reserved_4_63:60;
106 uint64_t bist:4;
107 } s;
108 struct cvmx_ciu_bist_s cn30xx;
109 struct cvmx_ciu_bist_s cn31xx;
110 struct cvmx_ciu_bist_s cn38xx;
111 struct cvmx_ciu_bist_s cn38xxp2;
112 struct cvmx_ciu_bist_cn50xx {
113 uint64_t reserved_2_63:62;
114 uint64_t bist:2;
115 } cn50xx;
116 struct cvmx_ciu_bist_cn52xx {
117 uint64_t reserved_3_63:61;
118 uint64_t bist:3;
119 } cn52xx;
120 struct cvmx_ciu_bist_cn52xx cn52xxp1;
121 struct cvmx_ciu_bist_s cn56xx;
122 struct cvmx_ciu_bist_s cn56xxp1;
123 struct cvmx_ciu_bist_s cn58xx;
124 struct cvmx_ciu_bist_s cn58xxp1;
125};
126
127union cvmx_ciu_dint {
128 uint64_t u64;
129 struct cvmx_ciu_dint_s {
130 uint64_t reserved_16_63:48;
131 uint64_t dint:16;
132 } s;
133 struct cvmx_ciu_dint_cn30xx {
134 uint64_t reserved_1_63:63;
135 uint64_t dint:1;
136 } cn30xx;
137 struct cvmx_ciu_dint_cn31xx {
138 uint64_t reserved_2_63:62;
139 uint64_t dint:2;
140 } cn31xx;
141 struct cvmx_ciu_dint_s cn38xx;
142 struct cvmx_ciu_dint_s cn38xxp2;
143 struct cvmx_ciu_dint_cn31xx cn50xx;
144 struct cvmx_ciu_dint_cn52xx {
145 uint64_t reserved_4_63:60;
146 uint64_t dint:4;
147 } cn52xx;
148 struct cvmx_ciu_dint_cn52xx cn52xxp1;
149 struct cvmx_ciu_dint_cn56xx {
150 uint64_t reserved_12_63:52;
151 uint64_t dint:12;
152 } cn56xx;
153 struct cvmx_ciu_dint_cn56xx cn56xxp1;
154 struct cvmx_ciu_dint_s cn58xx;
155 struct cvmx_ciu_dint_s cn58xxp1;
156};
157
158union cvmx_ciu_fuse {
159 uint64_t u64;
160 struct cvmx_ciu_fuse_s {
161 uint64_t reserved_16_63:48;
162 uint64_t fuse:16;
163 } s;
164 struct cvmx_ciu_fuse_cn30xx {
165 uint64_t reserved_1_63:63;
166 uint64_t fuse:1;
167 } cn30xx;
168 struct cvmx_ciu_fuse_cn31xx {
169 uint64_t reserved_2_63:62;
170 uint64_t fuse:2;
171 } cn31xx;
172 struct cvmx_ciu_fuse_s cn38xx;
173 struct cvmx_ciu_fuse_s cn38xxp2;
174 struct cvmx_ciu_fuse_cn31xx cn50xx;
175 struct cvmx_ciu_fuse_cn52xx {
176 uint64_t reserved_4_63:60;
177 uint64_t fuse:4;
178 } cn52xx;
179 struct cvmx_ciu_fuse_cn52xx cn52xxp1;
180 struct cvmx_ciu_fuse_cn56xx {
181 uint64_t reserved_12_63:52;
182 uint64_t fuse:12;
183 } cn56xx;
184 struct cvmx_ciu_fuse_cn56xx cn56xxp1;
185 struct cvmx_ciu_fuse_s cn58xx;
186 struct cvmx_ciu_fuse_s cn58xxp1;
187};
188
189union cvmx_ciu_gstop {
190 uint64_t u64;
191 struct cvmx_ciu_gstop_s {
192 uint64_t reserved_1_63:63;
193 uint64_t gstop:1;
194 } s;
195 struct cvmx_ciu_gstop_s cn30xx;
196 struct cvmx_ciu_gstop_s cn31xx;
197 struct cvmx_ciu_gstop_s cn38xx;
198 struct cvmx_ciu_gstop_s cn38xxp2;
199 struct cvmx_ciu_gstop_s cn50xx;
200 struct cvmx_ciu_gstop_s cn52xx;
201 struct cvmx_ciu_gstop_s cn52xxp1;
202 struct cvmx_ciu_gstop_s cn56xx;
203 struct cvmx_ciu_gstop_s cn56xxp1;
204 struct cvmx_ciu_gstop_s cn58xx;
205 struct cvmx_ciu_gstop_s cn58xxp1;
206};
207
208union cvmx_ciu_intx_en0 {
209 uint64_t u64;
210 struct cvmx_ciu_intx_en0_s {
211 uint64_t bootdma:1;
212 uint64_t mii:1;
213 uint64_t ipdppthr:1;
214 uint64_t powiq:1;
215 uint64_t twsi2:1;
216 uint64_t mpi:1;
217 uint64_t pcm:1;
218 uint64_t usb:1;
219 uint64_t timer:4;
220 uint64_t key_zero:1;
221 uint64_t ipd_drp:1;
222 uint64_t gmx_drp:2;
223 uint64_t trace:1;
224 uint64_t rml:1;
225 uint64_t twsi:1;
226 uint64_t reserved_44_44:1;
227 uint64_t pci_msi:4;
228 uint64_t pci_int:4;
229 uint64_t uart:2;
230 uint64_t mbox:2;
231 uint64_t gpio:16;
232 uint64_t workq:16;
233 } s;
234 struct cvmx_ciu_intx_en0_cn30xx {
235 uint64_t reserved_59_63:5;
236 uint64_t mpi:1;
237 uint64_t pcm:1;
238 uint64_t usb:1;
239 uint64_t timer:4;
240 uint64_t reserved_51_51:1;
241 uint64_t ipd_drp:1;
242 uint64_t reserved_49_49:1;
243 uint64_t gmx_drp:1;
244 uint64_t reserved_47_47:1;
245 uint64_t rml:1;
246 uint64_t twsi:1;
247 uint64_t reserved_44_44:1;
248 uint64_t pci_msi:4;
249 uint64_t pci_int:4;
250 uint64_t uart:2;
251 uint64_t mbox:2;
252 uint64_t gpio:16;
253 uint64_t workq:16;
254 } cn30xx;
255 struct cvmx_ciu_intx_en0_cn31xx {
256 uint64_t reserved_59_63:5;
257 uint64_t mpi:1;
258 uint64_t pcm:1;
259 uint64_t usb:1;
260 uint64_t timer:4;
261 uint64_t reserved_51_51:1;
262 uint64_t ipd_drp:1;
263 uint64_t reserved_49_49:1;
264 uint64_t gmx_drp:1;
265 uint64_t trace:1;
266 uint64_t rml:1;
267 uint64_t twsi:1;
268 uint64_t reserved_44_44:1;
269 uint64_t pci_msi:4;
270 uint64_t pci_int:4;
271 uint64_t uart:2;
272 uint64_t mbox:2;
273 uint64_t gpio:16;
274 uint64_t workq:16;
275 } cn31xx;
276 struct cvmx_ciu_intx_en0_cn38xx {
277 uint64_t reserved_56_63:8;
278 uint64_t timer:4;
279 uint64_t key_zero:1;
280 uint64_t ipd_drp:1;
281 uint64_t gmx_drp:2;
282 uint64_t trace:1;
283 uint64_t rml:1;
284 uint64_t twsi:1;
285 uint64_t reserved_44_44:1;
286 uint64_t pci_msi:4;
287 uint64_t pci_int:4;
288 uint64_t uart:2;
289 uint64_t mbox:2;
290 uint64_t gpio:16;
291 uint64_t workq:16;
292 } cn38xx;
293 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
294 struct cvmx_ciu_intx_en0_cn30xx cn50xx;
295 struct cvmx_ciu_intx_en0_cn52xx {
296 uint64_t bootdma:1;
297 uint64_t mii:1;
298 uint64_t ipdppthr:1;
299 uint64_t powiq:1;
300 uint64_t twsi2:1;
301 uint64_t reserved_57_58:2;
302 uint64_t usb:1;
303 uint64_t timer:4;
304 uint64_t reserved_51_51:1;
305 uint64_t ipd_drp:1;
306 uint64_t reserved_49_49:1;
307 uint64_t gmx_drp:1;
308 uint64_t trace:1;
309 uint64_t rml:1;
310 uint64_t twsi:1;
311 uint64_t reserved_44_44:1;
312 uint64_t pci_msi:4;
313 uint64_t pci_int:4;
314 uint64_t uart:2;
315 uint64_t mbox:2;
316 uint64_t gpio:16;
317 uint64_t workq:16;
318 } cn52xx;
319 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
320 struct cvmx_ciu_intx_en0_cn56xx {
321 uint64_t bootdma:1;
322 uint64_t mii:1;
323 uint64_t ipdppthr:1;
324 uint64_t powiq:1;
325 uint64_t twsi2:1;
326 uint64_t reserved_57_58:2;
327 uint64_t usb:1;
328 uint64_t timer:4;
329 uint64_t key_zero:1;
330 uint64_t ipd_drp:1;
331 uint64_t gmx_drp:2;
332 uint64_t trace:1;
333 uint64_t rml:1;
334 uint64_t twsi:1;
335 uint64_t reserved_44_44:1;
336 uint64_t pci_msi:4;
337 uint64_t pci_int:4;
338 uint64_t uart:2;
339 uint64_t mbox:2;
340 uint64_t gpio:16;
341 uint64_t workq:16;
342 } cn56xx;
343 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
344 struct cvmx_ciu_intx_en0_cn38xx cn58xx;
345 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
346};
347
348union cvmx_ciu_intx_en0_w1c {
349 uint64_t u64;
350 struct cvmx_ciu_intx_en0_w1c_s {
351 uint64_t bootdma:1;
352 uint64_t mii:1;
353 uint64_t ipdppthr:1;
354 uint64_t powiq:1;
355 uint64_t twsi2:1;
356 uint64_t reserved_57_58:2;
357 uint64_t usb:1;
358 uint64_t timer:4;
359 uint64_t key_zero:1;
360 uint64_t ipd_drp:1;
361 uint64_t gmx_drp:2;
362 uint64_t trace:1;
363 uint64_t rml:1;
364 uint64_t twsi:1;
365 uint64_t reserved_44_44:1;
366 uint64_t pci_msi:4;
367 uint64_t pci_int:4;
368 uint64_t uart:2;
369 uint64_t mbox:2;
370 uint64_t gpio:16;
371 uint64_t workq:16;
372 } s;
373 struct cvmx_ciu_intx_en0_w1c_cn52xx {
374 uint64_t bootdma:1;
375 uint64_t mii:1;
376 uint64_t ipdppthr:1;
377 uint64_t powiq:1;
378 uint64_t twsi2:1;
379 uint64_t reserved_57_58:2;
380 uint64_t usb:1;
381 uint64_t timer:4;
382 uint64_t reserved_51_51:1;
383 uint64_t ipd_drp:1;
384 uint64_t reserved_49_49:1;
385 uint64_t gmx_drp:1;
386 uint64_t trace:1;
387 uint64_t rml:1;
388 uint64_t twsi:1;
389 uint64_t reserved_44_44:1;
390 uint64_t pci_msi:4;
391 uint64_t pci_int:4;
392 uint64_t uart:2;
393 uint64_t mbox:2;
394 uint64_t gpio:16;
395 uint64_t workq:16;
396 } cn52xx;
397 struct cvmx_ciu_intx_en0_w1c_s cn56xx;
398 struct cvmx_ciu_intx_en0_w1c_cn58xx {
399 uint64_t reserved_56_63:8;
400 uint64_t timer:4;
401 uint64_t key_zero:1;
402 uint64_t ipd_drp:1;
403 uint64_t gmx_drp:2;
404 uint64_t trace:1;
405 uint64_t rml:1;
406 uint64_t twsi:1;
407 uint64_t reserved_44_44:1;
408 uint64_t pci_msi:4;
409 uint64_t pci_int:4;
410 uint64_t uart:2;
411 uint64_t mbox:2;
412 uint64_t gpio:16;
413 uint64_t workq:16;
414 } cn58xx;
415};
416
417union cvmx_ciu_intx_en0_w1s {
418 uint64_t u64;
419 struct cvmx_ciu_intx_en0_w1s_s {
420 uint64_t bootdma:1;
421 uint64_t mii:1;
422 uint64_t ipdppthr:1;
423 uint64_t powiq:1;
424 uint64_t twsi2:1;
425 uint64_t reserved_57_58:2;
426 uint64_t usb:1;
427 uint64_t timer:4;
428 uint64_t key_zero:1;
429 uint64_t ipd_drp:1;
430 uint64_t gmx_drp:2;
431 uint64_t trace:1;
432 uint64_t rml:1;
433 uint64_t twsi:1;
434 uint64_t reserved_44_44:1;
435 uint64_t pci_msi:4;
436 uint64_t pci_int:4;
437 uint64_t uart:2;
438 uint64_t mbox:2;
439 uint64_t gpio:16;
440 uint64_t workq:16;
441 } s;
442 struct cvmx_ciu_intx_en0_w1s_cn52xx {
443 uint64_t bootdma:1;
444 uint64_t mii:1;
445 uint64_t ipdppthr:1;
446 uint64_t powiq:1;
447 uint64_t twsi2:1;
448 uint64_t reserved_57_58:2;
449 uint64_t usb:1;
450 uint64_t timer:4;
451 uint64_t reserved_51_51:1;
452 uint64_t ipd_drp:1;
453 uint64_t reserved_49_49:1;
454 uint64_t gmx_drp:1;
455 uint64_t trace:1;
456 uint64_t rml:1;
457 uint64_t twsi:1;
458 uint64_t reserved_44_44:1;
459 uint64_t pci_msi:4;
460 uint64_t pci_int:4;
461 uint64_t uart:2;
462 uint64_t mbox:2;
463 uint64_t gpio:16;
464 uint64_t workq:16;
465 } cn52xx;
466 struct cvmx_ciu_intx_en0_w1s_s cn56xx;
467 struct cvmx_ciu_intx_en0_w1s_cn58xx {
468 uint64_t reserved_56_63:8;
469 uint64_t timer:4;
470 uint64_t key_zero:1;
471 uint64_t ipd_drp:1;
472 uint64_t gmx_drp:2;
473 uint64_t trace:1;
474 uint64_t rml:1;
475 uint64_t twsi:1;
476 uint64_t reserved_44_44:1;
477 uint64_t pci_msi:4;
478 uint64_t pci_int:4;
479 uint64_t uart:2;
480 uint64_t mbox:2;
481 uint64_t gpio:16;
482 uint64_t workq:16;
483 } cn58xx;
484};
485
486union cvmx_ciu_intx_en1 {
487 uint64_t u64;
488 struct cvmx_ciu_intx_en1_s {
489 uint64_t reserved_20_63:44;
490 uint64_t nand:1;
491 uint64_t mii1:1;
492 uint64_t usb1:1;
493 uint64_t uart2:1;
494 uint64_t wdog:16;
495 } s;
496 struct cvmx_ciu_intx_en1_cn30xx {
497 uint64_t reserved_1_63:63;
498 uint64_t wdog:1;
499 } cn30xx;
500 struct cvmx_ciu_intx_en1_cn31xx {
501 uint64_t reserved_2_63:62;
502 uint64_t wdog:2;
503 } cn31xx;
504 struct cvmx_ciu_intx_en1_cn38xx {
505 uint64_t reserved_16_63:48;
506 uint64_t wdog:16;
507 } cn38xx;
508 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
509 struct cvmx_ciu_intx_en1_cn31xx cn50xx;
510 struct cvmx_ciu_intx_en1_cn52xx {
511 uint64_t reserved_20_63:44;
512 uint64_t nand:1;
513 uint64_t mii1:1;
514 uint64_t usb1:1;
515 uint64_t uart2:1;
516 uint64_t reserved_4_15:12;
517 uint64_t wdog:4;
518 } cn52xx;
519 struct cvmx_ciu_intx_en1_cn52xxp1 {
520 uint64_t reserved_19_63:45;
521 uint64_t mii1:1;
522 uint64_t usb1:1;
523 uint64_t uart2:1;
524 uint64_t reserved_4_15:12;
525 uint64_t wdog:4;
526 } cn52xxp1;
527 struct cvmx_ciu_intx_en1_cn56xx {
528 uint64_t reserved_12_63:52;
529 uint64_t wdog:12;
530 } cn56xx;
531 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
532 struct cvmx_ciu_intx_en1_cn38xx cn58xx;
533 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
534};
535
536union cvmx_ciu_intx_en1_w1c {
537 uint64_t u64;
538 struct cvmx_ciu_intx_en1_w1c_s {
539 uint64_t reserved_20_63:44;
540 uint64_t nand:1;
541 uint64_t mii1:1;
542 uint64_t usb1:1;
543 uint64_t uart2:1;
544 uint64_t wdog:16;
545 } s;
546 struct cvmx_ciu_intx_en1_w1c_cn52xx {
547 uint64_t reserved_20_63:44;
548 uint64_t nand:1;
549 uint64_t mii1:1;
550 uint64_t usb1:1;
551 uint64_t uart2:1;
552 uint64_t reserved_4_15:12;
553 uint64_t wdog:4;
554 } cn52xx;
555 struct cvmx_ciu_intx_en1_w1c_cn56xx {
556 uint64_t reserved_12_63:52;
557 uint64_t wdog:12;
558 } cn56xx;
559 struct cvmx_ciu_intx_en1_w1c_cn58xx {
560 uint64_t reserved_16_63:48;
561 uint64_t wdog:16;
562 } cn58xx;
563};
564
565union cvmx_ciu_intx_en1_w1s {
566 uint64_t u64;
567 struct cvmx_ciu_intx_en1_w1s_s {
568 uint64_t reserved_20_63:44;
569 uint64_t nand:1;
570 uint64_t mii1:1;
571 uint64_t usb1:1;
572 uint64_t uart2:1;
573 uint64_t wdog:16;
574 } s;
575 struct cvmx_ciu_intx_en1_w1s_cn52xx {
576 uint64_t reserved_20_63:44;
577 uint64_t nand:1;
578 uint64_t mii1:1;
579 uint64_t usb1:1;
580 uint64_t uart2:1;
581 uint64_t reserved_4_15:12;
582 uint64_t wdog:4;
583 } cn52xx;
584 struct cvmx_ciu_intx_en1_w1s_cn56xx {
585 uint64_t reserved_12_63:52;
586 uint64_t wdog:12;
587 } cn56xx;
588 struct cvmx_ciu_intx_en1_w1s_cn58xx {
589 uint64_t reserved_16_63:48;
590 uint64_t wdog:16;
591 } cn58xx;
592};
593
594union cvmx_ciu_intx_en4_0 {
595 uint64_t u64;
596 struct cvmx_ciu_intx_en4_0_s {
597 uint64_t bootdma:1;
598 uint64_t mii:1;
599 uint64_t ipdppthr:1;
600 uint64_t powiq:1;
601 uint64_t twsi2:1;
602 uint64_t mpi:1;
603 uint64_t pcm:1;
604 uint64_t usb:1;
605 uint64_t timer:4;
606 uint64_t key_zero:1;
607 uint64_t ipd_drp:1;
608 uint64_t gmx_drp:2;
609 uint64_t trace:1;
610 uint64_t rml:1;
611 uint64_t twsi:1;
612 uint64_t reserved_44_44:1;
613 uint64_t pci_msi:4;
614 uint64_t pci_int:4;
615 uint64_t uart:2;
616 uint64_t mbox:2;
617 uint64_t gpio:16;
618 uint64_t workq:16;
619 } s;
620 struct cvmx_ciu_intx_en4_0_cn50xx {
621 uint64_t reserved_59_63:5;
622 uint64_t mpi:1;
623 uint64_t pcm:1;
624 uint64_t usb:1;
625 uint64_t timer:4;
626 uint64_t reserved_51_51:1;
627 uint64_t ipd_drp:1;
628 uint64_t reserved_49_49:1;
629 uint64_t gmx_drp:1;
630 uint64_t reserved_47_47:1;
631 uint64_t rml:1;
632 uint64_t twsi:1;
633 uint64_t reserved_44_44:1;
634 uint64_t pci_msi:4;
635 uint64_t pci_int:4;
636 uint64_t uart:2;
637 uint64_t mbox:2;
638 uint64_t gpio:16;
639 uint64_t workq:16;
640 } cn50xx;
641 struct cvmx_ciu_intx_en4_0_cn52xx {
642 uint64_t bootdma:1;
643 uint64_t mii:1;
644 uint64_t ipdppthr:1;
645 uint64_t powiq:1;
646 uint64_t twsi2:1;
647 uint64_t reserved_57_58:2;
648 uint64_t usb:1;
649 uint64_t timer:4;
650 uint64_t reserved_51_51:1;
651 uint64_t ipd_drp:1;
652 uint64_t reserved_49_49:1;
653 uint64_t gmx_drp:1;
654 uint64_t trace:1;
655 uint64_t rml:1;
656 uint64_t twsi:1;
657 uint64_t reserved_44_44:1;
658 uint64_t pci_msi:4;
659 uint64_t pci_int:4;
660 uint64_t uart:2;
661 uint64_t mbox:2;
662 uint64_t gpio:16;
663 uint64_t workq:16;
664 } cn52xx;
665 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
666 struct cvmx_ciu_intx_en4_0_cn56xx {
667 uint64_t bootdma:1;
668 uint64_t mii:1;
669 uint64_t ipdppthr:1;
670 uint64_t powiq:1;
671 uint64_t twsi2:1;
672 uint64_t reserved_57_58:2;
673 uint64_t usb:1;
674 uint64_t timer:4;
675 uint64_t key_zero:1;
676 uint64_t ipd_drp:1;
677 uint64_t gmx_drp:2;
678 uint64_t trace:1;
679 uint64_t rml:1;
680 uint64_t twsi:1;
681 uint64_t reserved_44_44:1;
682 uint64_t pci_msi:4;
683 uint64_t pci_int:4;
684 uint64_t uart:2;
685 uint64_t mbox:2;
686 uint64_t gpio:16;
687 uint64_t workq:16;
688 } cn56xx;
689 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
690 struct cvmx_ciu_intx_en4_0_cn58xx {
691 uint64_t reserved_56_63:8;
692 uint64_t timer:4;
693 uint64_t key_zero:1;
694 uint64_t ipd_drp:1;
695 uint64_t gmx_drp:2;
696 uint64_t trace:1;
697 uint64_t rml:1;
698 uint64_t twsi:1;
699 uint64_t reserved_44_44:1;
700 uint64_t pci_msi:4;
701 uint64_t pci_int:4;
702 uint64_t uart:2;
703 uint64_t mbox:2;
704 uint64_t gpio:16;
705 uint64_t workq:16;
706 } cn58xx;
707 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
708};
709
710union cvmx_ciu_intx_en4_0_w1c {
711 uint64_t u64;
712 struct cvmx_ciu_intx_en4_0_w1c_s {
713 uint64_t bootdma:1;
714 uint64_t mii:1;
715 uint64_t ipdppthr:1;
716 uint64_t powiq:1;
717 uint64_t twsi2:1;
718 uint64_t reserved_57_58:2;
719 uint64_t usb:1;
720 uint64_t timer:4;
721 uint64_t key_zero:1;
722 uint64_t ipd_drp:1;
723 uint64_t gmx_drp:2;
724 uint64_t trace:1;
725 uint64_t rml:1;
726 uint64_t twsi:1;
727 uint64_t reserved_44_44:1;
728 uint64_t pci_msi:4;
729 uint64_t pci_int:4;
730 uint64_t uart:2;
731 uint64_t mbox:2;
732 uint64_t gpio:16;
733 uint64_t workq:16;
734 } s;
735 struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
736 uint64_t bootdma:1;
737 uint64_t mii:1;
738 uint64_t ipdppthr:1;
739 uint64_t powiq:1;
740 uint64_t twsi2:1;
741 uint64_t reserved_57_58:2;
742 uint64_t usb:1;
743 uint64_t timer:4;
744 uint64_t reserved_51_51:1;
745 uint64_t ipd_drp:1;
746 uint64_t reserved_49_49:1;
747 uint64_t gmx_drp:1;
748 uint64_t trace:1;
749 uint64_t rml:1;
750 uint64_t twsi:1;
751 uint64_t reserved_44_44:1;
752 uint64_t pci_msi:4;
753 uint64_t pci_int:4;
754 uint64_t uart:2;
755 uint64_t mbox:2;
756 uint64_t gpio:16;
757 uint64_t workq:16;
758 } cn52xx;
759 struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
760 struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
761 uint64_t reserved_56_63:8;
762 uint64_t timer:4;
763 uint64_t key_zero:1;
764 uint64_t ipd_drp:1;
765 uint64_t gmx_drp:2;
766 uint64_t trace:1;
767 uint64_t rml:1;
768 uint64_t twsi:1;
769 uint64_t reserved_44_44:1;
770 uint64_t pci_msi:4;
771 uint64_t pci_int:4;
772 uint64_t uart:2;
773 uint64_t mbox:2;
774 uint64_t gpio:16;
775 uint64_t workq:16;
776 } cn58xx;
777};
778
779union cvmx_ciu_intx_en4_0_w1s {
780 uint64_t u64;
781 struct cvmx_ciu_intx_en4_0_w1s_s {
782 uint64_t bootdma:1;
783 uint64_t mii:1;
784 uint64_t ipdppthr:1;
785 uint64_t powiq:1;
786 uint64_t twsi2:1;
787 uint64_t reserved_57_58:2;
788 uint64_t usb:1;
789 uint64_t timer:4;
790 uint64_t key_zero:1;
791 uint64_t ipd_drp:1;
792 uint64_t gmx_drp:2;
793 uint64_t trace:1;
794 uint64_t rml:1;
795 uint64_t twsi:1;
796 uint64_t reserved_44_44:1;
797 uint64_t pci_msi:4;
798 uint64_t pci_int:4;
799 uint64_t uart:2;
800 uint64_t mbox:2;
801 uint64_t gpio:16;
802 uint64_t workq:16;
803 } s;
804 struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
805 uint64_t bootdma:1;
806 uint64_t mii:1;
807 uint64_t ipdppthr:1;
808 uint64_t powiq:1;
809 uint64_t twsi2:1;
810 uint64_t reserved_57_58:2;
811 uint64_t usb:1;
812 uint64_t timer:4;
813 uint64_t reserved_51_51:1;
814 uint64_t ipd_drp:1;
815 uint64_t reserved_49_49:1;
816 uint64_t gmx_drp:1;
817 uint64_t trace:1;
818 uint64_t rml:1;
819 uint64_t twsi:1;
820 uint64_t reserved_44_44:1;
821 uint64_t pci_msi:4;
822 uint64_t pci_int:4;
823 uint64_t uart:2;
824 uint64_t mbox:2;
825 uint64_t gpio:16;
826 uint64_t workq:16;
827 } cn52xx;
828 struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
829 struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
830 uint64_t reserved_56_63:8;
831 uint64_t timer:4;
832 uint64_t key_zero:1;
833 uint64_t ipd_drp:1;
834 uint64_t gmx_drp:2;
835 uint64_t trace:1;
836 uint64_t rml:1;
837 uint64_t twsi:1;
838 uint64_t reserved_44_44:1;
839 uint64_t pci_msi:4;
840 uint64_t pci_int:4;
841 uint64_t uart:2;
842 uint64_t mbox:2;
843 uint64_t gpio:16;
844 uint64_t workq:16;
845 } cn58xx;
846};
847
848union cvmx_ciu_intx_en4_1 {
849 uint64_t u64;
850 struct cvmx_ciu_intx_en4_1_s {
851 uint64_t reserved_20_63:44;
852 uint64_t nand:1;
853 uint64_t mii1:1;
854 uint64_t usb1:1;
855 uint64_t uart2:1;
856 uint64_t wdog:16;
857 } s;
858 struct cvmx_ciu_intx_en4_1_cn50xx {
859 uint64_t reserved_2_63:62;
860 uint64_t wdog:2;
861 } cn50xx;
862 struct cvmx_ciu_intx_en4_1_cn52xx {
863 uint64_t reserved_20_63:44;
864 uint64_t nand:1;
865 uint64_t mii1:1;
866 uint64_t usb1:1;
867 uint64_t uart2:1;
868 uint64_t reserved_4_15:12;
869 uint64_t wdog:4;
870 } cn52xx;
871 struct cvmx_ciu_intx_en4_1_cn52xxp1 {
872 uint64_t reserved_19_63:45;
873 uint64_t mii1:1;
874 uint64_t usb1:1;
875 uint64_t uart2:1;
876 uint64_t reserved_4_15:12;
877 uint64_t wdog:4;
878 } cn52xxp1;
879 struct cvmx_ciu_intx_en4_1_cn56xx {
880 uint64_t reserved_12_63:52;
881 uint64_t wdog:12;
882 } cn56xx;
883 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
884 struct cvmx_ciu_intx_en4_1_cn58xx {
885 uint64_t reserved_16_63:48;
886 uint64_t wdog:16;
887 } cn58xx;
888 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
889};
890
891union cvmx_ciu_intx_en4_1_w1c {
892 uint64_t u64;
893 struct cvmx_ciu_intx_en4_1_w1c_s {
894 uint64_t reserved_20_63:44;
895 uint64_t nand:1;
896 uint64_t mii1:1;
897 uint64_t usb1:1;
898 uint64_t uart2:1;
899 uint64_t wdog:16;
900 } s;
901 struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
902 uint64_t reserved_20_63:44;
903 uint64_t nand:1;
904 uint64_t mii1:1;
905 uint64_t usb1:1;
906 uint64_t uart2:1;
907 uint64_t reserved_4_15:12;
908 uint64_t wdog:4;
909 } cn52xx;
910 struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
911 uint64_t reserved_12_63:52;
912 uint64_t wdog:12;
913 } cn56xx;
914 struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
915 uint64_t reserved_16_63:48;
916 uint64_t wdog:16;
917 } cn58xx;
918};
919
920union cvmx_ciu_intx_en4_1_w1s {
921 uint64_t u64;
922 struct cvmx_ciu_intx_en4_1_w1s_s {
923 uint64_t reserved_20_63:44;
924 uint64_t nand:1;
925 uint64_t mii1:1;
926 uint64_t usb1:1;
927 uint64_t uart2:1;
928 uint64_t wdog:16;
929 } s;
930 struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
931 uint64_t reserved_20_63:44;
932 uint64_t nand:1;
933 uint64_t mii1:1;
934 uint64_t usb1:1;
935 uint64_t uart2:1;
936 uint64_t reserved_4_15:12;
937 uint64_t wdog:4;
938 } cn52xx;
939 struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
940 uint64_t reserved_12_63:52;
941 uint64_t wdog:12;
942 } cn56xx;
943 struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
944 uint64_t reserved_16_63:48;
945 uint64_t wdog:16;
946 } cn58xx;
947};
948
949union cvmx_ciu_intx_sum0 {
950 uint64_t u64;
951 struct cvmx_ciu_intx_sum0_s {
952 uint64_t bootdma:1;
953 uint64_t mii:1;
954 uint64_t ipdppthr:1;
955 uint64_t powiq:1;
956 uint64_t twsi2:1;
957 uint64_t mpi:1;
958 uint64_t pcm:1;
959 uint64_t usb:1;
960 uint64_t timer:4;
961 uint64_t key_zero:1;
962 uint64_t ipd_drp:1;
963 uint64_t gmx_drp:2;
964 uint64_t trace:1;
965 uint64_t rml:1;
966 uint64_t twsi:1;
967 uint64_t wdog_sum:1;
968 uint64_t pci_msi:4;
969 uint64_t pci_int:4;
970 uint64_t uart:2;
971 uint64_t mbox:2;
972 uint64_t gpio:16;
973 uint64_t workq:16;
974 } s;
975 struct cvmx_ciu_intx_sum0_cn30xx {
976 uint64_t reserved_59_63:5;
977 uint64_t mpi:1;
978 uint64_t pcm:1;
979 uint64_t usb:1;
980 uint64_t timer:4;
981 uint64_t reserved_51_51:1;
982 uint64_t ipd_drp:1;
983 uint64_t reserved_49_49:1;
984 uint64_t gmx_drp:1;
985 uint64_t reserved_47_47:1;
986 uint64_t rml:1;
987 uint64_t twsi:1;
988 uint64_t wdog_sum:1;
989 uint64_t pci_msi:4;
990 uint64_t pci_int:4;
991 uint64_t uart:2;
992 uint64_t mbox:2;
993 uint64_t gpio:16;
994 uint64_t workq:16;
995 } cn30xx;
996 struct cvmx_ciu_intx_sum0_cn31xx {
997 uint64_t reserved_59_63:5;
998 uint64_t mpi:1;
999 uint64_t pcm:1;
1000 uint64_t usb:1;
1001 uint64_t timer:4;
1002 uint64_t reserved_51_51:1;
1003 uint64_t ipd_drp:1;
1004 uint64_t reserved_49_49:1;
1005 uint64_t gmx_drp:1;
1006 uint64_t trace:1;
1007 uint64_t rml:1;
1008 uint64_t twsi:1;
1009 uint64_t wdog_sum:1;
1010 uint64_t pci_msi:4;
1011 uint64_t pci_int:4;
1012 uint64_t uart:2;
1013 uint64_t mbox:2;
1014 uint64_t gpio:16;
1015 uint64_t workq:16;
1016 } cn31xx;
1017 struct cvmx_ciu_intx_sum0_cn38xx {
1018 uint64_t reserved_56_63:8;
1019 uint64_t timer:4;
1020 uint64_t key_zero:1;
1021 uint64_t ipd_drp:1;
1022 uint64_t gmx_drp:2;
1023 uint64_t trace:1;
1024 uint64_t rml:1;
1025 uint64_t twsi:1;
1026 uint64_t wdog_sum:1;
1027 uint64_t pci_msi:4;
1028 uint64_t pci_int:4;
1029 uint64_t uart:2;
1030 uint64_t mbox:2;
1031 uint64_t gpio:16;
1032 uint64_t workq:16;
1033 } cn38xx;
1034 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
1035 struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
1036 struct cvmx_ciu_intx_sum0_cn52xx {
1037 uint64_t bootdma:1;
1038 uint64_t mii:1;
1039 uint64_t ipdppthr:1;
1040 uint64_t powiq:1;
1041 uint64_t twsi2:1;
1042 uint64_t reserved_57_58:2;
1043 uint64_t usb:1;
1044 uint64_t timer:4;
1045 uint64_t reserved_51_51:1;
1046 uint64_t ipd_drp:1;
1047 uint64_t reserved_49_49:1;
1048 uint64_t gmx_drp:1;
1049 uint64_t trace:1;
1050 uint64_t rml:1;
1051 uint64_t twsi:1;
1052 uint64_t wdog_sum:1;
1053 uint64_t pci_msi:4;
1054 uint64_t pci_int:4;
1055 uint64_t uart:2;
1056 uint64_t mbox:2;
1057 uint64_t gpio:16;
1058 uint64_t workq:16;
1059 } cn52xx;
1060 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
1061 struct cvmx_ciu_intx_sum0_cn56xx {
1062 uint64_t bootdma:1;
1063 uint64_t mii:1;
1064 uint64_t ipdppthr:1;
1065 uint64_t powiq:1;
1066 uint64_t twsi2:1;
1067 uint64_t reserved_57_58:2;
1068 uint64_t usb:1;
1069 uint64_t timer:4;
1070 uint64_t key_zero:1;
1071 uint64_t ipd_drp:1;
1072 uint64_t gmx_drp:2;
1073 uint64_t trace:1;
1074 uint64_t rml:1;
1075 uint64_t twsi:1;
1076 uint64_t wdog_sum:1;
1077 uint64_t pci_msi:4;
1078 uint64_t pci_int:4;
1079 uint64_t uart:2;
1080 uint64_t mbox:2;
1081 uint64_t gpio:16;
1082 uint64_t workq:16;
1083 } cn56xx;
1084 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
1085 struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
1086 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
1087};
1088
1089union cvmx_ciu_intx_sum4 {
1090 uint64_t u64;
1091 struct cvmx_ciu_intx_sum4_s {
1092 uint64_t bootdma:1;
1093 uint64_t mii:1;
1094 uint64_t ipdppthr:1;
1095 uint64_t powiq:1;
1096 uint64_t twsi2:1;
1097 uint64_t mpi:1;
1098 uint64_t pcm:1;
1099 uint64_t usb:1;
1100 uint64_t timer:4;
1101 uint64_t key_zero:1;
1102 uint64_t ipd_drp:1;
1103 uint64_t gmx_drp:2;
1104 uint64_t trace:1;
1105 uint64_t rml:1;
1106 uint64_t twsi:1;
1107 uint64_t wdog_sum:1;
1108 uint64_t pci_msi:4;
1109 uint64_t pci_int:4;
1110 uint64_t uart:2;
1111 uint64_t mbox:2;
1112 uint64_t gpio:16;
1113 uint64_t workq:16;
1114 } s;
1115 struct cvmx_ciu_intx_sum4_cn50xx {
1116 uint64_t reserved_59_63:5;
1117 uint64_t mpi:1;
1118 uint64_t pcm:1;
1119 uint64_t usb:1;
1120 uint64_t timer:4;
1121 uint64_t reserved_51_51:1;
1122 uint64_t ipd_drp:1;
1123 uint64_t reserved_49_49:1;
1124 uint64_t gmx_drp:1;
1125 uint64_t reserved_47_47:1;
1126 uint64_t rml:1;
1127 uint64_t twsi:1;
1128 uint64_t wdog_sum:1;
1129 uint64_t pci_msi:4;
1130 uint64_t pci_int:4;
1131 uint64_t uart:2;
1132 uint64_t mbox:2;
1133 uint64_t gpio:16;
1134 uint64_t workq:16;
1135 } cn50xx;
1136 struct cvmx_ciu_intx_sum4_cn52xx {
1137 uint64_t bootdma:1;
1138 uint64_t mii:1;
1139 uint64_t ipdppthr:1;
1140 uint64_t powiq:1;
1141 uint64_t twsi2:1;
1142 uint64_t reserved_57_58:2;
1143 uint64_t usb:1;
1144 uint64_t timer:4;
1145 uint64_t reserved_51_51:1;
1146 uint64_t ipd_drp:1;
1147 uint64_t reserved_49_49:1;
1148 uint64_t gmx_drp:1;
1149 uint64_t trace:1;
1150 uint64_t rml:1;
1151 uint64_t twsi:1;
1152 uint64_t wdog_sum:1;
1153 uint64_t pci_msi:4;
1154 uint64_t pci_int:4;
1155 uint64_t uart:2;
1156 uint64_t mbox:2;
1157 uint64_t gpio:16;
1158 uint64_t workq:16;
1159 } cn52xx;
1160 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
1161 struct cvmx_ciu_intx_sum4_cn56xx {
1162 uint64_t bootdma:1;
1163 uint64_t mii:1;
1164 uint64_t ipdppthr:1;
1165 uint64_t powiq:1;
1166 uint64_t twsi2:1;
1167 uint64_t reserved_57_58:2;
1168 uint64_t usb:1;
1169 uint64_t timer:4;
1170 uint64_t key_zero:1;
1171 uint64_t ipd_drp:1;
1172 uint64_t gmx_drp:2;
1173 uint64_t trace:1;
1174 uint64_t rml:1;
1175 uint64_t twsi:1;
1176 uint64_t wdog_sum:1;
1177 uint64_t pci_msi:4;
1178 uint64_t pci_int:4;
1179 uint64_t uart:2;
1180 uint64_t mbox:2;
1181 uint64_t gpio:16;
1182 uint64_t workq:16;
1183 } cn56xx;
1184 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
1185 struct cvmx_ciu_intx_sum4_cn58xx {
1186 uint64_t reserved_56_63:8;
1187 uint64_t timer:4;
1188 uint64_t key_zero:1;
1189 uint64_t ipd_drp:1;
1190 uint64_t gmx_drp:2;
1191 uint64_t trace:1;
1192 uint64_t rml:1;
1193 uint64_t twsi:1;
1194 uint64_t wdog_sum:1;
1195 uint64_t pci_msi:4;
1196 uint64_t pci_int:4;
1197 uint64_t uart:2;
1198 uint64_t mbox:2;
1199 uint64_t gpio:16;
1200 uint64_t workq:16;
1201 } cn58xx;
1202 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
1203};
1204
1205union cvmx_ciu_int_sum1 {
1206 uint64_t u64;
1207 struct cvmx_ciu_int_sum1_s {
1208 uint64_t reserved_20_63:44;
1209 uint64_t nand:1;
1210 uint64_t mii1:1;
1211 uint64_t usb1:1;
1212 uint64_t uart2:1;
1213 uint64_t wdog:16;
1214 } s;
1215 struct cvmx_ciu_int_sum1_cn30xx {
1216 uint64_t reserved_1_63:63;
1217 uint64_t wdog:1;
1218 } cn30xx;
1219 struct cvmx_ciu_int_sum1_cn31xx {
1220 uint64_t reserved_2_63:62;
1221 uint64_t wdog:2;
1222 } cn31xx;
1223 struct cvmx_ciu_int_sum1_cn38xx {
1224 uint64_t reserved_16_63:48;
1225 uint64_t wdog:16;
1226 } cn38xx;
1227 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
1228 struct cvmx_ciu_int_sum1_cn31xx cn50xx;
1229 struct cvmx_ciu_int_sum1_cn52xx {
1230 uint64_t reserved_20_63:44;
1231 uint64_t nand:1;
1232 uint64_t mii1:1;
1233 uint64_t usb1:1;
1234 uint64_t uart2:1;
1235 uint64_t reserved_4_15:12;
1236 uint64_t wdog:4;
1237 } cn52xx;
1238 struct cvmx_ciu_int_sum1_cn52xxp1 {
1239 uint64_t reserved_19_63:45;
1240 uint64_t mii1:1;
1241 uint64_t usb1:1;
1242 uint64_t uart2:1;
1243 uint64_t reserved_4_15:12;
1244 uint64_t wdog:4;
1245 } cn52xxp1;
1246 struct cvmx_ciu_int_sum1_cn56xx {
1247 uint64_t reserved_12_63:52;
1248 uint64_t wdog:12;
1249 } cn56xx;
1250 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
1251 struct cvmx_ciu_int_sum1_cn38xx cn58xx;
1252 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
1253};
1254
1255union cvmx_ciu_mbox_clrx {
1256 uint64_t u64;
1257 struct cvmx_ciu_mbox_clrx_s {
1258 uint64_t reserved_32_63:32;
1259 uint64_t bits:32;
1260 } s;
1261 struct cvmx_ciu_mbox_clrx_s cn30xx;
1262 struct cvmx_ciu_mbox_clrx_s cn31xx;
1263 struct cvmx_ciu_mbox_clrx_s cn38xx;
1264 struct cvmx_ciu_mbox_clrx_s cn38xxp2;
1265 struct cvmx_ciu_mbox_clrx_s cn50xx;
1266 struct cvmx_ciu_mbox_clrx_s cn52xx;
1267 struct cvmx_ciu_mbox_clrx_s cn52xxp1;
1268 struct cvmx_ciu_mbox_clrx_s cn56xx;
1269 struct cvmx_ciu_mbox_clrx_s cn56xxp1;
1270 struct cvmx_ciu_mbox_clrx_s cn58xx;
1271 struct cvmx_ciu_mbox_clrx_s cn58xxp1;
1272};
1273
1274union cvmx_ciu_mbox_setx {
1275 uint64_t u64;
1276 struct cvmx_ciu_mbox_setx_s {
1277 uint64_t reserved_32_63:32;
1278 uint64_t bits:32;
1279 } s;
1280 struct cvmx_ciu_mbox_setx_s cn30xx;
1281 struct cvmx_ciu_mbox_setx_s cn31xx;
1282 struct cvmx_ciu_mbox_setx_s cn38xx;
1283 struct cvmx_ciu_mbox_setx_s cn38xxp2;
1284 struct cvmx_ciu_mbox_setx_s cn50xx;
1285 struct cvmx_ciu_mbox_setx_s cn52xx;
1286 struct cvmx_ciu_mbox_setx_s cn52xxp1;
1287 struct cvmx_ciu_mbox_setx_s cn56xx;
1288 struct cvmx_ciu_mbox_setx_s cn56xxp1;
1289 struct cvmx_ciu_mbox_setx_s cn58xx;
1290 struct cvmx_ciu_mbox_setx_s cn58xxp1;
1291};
1292
1293union cvmx_ciu_nmi {
1294 uint64_t u64;
1295 struct cvmx_ciu_nmi_s {
1296 uint64_t reserved_16_63:48;
1297 uint64_t nmi:16;
1298 } s;
1299 struct cvmx_ciu_nmi_cn30xx {
1300 uint64_t reserved_1_63:63;
1301 uint64_t nmi:1;
1302 } cn30xx;
1303 struct cvmx_ciu_nmi_cn31xx {
1304 uint64_t reserved_2_63:62;
1305 uint64_t nmi:2;
1306 } cn31xx;
1307 struct cvmx_ciu_nmi_s cn38xx;
1308 struct cvmx_ciu_nmi_s cn38xxp2;
1309 struct cvmx_ciu_nmi_cn31xx cn50xx;
1310 struct cvmx_ciu_nmi_cn52xx {
1311 uint64_t reserved_4_63:60;
1312 uint64_t nmi:4;
1313 } cn52xx;
1314 struct cvmx_ciu_nmi_cn52xx cn52xxp1;
1315 struct cvmx_ciu_nmi_cn56xx {
1316 uint64_t reserved_12_63:52;
1317 uint64_t nmi:12;
1318 } cn56xx;
1319 struct cvmx_ciu_nmi_cn56xx cn56xxp1;
1320 struct cvmx_ciu_nmi_s cn58xx;
1321 struct cvmx_ciu_nmi_s cn58xxp1;
1322};
1323
1324union cvmx_ciu_pci_inta {
1325 uint64_t u64;
1326 struct cvmx_ciu_pci_inta_s {
1327 uint64_t reserved_2_63:62;
1328 uint64_t intr:2;
1329 } s;
1330 struct cvmx_ciu_pci_inta_s cn30xx;
1331 struct cvmx_ciu_pci_inta_s cn31xx;
1332 struct cvmx_ciu_pci_inta_s cn38xx;
1333 struct cvmx_ciu_pci_inta_s cn38xxp2;
1334 struct cvmx_ciu_pci_inta_s cn50xx;
1335 struct cvmx_ciu_pci_inta_s cn52xx;
1336 struct cvmx_ciu_pci_inta_s cn52xxp1;
1337 struct cvmx_ciu_pci_inta_s cn56xx;
1338 struct cvmx_ciu_pci_inta_s cn56xxp1;
1339 struct cvmx_ciu_pci_inta_s cn58xx;
1340 struct cvmx_ciu_pci_inta_s cn58xxp1;
1341};
1342
1343union cvmx_ciu_pp_dbg {
1344 uint64_t u64;
1345 struct cvmx_ciu_pp_dbg_s {
1346 uint64_t reserved_16_63:48;
1347 uint64_t ppdbg:16;
1348 } s;
1349 struct cvmx_ciu_pp_dbg_cn30xx {
1350 uint64_t reserved_1_63:63;
1351 uint64_t ppdbg:1;
1352 } cn30xx;
1353 struct cvmx_ciu_pp_dbg_cn31xx {
1354 uint64_t reserved_2_63:62;
1355 uint64_t ppdbg:2;
1356 } cn31xx;
1357 struct cvmx_ciu_pp_dbg_s cn38xx;
1358 struct cvmx_ciu_pp_dbg_s cn38xxp2;
1359 struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
1360 struct cvmx_ciu_pp_dbg_cn52xx {
1361 uint64_t reserved_4_63:60;
1362 uint64_t ppdbg:4;
1363 } cn52xx;
1364 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
1365 struct cvmx_ciu_pp_dbg_cn56xx {
1366 uint64_t reserved_12_63:52;
1367 uint64_t ppdbg:12;
1368 } cn56xx;
1369 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
1370 struct cvmx_ciu_pp_dbg_s cn58xx;
1371 struct cvmx_ciu_pp_dbg_s cn58xxp1;
1372};
1373
1374union cvmx_ciu_pp_pokex {
1375 uint64_t u64;
1376 struct cvmx_ciu_pp_pokex_s {
1377 uint64_t reserved_0_63:64;
1378 } s;
1379 struct cvmx_ciu_pp_pokex_s cn30xx;
1380 struct cvmx_ciu_pp_pokex_s cn31xx;
1381 struct cvmx_ciu_pp_pokex_s cn38xx;
1382 struct cvmx_ciu_pp_pokex_s cn38xxp2;
1383 struct cvmx_ciu_pp_pokex_s cn50xx;
1384 struct cvmx_ciu_pp_pokex_s cn52xx;
1385 struct cvmx_ciu_pp_pokex_s cn52xxp1;
1386 struct cvmx_ciu_pp_pokex_s cn56xx;
1387 struct cvmx_ciu_pp_pokex_s cn56xxp1;
1388 struct cvmx_ciu_pp_pokex_s cn58xx;
1389 struct cvmx_ciu_pp_pokex_s cn58xxp1;
1390};
1391
1392union cvmx_ciu_pp_rst {
1393 uint64_t u64;
1394 struct cvmx_ciu_pp_rst_s {
1395 uint64_t reserved_16_63:48;
1396 uint64_t rst:15;
1397 uint64_t rst0:1;
1398 } s;
1399 struct cvmx_ciu_pp_rst_cn30xx {
1400 uint64_t reserved_1_63:63;
1401 uint64_t rst0:1;
1402 } cn30xx;
1403 struct cvmx_ciu_pp_rst_cn31xx {
1404 uint64_t reserved_2_63:62;
1405 uint64_t rst:1;
1406 uint64_t rst0:1;
1407 } cn31xx;
1408 struct cvmx_ciu_pp_rst_s cn38xx;
1409 struct cvmx_ciu_pp_rst_s cn38xxp2;
1410 struct cvmx_ciu_pp_rst_cn31xx cn50xx;
1411 struct cvmx_ciu_pp_rst_cn52xx {
1412 uint64_t reserved_4_63:60;
1413 uint64_t rst:3;
1414 uint64_t rst0:1;
1415 } cn52xx;
1416 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
1417 struct cvmx_ciu_pp_rst_cn56xx {
1418 uint64_t reserved_12_63:52;
1419 uint64_t rst:11;
1420 uint64_t rst0:1;
1421 } cn56xx;
1422 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
1423 struct cvmx_ciu_pp_rst_s cn58xx;
1424 struct cvmx_ciu_pp_rst_s cn58xxp1;
1425};
1426
1427union cvmx_ciu_qlm_dcok {
1428 uint64_t u64;
1429 struct cvmx_ciu_qlm_dcok_s {
1430 uint64_t reserved_4_63:60;
1431 uint64_t qlm_dcok:4;
1432 } s;
1433 struct cvmx_ciu_qlm_dcok_cn52xx {
1434 uint64_t reserved_2_63:62;
1435 uint64_t qlm_dcok:2;
1436 } cn52xx;
1437 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
1438 struct cvmx_ciu_qlm_dcok_s cn56xx;
1439 struct cvmx_ciu_qlm_dcok_s cn56xxp1;
1440};
1441
1442union cvmx_ciu_qlm_jtgc {
1443 uint64_t u64;
1444 struct cvmx_ciu_qlm_jtgc_s {
1445 uint64_t reserved_11_63:53;
1446 uint64_t clk_div:3;
1447 uint64_t reserved_6_7:2;
1448 uint64_t mux_sel:2;
1449 uint64_t bypass:4;
1450 } s;
1451 struct cvmx_ciu_qlm_jtgc_cn52xx {
1452 uint64_t reserved_11_63:53;
1453 uint64_t clk_div:3;
1454 uint64_t reserved_5_7:3;
1455 uint64_t mux_sel:1;
1456 uint64_t reserved_2_3:2;
1457 uint64_t bypass:2;
1458 } cn52xx;
1459 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
1460 struct cvmx_ciu_qlm_jtgc_s cn56xx;
1461 struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
1462};
1463
1464union cvmx_ciu_qlm_jtgd {
1465 uint64_t u64;
1466 struct cvmx_ciu_qlm_jtgd_s {
1467 uint64_t capture:1;
1468 uint64_t shift:1;
1469 uint64_t update:1;
1470 uint64_t reserved_44_60:17;
1471 uint64_t select:4;
1472 uint64_t reserved_37_39:3;
1473 uint64_t shft_cnt:5;
1474 uint64_t shft_reg:32;
1475 } s;
1476 struct cvmx_ciu_qlm_jtgd_cn52xx {
1477 uint64_t capture:1;
1478 uint64_t shift:1;
1479 uint64_t update:1;
1480 uint64_t reserved_42_60:19;
1481 uint64_t select:2;
1482 uint64_t reserved_37_39:3;
1483 uint64_t shft_cnt:5;
1484 uint64_t shft_reg:32;
1485 } cn52xx;
1486 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
1487 struct cvmx_ciu_qlm_jtgd_s cn56xx;
1488 struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
1489 uint64_t capture:1;
1490 uint64_t shift:1;
1491 uint64_t update:1;
1492 uint64_t reserved_37_60:24;
1493 uint64_t shft_cnt:5;
1494 uint64_t shft_reg:32;
1495 } cn56xxp1;
1496};
1497
1498union cvmx_ciu_soft_bist {
1499 uint64_t u64;
1500 struct cvmx_ciu_soft_bist_s {
1501 uint64_t reserved_1_63:63;
1502 uint64_t soft_bist:1;
1503 } s;
1504 struct cvmx_ciu_soft_bist_s cn30xx;
1505 struct cvmx_ciu_soft_bist_s cn31xx;
1506 struct cvmx_ciu_soft_bist_s cn38xx;
1507 struct cvmx_ciu_soft_bist_s cn38xxp2;
1508 struct cvmx_ciu_soft_bist_s cn50xx;
1509 struct cvmx_ciu_soft_bist_s cn52xx;
1510 struct cvmx_ciu_soft_bist_s cn52xxp1;
1511 struct cvmx_ciu_soft_bist_s cn56xx;
1512 struct cvmx_ciu_soft_bist_s cn56xxp1;
1513 struct cvmx_ciu_soft_bist_s cn58xx;
1514 struct cvmx_ciu_soft_bist_s cn58xxp1;
1515};
1516
1517union cvmx_ciu_soft_prst {
1518 uint64_t u64;
1519 struct cvmx_ciu_soft_prst_s {
1520 uint64_t reserved_3_63:61;
1521 uint64_t host64:1;
1522 uint64_t npi:1;
1523 uint64_t soft_prst:1;
1524 } s;
1525 struct cvmx_ciu_soft_prst_s cn30xx;
1526 struct cvmx_ciu_soft_prst_s cn31xx;
1527 struct cvmx_ciu_soft_prst_s cn38xx;
1528 struct cvmx_ciu_soft_prst_s cn38xxp2;
1529 struct cvmx_ciu_soft_prst_s cn50xx;
1530 struct cvmx_ciu_soft_prst_cn52xx {
1531 uint64_t reserved_1_63:63;
1532 uint64_t soft_prst:1;
1533 } cn52xx;
1534 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
1535 struct cvmx_ciu_soft_prst_cn52xx cn56xx;
1536 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
1537 struct cvmx_ciu_soft_prst_s cn58xx;
1538 struct cvmx_ciu_soft_prst_s cn58xxp1;
1539};
1540
1541union cvmx_ciu_soft_prst1 {
1542 uint64_t u64;
1543 struct cvmx_ciu_soft_prst1_s {
1544 uint64_t reserved_1_63:63;
1545 uint64_t soft_prst:1;
1546 } s;
1547 struct cvmx_ciu_soft_prst1_s cn52xx;
1548 struct cvmx_ciu_soft_prst1_s cn52xxp1;
1549 struct cvmx_ciu_soft_prst1_s cn56xx;
1550 struct cvmx_ciu_soft_prst1_s cn56xxp1;
1551};
1552
1553union cvmx_ciu_soft_rst {
1554 uint64_t u64;
1555 struct cvmx_ciu_soft_rst_s {
1556 uint64_t reserved_1_63:63;
1557 uint64_t soft_rst:1;
1558 } s;
1559 struct cvmx_ciu_soft_rst_s cn30xx;
1560 struct cvmx_ciu_soft_rst_s cn31xx;
1561 struct cvmx_ciu_soft_rst_s cn38xx;
1562 struct cvmx_ciu_soft_rst_s cn38xxp2;
1563 struct cvmx_ciu_soft_rst_s cn50xx;
1564 struct cvmx_ciu_soft_rst_s cn52xx;
1565 struct cvmx_ciu_soft_rst_s cn52xxp1;
1566 struct cvmx_ciu_soft_rst_s cn56xx;
1567 struct cvmx_ciu_soft_rst_s cn56xxp1;
1568 struct cvmx_ciu_soft_rst_s cn58xx;
1569 struct cvmx_ciu_soft_rst_s cn58xxp1;
1570};
1571
1572union cvmx_ciu_timx {
1573 uint64_t u64;
1574 struct cvmx_ciu_timx_s {
1575 uint64_t reserved_37_63:27;
1576 uint64_t one_shot:1;
1577 uint64_t len:36;
1578 } s;
1579 struct cvmx_ciu_timx_s cn30xx;
1580 struct cvmx_ciu_timx_s cn31xx;
1581 struct cvmx_ciu_timx_s cn38xx;
1582 struct cvmx_ciu_timx_s cn38xxp2;
1583 struct cvmx_ciu_timx_s cn50xx;
1584 struct cvmx_ciu_timx_s cn52xx;
1585 struct cvmx_ciu_timx_s cn52xxp1;
1586 struct cvmx_ciu_timx_s cn56xx;
1587 struct cvmx_ciu_timx_s cn56xxp1;
1588 struct cvmx_ciu_timx_s cn58xx;
1589 struct cvmx_ciu_timx_s cn58xxp1;
1590};
1591
1592union cvmx_ciu_wdogx {
1593 uint64_t u64;
1594 struct cvmx_ciu_wdogx_s {
1595 uint64_t reserved_46_63:18;
1596 uint64_t gstopen:1;
1597 uint64_t dstop:1;
1598 uint64_t cnt:24;
1599 uint64_t len:16;
1600 uint64_t state:2;
1601 uint64_t mode:2;
1602 } s;
1603 struct cvmx_ciu_wdogx_s cn30xx;
1604 struct cvmx_ciu_wdogx_s cn31xx;
1605 struct cvmx_ciu_wdogx_s cn38xx;
1606 struct cvmx_ciu_wdogx_s cn38xxp2;
1607 struct cvmx_ciu_wdogx_s cn50xx;
1608 struct cvmx_ciu_wdogx_s cn52xx;
1609 struct cvmx_ciu_wdogx_s cn52xxp1;
1610 struct cvmx_ciu_wdogx_s cn56xx;
1611 struct cvmx_ciu_wdogx_s cn56xxp1;
1612 struct cvmx_ciu_wdogx_s cn58xx;
1613 struct cvmx_ciu_wdogx_s cn58xxp1;
1614};
1615
1616#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
new file mode 100644
index 000000000000..5fdd6ba48a05
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -0,0 +1,219 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GPIO_DEFS_H__
29#define __CVMX_GPIO_DEFS_H__
30
31#define CVMX_GPIO_BIT_CFGX(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
33#define CVMX_GPIO_BOOT_ENA \
34 CVMX_ADD_IO_SEG(0x00010700000008A8ull)
35#define CVMX_GPIO_CLK_GENX(offset) \
36 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
37#define CVMX_GPIO_DBG_ENA \
38 CVMX_ADD_IO_SEG(0x00010700000008A0ull)
39#define CVMX_GPIO_INT_CLR \
40 CVMX_ADD_IO_SEG(0x0001070000000898ull)
41#define CVMX_GPIO_RX_DAT \
42 CVMX_ADD_IO_SEG(0x0001070000000880ull)
43#define CVMX_GPIO_TX_CLR \
44 CVMX_ADD_IO_SEG(0x0001070000000890ull)
45#define CVMX_GPIO_TX_SET \
46 CVMX_ADD_IO_SEG(0x0001070000000888ull)
47#define CVMX_GPIO_XBIT_CFGX(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
49
50union cvmx_gpio_bit_cfgx {
51 uint64_t u64;
52 struct cvmx_gpio_bit_cfgx_s {
53 uint64_t reserved_15_63:49;
54 uint64_t clk_gen:1;
55 uint64_t clk_sel:2;
56 uint64_t fil_sel:4;
57 uint64_t fil_cnt:4;
58 uint64_t int_type:1;
59 uint64_t int_en:1;
60 uint64_t rx_xor:1;
61 uint64_t tx_oe:1;
62 } s;
63 struct cvmx_gpio_bit_cfgx_cn30xx {
64 uint64_t reserved_12_63:52;
65 uint64_t fil_sel:4;
66 uint64_t fil_cnt:4;
67 uint64_t int_type:1;
68 uint64_t int_en:1;
69 uint64_t rx_xor:1;
70 uint64_t tx_oe:1;
71 } cn30xx;
72 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
73 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
74 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
75 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
76 struct cvmx_gpio_bit_cfgx_s cn52xx;
77 struct cvmx_gpio_bit_cfgx_s cn52xxp1;
78 struct cvmx_gpio_bit_cfgx_s cn56xx;
79 struct cvmx_gpio_bit_cfgx_s cn56xxp1;
80 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
81 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
82};
83
84union cvmx_gpio_boot_ena {
85 uint64_t u64;
86 struct cvmx_gpio_boot_ena_s {
87 uint64_t reserved_12_63:52;
88 uint64_t boot_ena:4;
89 uint64_t reserved_0_7:8;
90 } s;
91 struct cvmx_gpio_boot_ena_s cn30xx;
92 struct cvmx_gpio_boot_ena_s cn31xx;
93 struct cvmx_gpio_boot_ena_s cn50xx;
94};
95
96union cvmx_gpio_clk_genx {
97 uint64_t u64;
98 struct cvmx_gpio_clk_genx_s {
99 uint64_t reserved_32_63:32;
100 uint64_t n:32;
101 } s;
102 struct cvmx_gpio_clk_genx_s cn52xx;
103 struct cvmx_gpio_clk_genx_s cn52xxp1;
104 struct cvmx_gpio_clk_genx_s cn56xx;
105 struct cvmx_gpio_clk_genx_s cn56xxp1;
106};
107
108union cvmx_gpio_dbg_ena {
109 uint64_t u64;
110 struct cvmx_gpio_dbg_ena_s {
111 uint64_t reserved_21_63:43;
112 uint64_t dbg_ena:21;
113 } s;
114 struct cvmx_gpio_dbg_ena_s cn30xx;
115 struct cvmx_gpio_dbg_ena_s cn31xx;
116 struct cvmx_gpio_dbg_ena_s cn50xx;
117};
118
119union cvmx_gpio_int_clr {
120 uint64_t u64;
121 struct cvmx_gpio_int_clr_s {
122 uint64_t reserved_16_63:48;
123 uint64_t type:16;
124 } s;
125 struct cvmx_gpio_int_clr_s cn30xx;
126 struct cvmx_gpio_int_clr_s cn31xx;
127 struct cvmx_gpio_int_clr_s cn38xx;
128 struct cvmx_gpio_int_clr_s cn38xxp2;
129 struct cvmx_gpio_int_clr_s cn50xx;
130 struct cvmx_gpio_int_clr_s cn52xx;
131 struct cvmx_gpio_int_clr_s cn52xxp1;
132 struct cvmx_gpio_int_clr_s cn56xx;
133 struct cvmx_gpio_int_clr_s cn56xxp1;
134 struct cvmx_gpio_int_clr_s cn58xx;
135 struct cvmx_gpio_int_clr_s cn58xxp1;
136};
137
138union cvmx_gpio_rx_dat {
139 uint64_t u64;
140 struct cvmx_gpio_rx_dat_s {
141 uint64_t reserved_24_63:40;
142 uint64_t dat:24;
143 } s;
144 struct cvmx_gpio_rx_dat_s cn30xx;
145 struct cvmx_gpio_rx_dat_s cn31xx;
146 struct cvmx_gpio_rx_dat_cn38xx {
147 uint64_t reserved_16_63:48;
148 uint64_t dat:16;
149 } cn38xx;
150 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
151 struct cvmx_gpio_rx_dat_s cn50xx;
152 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
153 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
154 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
155 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
156 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
157 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
158};
159
160union cvmx_gpio_tx_clr {
161 uint64_t u64;
162 struct cvmx_gpio_tx_clr_s {
163 uint64_t reserved_24_63:40;
164 uint64_t clr:24;
165 } s;
166 struct cvmx_gpio_tx_clr_s cn30xx;
167 struct cvmx_gpio_tx_clr_s cn31xx;
168 struct cvmx_gpio_tx_clr_cn38xx {
169 uint64_t reserved_16_63:48;
170 uint64_t clr:16;
171 } cn38xx;
172 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
173 struct cvmx_gpio_tx_clr_s cn50xx;
174 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
175 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
176 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
177 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
178 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
179 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
180};
181
182union cvmx_gpio_tx_set {
183 uint64_t u64;
184 struct cvmx_gpio_tx_set_s {
185 uint64_t reserved_24_63:40;
186 uint64_t set:24;
187 } s;
188 struct cvmx_gpio_tx_set_s cn30xx;
189 struct cvmx_gpio_tx_set_s cn31xx;
190 struct cvmx_gpio_tx_set_cn38xx {
191 uint64_t reserved_16_63:48;
192 uint64_t set:16;
193 } cn38xx;
194 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
195 struct cvmx_gpio_tx_set_s cn50xx;
196 struct cvmx_gpio_tx_set_cn38xx cn52xx;
197 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
198 struct cvmx_gpio_tx_set_cn38xx cn56xx;
199 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
200 struct cvmx_gpio_tx_set_cn38xx cn58xx;
201 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
202};
203
204union cvmx_gpio_xbit_cfgx {
205 uint64_t u64;
206 struct cvmx_gpio_xbit_cfgx_s {
207 uint64_t reserved_12_63:52;
208 uint64_t fil_sel:4;
209 uint64_t fil_cnt:4;
210 uint64_t reserved_2_3:2;
211 uint64_t rx_xor:1;
212 uint64_t tx_oe:1;
213 } s;
214 struct cvmx_gpio_xbit_cfgx_s cn30xx;
215 struct cvmx_gpio_xbit_cfgx_s cn31xx;
216 struct cvmx_gpio_xbit_cfgx_s cn50xx;
217};
218
219#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
new file mode 100644
index 000000000000..0ee36baec500
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -0,0 +1,530 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IOB_DEFS_H__
29#define __CVMX_IOB_DEFS_H__
30
31#define CVMX_IOB_BIST_STATUS \
32 CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
33#define CVMX_IOB_CTL_STATUS \
34 CVMX_ADD_IO_SEG(0x00011800F0000050ull)
35#define CVMX_IOB_DWB_PRI_CNT \
36 CVMX_ADD_IO_SEG(0x00011800F0000028ull)
37#define CVMX_IOB_FAU_TIMEOUT \
38 CVMX_ADD_IO_SEG(0x00011800F0000000ull)
39#define CVMX_IOB_I2C_PRI_CNT \
40 CVMX_ADD_IO_SEG(0x00011800F0000010ull)
41#define CVMX_IOB_INB_CONTROL_MATCH \
42 CVMX_ADD_IO_SEG(0x00011800F0000078ull)
43#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
44 CVMX_ADD_IO_SEG(0x00011800F0000088ull)
45#define CVMX_IOB_INB_DATA_MATCH \
46 CVMX_ADD_IO_SEG(0x00011800F0000070ull)
47#define CVMX_IOB_INB_DATA_MATCH_ENB \
48 CVMX_ADD_IO_SEG(0x00011800F0000080ull)
49#define CVMX_IOB_INT_ENB \
50 CVMX_ADD_IO_SEG(0x00011800F0000060ull)
51#define CVMX_IOB_INT_SUM \
52 CVMX_ADD_IO_SEG(0x00011800F0000058ull)
53#define CVMX_IOB_N2C_L2C_PRI_CNT \
54 CVMX_ADD_IO_SEG(0x00011800F0000020ull)
55#define CVMX_IOB_N2C_RSP_PRI_CNT \
56 CVMX_ADD_IO_SEG(0x00011800F0000008ull)
57#define CVMX_IOB_OUTB_COM_PRI_CNT \
58 CVMX_ADD_IO_SEG(0x00011800F0000040ull)
59#define CVMX_IOB_OUTB_CONTROL_MATCH \
60 CVMX_ADD_IO_SEG(0x00011800F0000098ull)
61#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
62 CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
63#define CVMX_IOB_OUTB_DATA_MATCH \
64 CVMX_ADD_IO_SEG(0x00011800F0000090ull)
65#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
66 CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
67#define CVMX_IOB_OUTB_FPA_PRI_CNT \
68 CVMX_ADD_IO_SEG(0x00011800F0000048ull)
69#define CVMX_IOB_OUTB_REQ_PRI_CNT \
70 CVMX_ADD_IO_SEG(0x00011800F0000038ull)
71#define CVMX_IOB_P2C_REQ_PRI_CNT \
72 CVMX_ADD_IO_SEG(0x00011800F0000018ull)
73#define CVMX_IOB_PKT_ERR \
74 CVMX_ADD_IO_SEG(0x00011800F0000068ull)
75
76union cvmx_iob_bist_status {
77 uint64_t u64;
78 struct cvmx_iob_bist_status_s {
79 uint64_t reserved_18_63:46;
80 uint64_t icnrcb:1;
81 uint64_t icr0:1;
82 uint64_t icr1:1;
83 uint64_t icnr1:1;
84 uint64_t icnr0:1;
85 uint64_t ibdr0:1;
86 uint64_t ibdr1:1;
87 uint64_t ibr0:1;
88 uint64_t ibr1:1;
89 uint64_t icnrt:1;
90 uint64_t ibrq0:1;
91 uint64_t ibrq1:1;
92 uint64_t icrn0:1;
93 uint64_t icrn1:1;
94 uint64_t icrp0:1;
95 uint64_t icrp1:1;
96 uint64_t ibd:1;
97 uint64_t icd:1;
98 } s;
99 struct cvmx_iob_bist_status_s cn30xx;
100 struct cvmx_iob_bist_status_s cn31xx;
101 struct cvmx_iob_bist_status_s cn38xx;
102 struct cvmx_iob_bist_status_s cn38xxp2;
103 struct cvmx_iob_bist_status_s cn50xx;
104 struct cvmx_iob_bist_status_s cn52xx;
105 struct cvmx_iob_bist_status_s cn52xxp1;
106 struct cvmx_iob_bist_status_s cn56xx;
107 struct cvmx_iob_bist_status_s cn56xxp1;
108 struct cvmx_iob_bist_status_s cn58xx;
109 struct cvmx_iob_bist_status_s cn58xxp1;
110};
111
112union cvmx_iob_ctl_status {
113 uint64_t u64;
114 struct cvmx_iob_ctl_status_s {
115 uint64_t reserved_5_63:59;
116 uint64_t outb_mat:1;
117 uint64_t inb_mat:1;
118 uint64_t pko_enb:1;
119 uint64_t dwb_enb:1;
120 uint64_t fau_end:1;
121 } s;
122 struct cvmx_iob_ctl_status_s cn30xx;
123 struct cvmx_iob_ctl_status_s cn31xx;
124 struct cvmx_iob_ctl_status_s cn38xx;
125 struct cvmx_iob_ctl_status_s cn38xxp2;
126 struct cvmx_iob_ctl_status_s cn50xx;
127 struct cvmx_iob_ctl_status_s cn52xx;
128 struct cvmx_iob_ctl_status_s cn52xxp1;
129 struct cvmx_iob_ctl_status_s cn56xx;
130 struct cvmx_iob_ctl_status_s cn56xxp1;
131 struct cvmx_iob_ctl_status_s cn58xx;
132 struct cvmx_iob_ctl_status_s cn58xxp1;
133};
134
135union cvmx_iob_dwb_pri_cnt {
136 uint64_t u64;
137 struct cvmx_iob_dwb_pri_cnt_s {
138 uint64_t reserved_16_63:48;
139 uint64_t cnt_enb:1;
140 uint64_t cnt_val:15;
141 } s;
142 struct cvmx_iob_dwb_pri_cnt_s cn38xx;
143 struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
144 struct cvmx_iob_dwb_pri_cnt_s cn52xx;
145 struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
146 struct cvmx_iob_dwb_pri_cnt_s cn56xx;
147 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
148 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
149 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
150};
151
152union cvmx_iob_fau_timeout {
153 uint64_t u64;
154 struct cvmx_iob_fau_timeout_s {
155 uint64_t reserved_13_63:51;
156 uint64_t tout_enb:1;
157 uint64_t tout_val:12;
158 } s;
159 struct cvmx_iob_fau_timeout_s cn30xx;
160 struct cvmx_iob_fau_timeout_s cn31xx;
161 struct cvmx_iob_fau_timeout_s cn38xx;
162 struct cvmx_iob_fau_timeout_s cn38xxp2;
163 struct cvmx_iob_fau_timeout_s cn50xx;
164 struct cvmx_iob_fau_timeout_s cn52xx;
165 struct cvmx_iob_fau_timeout_s cn52xxp1;
166 struct cvmx_iob_fau_timeout_s cn56xx;
167 struct cvmx_iob_fau_timeout_s cn56xxp1;
168 struct cvmx_iob_fau_timeout_s cn58xx;
169 struct cvmx_iob_fau_timeout_s cn58xxp1;
170};
171
172union cvmx_iob_i2c_pri_cnt {
173 uint64_t u64;
174 struct cvmx_iob_i2c_pri_cnt_s {
175 uint64_t reserved_16_63:48;
176 uint64_t cnt_enb:1;
177 uint64_t cnt_val:15;
178 } s;
179 struct cvmx_iob_i2c_pri_cnt_s cn38xx;
180 struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
181 struct cvmx_iob_i2c_pri_cnt_s cn52xx;
182 struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
183 struct cvmx_iob_i2c_pri_cnt_s cn56xx;
184 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
185 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
186 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
187};
188
189union cvmx_iob_inb_control_match {
190 uint64_t u64;
191 struct cvmx_iob_inb_control_match_s {
192 uint64_t reserved_29_63:35;
193 uint64_t mask:8;
194 uint64_t opc:4;
195 uint64_t dst:9;
196 uint64_t src:8;
197 } s;
198 struct cvmx_iob_inb_control_match_s cn30xx;
199 struct cvmx_iob_inb_control_match_s cn31xx;
200 struct cvmx_iob_inb_control_match_s cn38xx;
201 struct cvmx_iob_inb_control_match_s cn38xxp2;
202 struct cvmx_iob_inb_control_match_s cn50xx;
203 struct cvmx_iob_inb_control_match_s cn52xx;
204 struct cvmx_iob_inb_control_match_s cn52xxp1;
205 struct cvmx_iob_inb_control_match_s cn56xx;
206 struct cvmx_iob_inb_control_match_s cn56xxp1;
207 struct cvmx_iob_inb_control_match_s cn58xx;
208 struct cvmx_iob_inb_control_match_s cn58xxp1;
209};
210
211union cvmx_iob_inb_control_match_enb {
212 uint64_t u64;
213 struct cvmx_iob_inb_control_match_enb_s {
214 uint64_t reserved_29_63:35;
215 uint64_t mask:8;
216 uint64_t opc:4;
217 uint64_t dst:9;
218 uint64_t src:8;
219 } s;
220 struct cvmx_iob_inb_control_match_enb_s cn30xx;
221 struct cvmx_iob_inb_control_match_enb_s cn31xx;
222 struct cvmx_iob_inb_control_match_enb_s cn38xx;
223 struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
224 struct cvmx_iob_inb_control_match_enb_s cn50xx;
225 struct cvmx_iob_inb_control_match_enb_s cn52xx;
226 struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
227 struct cvmx_iob_inb_control_match_enb_s cn56xx;
228 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
229 struct cvmx_iob_inb_control_match_enb_s cn58xx;
230 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
231};
232
233union cvmx_iob_inb_data_match {
234 uint64_t u64;
235 struct cvmx_iob_inb_data_match_s {
236 uint64_t data:64;
237 } s;
238 struct cvmx_iob_inb_data_match_s cn30xx;
239 struct cvmx_iob_inb_data_match_s cn31xx;
240 struct cvmx_iob_inb_data_match_s cn38xx;
241 struct cvmx_iob_inb_data_match_s cn38xxp2;
242 struct cvmx_iob_inb_data_match_s cn50xx;
243 struct cvmx_iob_inb_data_match_s cn52xx;
244 struct cvmx_iob_inb_data_match_s cn52xxp1;
245 struct cvmx_iob_inb_data_match_s cn56xx;
246 struct cvmx_iob_inb_data_match_s cn56xxp1;
247 struct cvmx_iob_inb_data_match_s cn58xx;
248 struct cvmx_iob_inb_data_match_s cn58xxp1;
249};
250
251union cvmx_iob_inb_data_match_enb {
252 uint64_t u64;
253 struct cvmx_iob_inb_data_match_enb_s {
254 uint64_t data:64;
255 } s;
256 struct cvmx_iob_inb_data_match_enb_s cn30xx;
257 struct cvmx_iob_inb_data_match_enb_s cn31xx;
258 struct cvmx_iob_inb_data_match_enb_s cn38xx;
259 struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
260 struct cvmx_iob_inb_data_match_enb_s cn50xx;
261 struct cvmx_iob_inb_data_match_enb_s cn52xx;
262 struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
263 struct cvmx_iob_inb_data_match_enb_s cn56xx;
264 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
265 struct cvmx_iob_inb_data_match_enb_s cn58xx;
266 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
267};
268
269union cvmx_iob_int_enb {
270 uint64_t u64;
271 struct cvmx_iob_int_enb_s {
272 uint64_t reserved_6_63:58;
273 uint64_t p_dat:1;
274 uint64_t np_dat:1;
275 uint64_t p_eop:1;
276 uint64_t p_sop:1;
277 uint64_t np_eop:1;
278 uint64_t np_sop:1;
279 } s;
280 struct cvmx_iob_int_enb_cn30xx {
281 uint64_t reserved_4_63:60;
282 uint64_t p_eop:1;
283 uint64_t p_sop:1;
284 uint64_t np_eop:1;
285 uint64_t np_sop:1;
286 } cn30xx;
287 struct cvmx_iob_int_enb_cn30xx cn31xx;
288 struct cvmx_iob_int_enb_cn30xx cn38xx;
289 struct cvmx_iob_int_enb_cn30xx cn38xxp2;
290 struct cvmx_iob_int_enb_s cn50xx;
291 struct cvmx_iob_int_enb_s cn52xx;
292 struct cvmx_iob_int_enb_s cn52xxp1;
293 struct cvmx_iob_int_enb_s cn56xx;
294 struct cvmx_iob_int_enb_s cn56xxp1;
295 struct cvmx_iob_int_enb_s cn58xx;
296 struct cvmx_iob_int_enb_s cn58xxp1;
297};
298
299union cvmx_iob_int_sum {
300 uint64_t u64;
301 struct cvmx_iob_int_sum_s {
302 uint64_t reserved_6_63:58;
303 uint64_t p_dat:1;
304 uint64_t np_dat:1;
305 uint64_t p_eop:1;
306 uint64_t p_sop:1;
307 uint64_t np_eop:1;
308 uint64_t np_sop:1;
309 } s;
310 struct cvmx_iob_int_sum_cn30xx {
311 uint64_t reserved_4_63:60;
312 uint64_t p_eop:1;
313 uint64_t p_sop:1;
314 uint64_t np_eop:1;
315 uint64_t np_sop:1;
316 } cn30xx;
317 struct cvmx_iob_int_sum_cn30xx cn31xx;
318 struct cvmx_iob_int_sum_cn30xx cn38xx;
319 struct cvmx_iob_int_sum_cn30xx cn38xxp2;
320 struct cvmx_iob_int_sum_s cn50xx;
321 struct cvmx_iob_int_sum_s cn52xx;
322 struct cvmx_iob_int_sum_s cn52xxp1;
323 struct cvmx_iob_int_sum_s cn56xx;
324 struct cvmx_iob_int_sum_s cn56xxp1;
325 struct cvmx_iob_int_sum_s cn58xx;
326 struct cvmx_iob_int_sum_s cn58xxp1;
327};
328
329union cvmx_iob_n2c_l2c_pri_cnt {
330 uint64_t u64;
331 struct cvmx_iob_n2c_l2c_pri_cnt_s {
332 uint64_t reserved_16_63:48;
333 uint64_t cnt_enb:1;
334 uint64_t cnt_val:15;
335 } s;
336 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
337 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
338 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
339 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
340 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
341 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
342 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
343 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
344};
345
346union cvmx_iob_n2c_rsp_pri_cnt {
347 uint64_t u64;
348 struct cvmx_iob_n2c_rsp_pri_cnt_s {
349 uint64_t reserved_16_63:48;
350 uint64_t cnt_enb:1;
351 uint64_t cnt_val:15;
352 } s;
353 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
354 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
355 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
356 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
357 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
358 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
359 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
360 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
361};
362
363union cvmx_iob_outb_com_pri_cnt {
364 uint64_t u64;
365 struct cvmx_iob_outb_com_pri_cnt_s {
366 uint64_t reserved_16_63:48;
367 uint64_t cnt_enb:1;
368 uint64_t cnt_val:15;
369 } s;
370 struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
371 struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
372 struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
373 struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
374 struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
375 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
376 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
377 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
378};
379
380union cvmx_iob_outb_control_match {
381 uint64_t u64;
382 struct cvmx_iob_outb_control_match_s {
383 uint64_t reserved_26_63:38;
384 uint64_t mask:8;
385 uint64_t eot:1;
386 uint64_t dst:8;
387 uint64_t src:9;
388 } s;
389 struct cvmx_iob_outb_control_match_s cn30xx;
390 struct cvmx_iob_outb_control_match_s cn31xx;
391 struct cvmx_iob_outb_control_match_s cn38xx;
392 struct cvmx_iob_outb_control_match_s cn38xxp2;
393 struct cvmx_iob_outb_control_match_s cn50xx;
394 struct cvmx_iob_outb_control_match_s cn52xx;
395 struct cvmx_iob_outb_control_match_s cn52xxp1;
396 struct cvmx_iob_outb_control_match_s cn56xx;
397 struct cvmx_iob_outb_control_match_s cn56xxp1;
398 struct cvmx_iob_outb_control_match_s cn58xx;
399 struct cvmx_iob_outb_control_match_s cn58xxp1;
400};
401
402union cvmx_iob_outb_control_match_enb {
403 uint64_t u64;
404 struct cvmx_iob_outb_control_match_enb_s {
405 uint64_t reserved_26_63:38;
406 uint64_t mask:8;
407 uint64_t eot:1;
408 uint64_t dst:8;
409 uint64_t src:9;
410 } s;
411 struct cvmx_iob_outb_control_match_enb_s cn30xx;
412 struct cvmx_iob_outb_control_match_enb_s cn31xx;
413 struct cvmx_iob_outb_control_match_enb_s cn38xx;
414 struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
415 struct cvmx_iob_outb_control_match_enb_s cn50xx;
416 struct cvmx_iob_outb_control_match_enb_s cn52xx;
417 struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
418 struct cvmx_iob_outb_control_match_enb_s cn56xx;
419 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
420 struct cvmx_iob_outb_control_match_enb_s cn58xx;
421 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
422};
423
424union cvmx_iob_outb_data_match {
425 uint64_t u64;
426 struct cvmx_iob_outb_data_match_s {
427 uint64_t data:64;
428 } s;
429 struct cvmx_iob_outb_data_match_s cn30xx;
430 struct cvmx_iob_outb_data_match_s cn31xx;
431 struct cvmx_iob_outb_data_match_s cn38xx;
432 struct cvmx_iob_outb_data_match_s cn38xxp2;
433 struct cvmx_iob_outb_data_match_s cn50xx;
434 struct cvmx_iob_outb_data_match_s cn52xx;
435 struct cvmx_iob_outb_data_match_s cn52xxp1;
436 struct cvmx_iob_outb_data_match_s cn56xx;
437 struct cvmx_iob_outb_data_match_s cn56xxp1;
438 struct cvmx_iob_outb_data_match_s cn58xx;
439 struct cvmx_iob_outb_data_match_s cn58xxp1;
440};
441
442union cvmx_iob_outb_data_match_enb {
443 uint64_t u64;
444 struct cvmx_iob_outb_data_match_enb_s {
445 uint64_t data:64;
446 } s;
447 struct cvmx_iob_outb_data_match_enb_s cn30xx;
448 struct cvmx_iob_outb_data_match_enb_s cn31xx;
449 struct cvmx_iob_outb_data_match_enb_s cn38xx;
450 struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
451 struct cvmx_iob_outb_data_match_enb_s cn50xx;
452 struct cvmx_iob_outb_data_match_enb_s cn52xx;
453 struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
454 struct cvmx_iob_outb_data_match_enb_s cn56xx;
455 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
456 struct cvmx_iob_outb_data_match_enb_s cn58xx;
457 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
458};
459
460union cvmx_iob_outb_fpa_pri_cnt {
461 uint64_t u64;
462 struct cvmx_iob_outb_fpa_pri_cnt_s {
463 uint64_t reserved_16_63:48;
464 uint64_t cnt_enb:1;
465 uint64_t cnt_val:15;
466 } s;
467 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
468 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
469 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
470 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
471 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
472 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
473 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
474 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
475};
476
477union cvmx_iob_outb_req_pri_cnt {
478 uint64_t u64;
479 struct cvmx_iob_outb_req_pri_cnt_s {
480 uint64_t reserved_16_63:48;
481 uint64_t cnt_enb:1;
482 uint64_t cnt_val:15;
483 } s;
484 struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
485 struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
486 struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
487 struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
488 struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
489 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
490 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
491 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
492};
493
494union cvmx_iob_p2c_req_pri_cnt {
495 uint64_t u64;
496 struct cvmx_iob_p2c_req_pri_cnt_s {
497 uint64_t reserved_16_63:48;
498 uint64_t cnt_enb:1;
499 uint64_t cnt_val:15;
500 } s;
501 struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
502 struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
503 struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
504 struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
505 struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
506 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
507 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
508 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
509};
510
511union cvmx_iob_pkt_err {
512 uint64_t u64;
513 struct cvmx_iob_pkt_err_s {
514 uint64_t reserved_6_63:58;
515 uint64_t port:6;
516 } s;
517 struct cvmx_iob_pkt_err_s cn30xx;
518 struct cvmx_iob_pkt_err_s cn31xx;
519 struct cvmx_iob_pkt_err_s cn38xx;
520 struct cvmx_iob_pkt_err_s cn38xxp2;
521 struct cvmx_iob_pkt_err_s cn50xx;
522 struct cvmx_iob_pkt_err_s cn52xx;
523 struct cvmx_iob_pkt_err_s cn52xxp1;
524 struct cvmx_iob_pkt_err_s cn56xx;
525 struct cvmx_iob_pkt_err_s cn56xxp1;
526 struct cvmx_iob_pkt_err_s cn58xx;
527 struct cvmx_iob_pkt_err_s cn58xxp1;
528};
529
530#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
new file mode 100644
index 000000000000..f8b8fc657d2c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -0,0 +1,877 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IPD_DEFS_H__
29#define __CVMX_IPD_DEFS_H__
30
31#define CVMX_IPD_1ST_MBUFF_SKIP \
32 CVMX_ADD_IO_SEG(0x00014F0000000000ull)
33#define CVMX_IPD_1st_NEXT_PTR_BACK \
34 CVMX_ADD_IO_SEG(0x00014F0000000150ull)
35#define CVMX_IPD_2nd_NEXT_PTR_BACK \
36 CVMX_ADD_IO_SEG(0x00014F0000000158ull)
37#define CVMX_IPD_BIST_STATUS \
38 CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
39#define CVMX_IPD_BP_PRT_RED_END \
40 CVMX_ADD_IO_SEG(0x00014F0000000328ull)
41#define CVMX_IPD_CLK_COUNT \
42 CVMX_ADD_IO_SEG(0x00014F0000000338ull)
43#define CVMX_IPD_CTL_STATUS \
44 CVMX_ADD_IO_SEG(0x00014F0000000018ull)
45#define CVMX_IPD_INT_ENB \
46 CVMX_ADD_IO_SEG(0x00014F0000000160ull)
47#define CVMX_IPD_INT_SUM \
48 CVMX_ADD_IO_SEG(0x00014F0000000168ull)
49#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
50 CVMX_ADD_IO_SEG(0x00014F0000000008ull)
51#define CVMX_IPD_PACKET_MBUFF_SIZE \
52 CVMX_ADD_IO_SEG(0x00014F0000000010ull)
53#define CVMX_IPD_PKT_PTR_VALID \
54 CVMX_ADD_IO_SEG(0x00014F0000000358ull)
55#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
56 CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
57#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
58 CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
59#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
60 CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
61#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
62 CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
63#define CVMX_IPD_PORT_QOS_INTX(offset) \
64 CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
65#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
66 CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
67#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
68 CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
69#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
70 CVMX_ADD_IO_SEG(0x00014F0000000348ull)
71#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
72 CVMX_ADD_IO_SEG(0x00014F0000000350ull)
73#define CVMX_IPD_PTR_COUNT \
74 CVMX_ADD_IO_SEG(0x00014F0000000320ull)
75#define CVMX_IPD_PWP_PTR_FIFO_CTL \
76 CVMX_ADD_IO_SEG(0x00014F0000000340ull)
77#define CVMX_IPD_QOS0_RED_MARKS \
78 CVMX_ADD_IO_SEG(0x00014F0000000178ull)
79#define CVMX_IPD_QOS1_RED_MARKS \
80 CVMX_ADD_IO_SEG(0x00014F0000000180ull)
81#define CVMX_IPD_QOS2_RED_MARKS \
82 CVMX_ADD_IO_SEG(0x00014F0000000188ull)
83#define CVMX_IPD_QOS3_RED_MARKS \
84 CVMX_ADD_IO_SEG(0x00014F0000000190ull)
85#define CVMX_IPD_QOS4_RED_MARKS \
86 CVMX_ADD_IO_SEG(0x00014F0000000198ull)
87#define CVMX_IPD_QOS5_RED_MARKS \
88 CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
89#define CVMX_IPD_QOS6_RED_MARKS \
90 CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
91#define CVMX_IPD_QOS7_RED_MARKS \
92 CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
93#define CVMX_IPD_QOSX_RED_MARKS(offset) \
94 CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
95#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
96 CVMX_ADD_IO_SEG(0x00014F0000000330ull)
97#define CVMX_IPD_RED_PORT_ENABLE \
98 CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
99#define CVMX_IPD_RED_PORT_ENABLE2 \
100 CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
101#define CVMX_IPD_RED_QUE0_PARAM \
102 CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
103#define CVMX_IPD_RED_QUE1_PARAM \
104 CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
105#define CVMX_IPD_RED_QUE2_PARAM \
106 CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
107#define CVMX_IPD_RED_QUE3_PARAM \
108 CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
109#define CVMX_IPD_RED_QUE4_PARAM \
110 CVMX_ADD_IO_SEG(0x00014F0000000300ull)
111#define CVMX_IPD_RED_QUE5_PARAM \
112 CVMX_ADD_IO_SEG(0x00014F0000000308ull)
113#define CVMX_IPD_RED_QUE6_PARAM \
114 CVMX_ADD_IO_SEG(0x00014F0000000310ull)
115#define CVMX_IPD_RED_QUE7_PARAM \
116 CVMX_ADD_IO_SEG(0x00014F0000000318ull)
117#define CVMX_IPD_RED_QUEX_PARAM(offset) \
118 CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
119#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
120 CVMX_ADD_IO_SEG(0x00014F0000000148ull)
121#define CVMX_IPD_SUB_PORT_FCS \
122 CVMX_ADD_IO_SEG(0x00014F0000000170ull)
123#define CVMX_IPD_SUB_PORT_QOS_CNT \
124 CVMX_ADD_IO_SEG(0x00014F0000000800ull)
125#define CVMX_IPD_WQE_FPA_QUEUE \
126 CVMX_ADD_IO_SEG(0x00014F0000000020ull)
127#define CVMX_IPD_WQE_PTR_VALID \
128 CVMX_ADD_IO_SEG(0x00014F0000000360ull)
129
130union cvmx_ipd_1st_mbuff_skip {
131 uint64_t u64;
132 struct cvmx_ipd_1st_mbuff_skip_s {
133 uint64_t reserved_6_63:58;
134 uint64_t skip_sz:6;
135 } s;
136 struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
137 struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
138 struct cvmx_ipd_1st_mbuff_skip_s cn38xx;
139 struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;
140 struct cvmx_ipd_1st_mbuff_skip_s cn50xx;
141 struct cvmx_ipd_1st_mbuff_skip_s cn52xx;
142 struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;
143 struct cvmx_ipd_1st_mbuff_skip_s cn56xx;
144 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
145 struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
146 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
147};
148
149union cvmx_ipd_1st_next_ptr_back {
150 uint64_t u64;
151 struct cvmx_ipd_1st_next_ptr_back_s {
152 uint64_t reserved_4_63:60;
153 uint64_t back:4;
154 } s;
155 struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
156 struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
157 struct cvmx_ipd_1st_next_ptr_back_s cn38xx;
158 struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;
159 struct cvmx_ipd_1st_next_ptr_back_s cn50xx;
160 struct cvmx_ipd_1st_next_ptr_back_s cn52xx;
161 struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;
162 struct cvmx_ipd_1st_next_ptr_back_s cn56xx;
163 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
164 struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
165 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
166};
167
168union cvmx_ipd_2nd_next_ptr_back {
169 uint64_t u64;
170 struct cvmx_ipd_2nd_next_ptr_back_s {
171 uint64_t reserved_4_63:60;
172 uint64_t back:4;
173 } s;
174 struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
175 struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
176 struct cvmx_ipd_2nd_next_ptr_back_s cn38xx;
177 struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;
178 struct cvmx_ipd_2nd_next_ptr_back_s cn50xx;
179 struct cvmx_ipd_2nd_next_ptr_back_s cn52xx;
180 struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;
181 struct cvmx_ipd_2nd_next_ptr_back_s cn56xx;
182 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
183 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
184 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
185};
186
187union cvmx_ipd_bist_status {
188 uint64_t u64;
189 struct cvmx_ipd_bist_status_s {
190 uint64_t reserved_18_63:46;
191 uint64_t csr_mem:1;
192 uint64_t csr_ncmd:1;
193 uint64_t pwq_wqed:1;
194 uint64_t pwq_wp1:1;
195 uint64_t pwq_pow:1;
196 uint64_t ipq_pbe1:1;
197 uint64_t ipq_pbe0:1;
198 uint64_t pbm3:1;
199 uint64_t pbm2:1;
200 uint64_t pbm1:1;
201 uint64_t pbm0:1;
202 uint64_t pbm_word:1;
203 uint64_t pwq1:1;
204 uint64_t pwq0:1;
205 uint64_t prc_off:1;
206 uint64_t ipd_old:1;
207 uint64_t ipd_new:1;
208 uint64_t pwp:1;
209 } s;
210 struct cvmx_ipd_bist_status_cn30xx {
211 uint64_t reserved_16_63:48;
212 uint64_t pwq_wqed:1;
213 uint64_t pwq_wp1:1;
214 uint64_t pwq_pow:1;
215 uint64_t ipq_pbe1:1;
216 uint64_t ipq_pbe0:1;
217 uint64_t pbm3:1;
218 uint64_t pbm2:1;
219 uint64_t pbm1:1;
220 uint64_t pbm0:1;
221 uint64_t pbm_word:1;
222 uint64_t pwq1:1;
223 uint64_t pwq0:1;
224 uint64_t prc_off:1;
225 uint64_t ipd_old:1;
226 uint64_t ipd_new:1;
227 uint64_t pwp:1;
228 } cn30xx;
229 struct cvmx_ipd_bist_status_cn30xx cn31xx;
230 struct cvmx_ipd_bist_status_cn30xx cn38xx;
231 struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
232 struct cvmx_ipd_bist_status_cn30xx cn50xx;
233 struct cvmx_ipd_bist_status_s cn52xx;
234 struct cvmx_ipd_bist_status_s cn52xxp1;
235 struct cvmx_ipd_bist_status_s cn56xx;
236 struct cvmx_ipd_bist_status_s cn56xxp1;
237 struct cvmx_ipd_bist_status_cn30xx cn58xx;
238 struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
239};
240
241union cvmx_ipd_bp_prt_red_end {
242 uint64_t u64;
243 struct cvmx_ipd_bp_prt_red_end_s {
244 uint64_t reserved_40_63:24;
245 uint64_t prt_enb:40;
246 } s;
247 struct cvmx_ipd_bp_prt_red_end_cn30xx {
248 uint64_t reserved_36_63:28;
249 uint64_t prt_enb:36;
250 } cn30xx;
251 struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
252 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
253 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
254 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
255 struct cvmx_ipd_bp_prt_red_end_s cn52xx;
256 struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
257 struct cvmx_ipd_bp_prt_red_end_s cn56xx;
258 struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
259 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
260 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
261};
262
263union cvmx_ipd_clk_count {
264 uint64_t u64;
265 struct cvmx_ipd_clk_count_s {
266 uint64_t clk_cnt:64;
267 } s;
268 struct cvmx_ipd_clk_count_s cn30xx;
269 struct cvmx_ipd_clk_count_s cn31xx;
270 struct cvmx_ipd_clk_count_s cn38xx;
271 struct cvmx_ipd_clk_count_s cn38xxp2;
272 struct cvmx_ipd_clk_count_s cn50xx;
273 struct cvmx_ipd_clk_count_s cn52xx;
274 struct cvmx_ipd_clk_count_s cn52xxp1;
275 struct cvmx_ipd_clk_count_s cn56xx;
276 struct cvmx_ipd_clk_count_s cn56xxp1;
277 struct cvmx_ipd_clk_count_s cn58xx;
278 struct cvmx_ipd_clk_count_s cn58xxp1;
279};
280
281union cvmx_ipd_ctl_status {
282 uint64_t u64;
283 struct cvmx_ipd_ctl_status_s {
284 uint64_t reserved_15_63:49;
285 uint64_t no_wptr:1;
286 uint64_t pq_apkt:1;
287 uint64_t pq_nabuf:1;
288 uint64_t ipd_full:1;
289 uint64_t pkt_off:1;
290 uint64_t len_m8:1;
291 uint64_t reset:1;
292 uint64_t addpkt:1;
293 uint64_t naddbuf:1;
294 uint64_t pkt_lend:1;
295 uint64_t wqe_lend:1;
296 uint64_t pbp_en:1;
297 uint64_t opc_mode:2;
298 uint64_t ipd_en:1;
299 } s;
300 struct cvmx_ipd_ctl_status_cn30xx {
301 uint64_t reserved_10_63:54;
302 uint64_t len_m8:1;
303 uint64_t reset:1;
304 uint64_t addpkt:1;
305 uint64_t naddbuf:1;
306 uint64_t pkt_lend:1;
307 uint64_t wqe_lend:1;
308 uint64_t pbp_en:1;
309 uint64_t opc_mode:2;
310 uint64_t ipd_en:1;
311 } cn30xx;
312 struct cvmx_ipd_ctl_status_cn30xx cn31xx;
313 struct cvmx_ipd_ctl_status_cn30xx cn38xx;
314 struct cvmx_ipd_ctl_status_cn38xxp2 {
315 uint64_t reserved_9_63:55;
316 uint64_t reset:1;
317 uint64_t addpkt:1;
318 uint64_t naddbuf:1;
319 uint64_t pkt_lend:1;
320 uint64_t wqe_lend:1;
321 uint64_t pbp_en:1;
322 uint64_t opc_mode:2;
323 uint64_t ipd_en:1;
324 } cn38xxp2;
325 struct cvmx_ipd_ctl_status_s cn50xx;
326 struct cvmx_ipd_ctl_status_s cn52xx;
327 struct cvmx_ipd_ctl_status_s cn52xxp1;
328 struct cvmx_ipd_ctl_status_s cn56xx;
329 struct cvmx_ipd_ctl_status_s cn56xxp1;
330 struct cvmx_ipd_ctl_status_cn58xx {
331 uint64_t reserved_12_63:52;
332 uint64_t ipd_full:1;
333 uint64_t pkt_off:1;
334 uint64_t len_m8:1;
335 uint64_t reset:1;
336 uint64_t addpkt:1;
337 uint64_t naddbuf:1;
338 uint64_t pkt_lend:1;
339 uint64_t wqe_lend:1;
340 uint64_t pbp_en:1;
341 uint64_t opc_mode:2;
342 uint64_t ipd_en:1;
343 } cn58xx;
344 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
345};
346
347union cvmx_ipd_int_enb {
348 uint64_t u64;
349 struct cvmx_ipd_int_enb_s {
350 uint64_t reserved_12_63:52;
351 uint64_t pq_sub:1;
352 uint64_t pq_add:1;
353 uint64_t bc_ovr:1;
354 uint64_t d_coll:1;
355 uint64_t c_coll:1;
356 uint64_t cc_ovr:1;
357 uint64_t dc_ovr:1;
358 uint64_t bp_sub:1;
359 uint64_t prc_par3:1;
360 uint64_t prc_par2:1;
361 uint64_t prc_par1:1;
362 uint64_t prc_par0:1;
363 } s;
364 struct cvmx_ipd_int_enb_cn30xx {
365 uint64_t reserved_5_63:59;
366 uint64_t bp_sub:1;
367 uint64_t prc_par3:1;
368 uint64_t prc_par2:1;
369 uint64_t prc_par1:1;
370 uint64_t prc_par0:1;
371 } cn30xx;
372 struct cvmx_ipd_int_enb_cn30xx cn31xx;
373 struct cvmx_ipd_int_enb_cn38xx {
374 uint64_t reserved_10_63:54;
375 uint64_t bc_ovr:1;
376 uint64_t d_coll:1;
377 uint64_t c_coll:1;
378 uint64_t cc_ovr:1;
379 uint64_t dc_ovr:1;
380 uint64_t bp_sub:1;
381 uint64_t prc_par3:1;
382 uint64_t prc_par2:1;
383 uint64_t prc_par1:1;
384 uint64_t prc_par0:1;
385 } cn38xx;
386 struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
387 struct cvmx_ipd_int_enb_cn38xx cn50xx;
388 struct cvmx_ipd_int_enb_s cn52xx;
389 struct cvmx_ipd_int_enb_s cn52xxp1;
390 struct cvmx_ipd_int_enb_s cn56xx;
391 struct cvmx_ipd_int_enb_s cn56xxp1;
392 struct cvmx_ipd_int_enb_cn38xx cn58xx;
393 struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
394};
395
396union cvmx_ipd_int_sum {
397 uint64_t u64;
398 struct cvmx_ipd_int_sum_s {
399 uint64_t reserved_12_63:52;
400 uint64_t pq_sub:1;
401 uint64_t pq_add:1;
402 uint64_t bc_ovr:1;
403 uint64_t d_coll:1;
404 uint64_t c_coll:1;
405 uint64_t cc_ovr:1;
406 uint64_t dc_ovr:1;
407 uint64_t bp_sub:1;
408 uint64_t prc_par3:1;
409 uint64_t prc_par2:1;
410 uint64_t prc_par1:1;
411 uint64_t prc_par0:1;
412 } s;
413 struct cvmx_ipd_int_sum_cn30xx {
414 uint64_t reserved_5_63:59;
415 uint64_t bp_sub:1;
416 uint64_t prc_par3:1;
417 uint64_t prc_par2:1;
418 uint64_t prc_par1:1;
419 uint64_t prc_par0:1;
420 } cn30xx;
421 struct cvmx_ipd_int_sum_cn30xx cn31xx;
422 struct cvmx_ipd_int_sum_cn38xx {
423 uint64_t reserved_10_63:54;
424 uint64_t bc_ovr:1;
425 uint64_t d_coll:1;
426 uint64_t c_coll:1;
427 uint64_t cc_ovr:1;
428 uint64_t dc_ovr:1;
429 uint64_t bp_sub:1;
430 uint64_t prc_par3:1;
431 uint64_t prc_par2:1;
432 uint64_t prc_par1:1;
433 uint64_t prc_par0:1;
434 } cn38xx;
435 struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
436 struct cvmx_ipd_int_sum_cn38xx cn50xx;
437 struct cvmx_ipd_int_sum_s cn52xx;
438 struct cvmx_ipd_int_sum_s cn52xxp1;
439 struct cvmx_ipd_int_sum_s cn56xx;
440 struct cvmx_ipd_int_sum_s cn56xxp1;
441 struct cvmx_ipd_int_sum_cn38xx cn58xx;
442 struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
443};
444
445union cvmx_ipd_not_1st_mbuff_skip {
446 uint64_t u64;
447 struct cvmx_ipd_not_1st_mbuff_skip_s {
448 uint64_t reserved_6_63:58;
449 uint64_t skip_sz:6;
450 } s;
451 struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
452 struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
453 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
454 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
455 struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
456 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
457 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
458 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
459 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
460 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
461 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
462};
463
464union cvmx_ipd_packet_mbuff_size {
465 uint64_t u64;
466 struct cvmx_ipd_packet_mbuff_size_s {
467 uint64_t reserved_12_63:52;
468 uint64_t mb_size:12;
469 } s;
470 struct cvmx_ipd_packet_mbuff_size_s cn30xx;
471 struct cvmx_ipd_packet_mbuff_size_s cn31xx;
472 struct cvmx_ipd_packet_mbuff_size_s cn38xx;
473 struct cvmx_ipd_packet_mbuff_size_s cn38xxp2;
474 struct cvmx_ipd_packet_mbuff_size_s cn50xx;
475 struct cvmx_ipd_packet_mbuff_size_s cn52xx;
476 struct cvmx_ipd_packet_mbuff_size_s cn52xxp1;
477 struct cvmx_ipd_packet_mbuff_size_s cn56xx;
478 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
479 struct cvmx_ipd_packet_mbuff_size_s cn58xx;
480 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
481};
482
483union cvmx_ipd_pkt_ptr_valid {
484 uint64_t u64;
485 struct cvmx_ipd_pkt_ptr_valid_s {
486 uint64_t reserved_29_63:35;
487 uint64_t ptr:29;
488 } s;
489 struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
490 struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
491 struct cvmx_ipd_pkt_ptr_valid_s cn38xx;
492 struct cvmx_ipd_pkt_ptr_valid_s cn50xx;
493 struct cvmx_ipd_pkt_ptr_valid_s cn52xx;
494 struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;
495 struct cvmx_ipd_pkt_ptr_valid_s cn56xx;
496 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
497 struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
498 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
499};
500
501union cvmx_ipd_portx_bp_page_cnt {
502 uint64_t u64;
503 struct cvmx_ipd_portx_bp_page_cnt_s {
504 uint64_t reserved_18_63:46;
505 uint64_t bp_enb:1;
506 uint64_t page_cnt:17;
507 } s;
508 struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
509 struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
510 struct cvmx_ipd_portx_bp_page_cnt_s cn38xx;
511 struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;
512 struct cvmx_ipd_portx_bp_page_cnt_s cn50xx;
513 struct cvmx_ipd_portx_bp_page_cnt_s cn52xx;
514 struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;
515 struct cvmx_ipd_portx_bp_page_cnt_s cn56xx;
516 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
517 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
518 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
519};
520
521union cvmx_ipd_portx_bp_page_cnt2 {
522 uint64_t u64;
523 struct cvmx_ipd_portx_bp_page_cnt2_s {
524 uint64_t reserved_18_63:46;
525 uint64_t bp_enb:1;
526 uint64_t page_cnt:17;
527 } s;
528 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
529 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
530 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
531 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
532};
533
534union cvmx_ipd_port_bp_counters2_pairx {
535 uint64_t u64;
536 struct cvmx_ipd_port_bp_counters2_pairx_s {
537 uint64_t reserved_25_63:39;
538 uint64_t cnt_val:25;
539 } s;
540 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
541 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
542 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
543 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
544};
545
546union cvmx_ipd_port_bp_counters_pairx {
547 uint64_t u64;
548 struct cvmx_ipd_port_bp_counters_pairx_s {
549 uint64_t reserved_25_63:39;
550 uint64_t cnt_val:25;
551 } s;
552 struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
553 struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
554 struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
555 struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
556 struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
557 struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
558 struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
559 struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
560 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
561 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
562 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
563};
564
565union cvmx_ipd_port_qos_x_cnt {
566 uint64_t u64;
567 struct cvmx_ipd_port_qos_x_cnt_s {
568 uint64_t wmark:32;
569 uint64_t cnt:32;
570 } s;
571 struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
572 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
573 struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
574 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
575};
576
577union cvmx_ipd_port_qos_intx {
578 uint64_t u64;
579 struct cvmx_ipd_port_qos_intx_s {
580 uint64_t intr:64;
581 } s;
582 struct cvmx_ipd_port_qos_intx_s cn52xx;
583 struct cvmx_ipd_port_qos_intx_s cn52xxp1;
584 struct cvmx_ipd_port_qos_intx_s cn56xx;
585 struct cvmx_ipd_port_qos_intx_s cn56xxp1;
586};
587
588union cvmx_ipd_port_qos_int_enbx {
589 uint64_t u64;
590 struct cvmx_ipd_port_qos_int_enbx_s {
591 uint64_t enb:64;
592 } s;
593 struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
594 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
595 struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
596 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
597};
598
599union cvmx_ipd_prc_hold_ptr_fifo_ctl {
600 uint64_t u64;
601 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
602 uint64_t reserved_39_63:25;
603 uint64_t max_pkt:3;
604 uint64_t praddr:3;
605 uint64_t ptr:29;
606 uint64_t cena:1;
607 uint64_t raddr:3;
608 } s;
609 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
610 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
611 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
612 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
613 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
614 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
615 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
616 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
617 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
618 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
619};
620
621union cvmx_ipd_prc_port_ptr_fifo_ctl {
622 uint64_t u64;
623 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
624 uint64_t reserved_44_63:20;
625 uint64_t max_pkt:7;
626 uint64_t ptr:29;
627 uint64_t cena:1;
628 uint64_t raddr:7;
629 } s;
630 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
631 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
632 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
633 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
634 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
635 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
636 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
637 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
638 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
639 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
640};
641
642union cvmx_ipd_ptr_count {
643 uint64_t u64;
644 struct cvmx_ipd_ptr_count_s {
645 uint64_t reserved_19_63:45;
646 uint64_t pktv_cnt:1;
647 uint64_t wqev_cnt:1;
648 uint64_t pfif_cnt:3;
649 uint64_t pkt_pcnt:7;
650 uint64_t wqe_pcnt:7;
651 } s;
652 struct cvmx_ipd_ptr_count_s cn30xx;
653 struct cvmx_ipd_ptr_count_s cn31xx;
654 struct cvmx_ipd_ptr_count_s cn38xx;
655 struct cvmx_ipd_ptr_count_s cn38xxp2;
656 struct cvmx_ipd_ptr_count_s cn50xx;
657 struct cvmx_ipd_ptr_count_s cn52xx;
658 struct cvmx_ipd_ptr_count_s cn52xxp1;
659 struct cvmx_ipd_ptr_count_s cn56xx;
660 struct cvmx_ipd_ptr_count_s cn56xxp1;
661 struct cvmx_ipd_ptr_count_s cn58xx;
662 struct cvmx_ipd_ptr_count_s cn58xxp1;
663};
664
665union cvmx_ipd_pwp_ptr_fifo_ctl {
666 uint64_t u64;
667 struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
668 uint64_t reserved_61_63:3;
669 uint64_t max_cnts:7;
670 uint64_t wraddr:8;
671 uint64_t praddr:8;
672 uint64_t ptr:29;
673 uint64_t cena:1;
674 uint64_t raddr:8;
675 } s;
676 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
677 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
678 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;
679 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;
680 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;
681 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;
682 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;
683 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
684 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
685 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
686};
687
688union cvmx_ipd_qosx_red_marks {
689 uint64_t u64;
690 struct cvmx_ipd_qosx_red_marks_s {
691 uint64_t drop:32;
692 uint64_t pass:32;
693 } s;
694 struct cvmx_ipd_qosx_red_marks_s cn30xx;
695 struct cvmx_ipd_qosx_red_marks_s cn31xx;
696 struct cvmx_ipd_qosx_red_marks_s cn38xx;
697 struct cvmx_ipd_qosx_red_marks_s cn38xxp2;
698 struct cvmx_ipd_qosx_red_marks_s cn50xx;
699 struct cvmx_ipd_qosx_red_marks_s cn52xx;
700 struct cvmx_ipd_qosx_red_marks_s cn52xxp1;
701 struct cvmx_ipd_qosx_red_marks_s cn56xx;
702 struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
703 struct cvmx_ipd_qosx_red_marks_s cn58xx;
704 struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
705};
706
707union cvmx_ipd_que0_free_page_cnt {
708 uint64_t u64;
709 struct cvmx_ipd_que0_free_page_cnt_s {
710 uint64_t reserved_32_63:32;
711 uint64_t q0_pcnt:32;
712 } s;
713 struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
714 struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
715 struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
716 struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
717 struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
718 struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
719 struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
720 struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
721 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
722 struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
723 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
724};
725
726union cvmx_ipd_red_port_enable {
727 uint64_t u64;
728 struct cvmx_ipd_red_port_enable_s {
729 uint64_t prb_dly:14;
730 uint64_t avg_dly:14;
731 uint64_t prt_enb:36;
732 } s;
733 struct cvmx_ipd_red_port_enable_s cn30xx;
734 struct cvmx_ipd_red_port_enable_s cn31xx;
735 struct cvmx_ipd_red_port_enable_s cn38xx;
736 struct cvmx_ipd_red_port_enable_s cn38xxp2;
737 struct cvmx_ipd_red_port_enable_s cn50xx;
738 struct cvmx_ipd_red_port_enable_s cn52xx;
739 struct cvmx_ipd_red_port_enable_s cn52xxp1;
740 struct cvmx_ipd_red_port_enable_s cn56xx;
741 struct cvmx_ipd_red_port_enable_s cn56xxp1;
742 struct cvmx_ipd_red_port_enable_s cn58xx;
743 struct cvmx_ipd_red_port_enable_s cn58xxp1;
744};
745
746union cvmx_ipd_red_port_enable2 {
747 uint64_t u64;
748 struct cvmx_ipd_red_port_enable2_s {
749 uint64_t reserved_4_63:60;
750 uint64_t prt_enb:4;
751 } s;
752 struct cvmx_ipd_red_port_enable2_s cn52xx;
753 struct cvmx_ipd_red_port_enable2_s cn52xxp1;
754 struct cvmx_ipd_red_port_enable2_s cn56xx;
755 struct cvmx_ipd_red_port_enable2_s cn56xxp1;
756};
757
758union cvmx_ipd_red_quex_param {
759 uint64_t u64;
760 struct cvmx_ipd_red_quex_param_s {
761 uint64_t reserved_49_63:15;
762 uint64_t use_pcnt:1;
763 uint64_t new_con:8;
764 uint64_t avg_con:8;
765 uint64_t prb_con:32;
766 } s;
767 struct cvmx_ipd_red_quex_param_s cn30xx;
768 struct cvmx_ipd_red_quex_param_s cn31xx;
769 struct cvmx_ipd_red_quex_param_s cn38xx;
770 struct cvmx_ipd_red_quex_param_s cn38xxp2;
771 struct cvmx_ipd_red_quex_param_s cn50xx;
772 struct cvmx_ipd_red_quex_param_s cn52xx;
773 struct cvmx_ipd_red_quex_param_s cn52xxp1;
774 struct cvmx_ipd_red_quex_param_s cn56xx;
775 struct cvmx_ipd_red_quex_param_s cn56xxp1;
776 struct cvmx_ipd_red_quex_param_s cn58xx;
777 struct cvmx_ipd_red_quex_param_s cn58xxp1;
778};
779
780union cvmx_ipd_sub_port_bp_page_cnt {
781 uint64_t u64;
782 struct cvmx_ipd_sub_port_bp_page_cnt_s {
783 uint64_t reserved_31_63:33;
784 uint64_t port:6;
785 uint64_t page_cnt:25;
786 } s;
787 struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
788 struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
789 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
790 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
791 struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
792 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
793 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
794 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
795 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
796 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
797 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
798};
799
800union cvmx_ipd_sub_port_fcs {
801 uint64_t u64;
802 struct cvmx_ipd_sub_port_fcs_s {
803 uint64_t reserved_40_63:24;
804 uint64_t port_bit2:4;
805 uint64_t reserved_32_35:4;
806 uint64_t port_bit:32;
807 } s;
808 struct cvmx_ipd_sub_port_fcs_cn30xx {
809 uint64_t reserved_3_63:61;
810 uint64_t port_bit:3;
811 } cn30xx;
812 struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
813 struct cvmx_ipd_sub_port_fcs_cn38xx {
814 uint64_t reserved_32_63:32;
815 uint64_t port_bit:32;
816 } cn38xx;
817 struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
818 struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
819 struct cvmx_ipd_sub_port_fcs_s cn52xx;
820 struct cvmx_ipd_sub_port_fcs_s cn52xxp1;
821 struct cvmx_ipd_sub_port_fcs_s cn56xx;
822 struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
823 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
824 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
825};
826
827union cvmx_ipd_sub_port_qos_cnt {
828 uint64_t u64;
829 struct cvmx_ipd_sub_port_qos_cnt_s {
830 uint64_t reserved_41_63:23;
831 uint64_t port_qos:9;
832 uint64_t cnt:32;
833 } s;
834 struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
835 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
836 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
837 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
838};
839
840union cvmx_ipd_wqe_fpa_queue {
841 uint64_t u64;
842 struct cvmx_ipd_wqe_fpa_queue_s {
843 uint64_t reserved_3_63:61;
844 uint64_t wqe_pool:3;
845 } s;
846 struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
847 struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
848 struct cvmx_ipd_wqe_fpa_queue_s cn38xx;
849 struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;
850 struct cvmx_ipd_wqe_fpa_queue_s cn50xx;
851 struct cvmx_ipd_wqe_fpa_queue_s cn52xx;
852 struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;
853 struct cvmx_ipd_wqe_fpa_queue_s cn56xx;
854 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
855 struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
856 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
857};
858
859union cvmx_ipd_wqe_ptr_valid {
860 uint64_t u64;
861 struct cvmx_ipd_wqe_ptr_valid_s {
862 uint64_t reserved_29_63:35;
863 uint64_t ptr:29;
864 } s;
865 struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
866 struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
867 struct cvmx_ipd_wqe_ptr_valid_s cn38xx;
868 struct cvmx_ipd_wqe_ptr_valid_s cn50xx;
869 struct cvmx_ipd_wqe_ptr_valid_s cn52xx;
870 struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;
871 struct cvmx_ipd_wqe_ptr_valid_s cn56xx;
872 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
873 struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
874 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
875};
876
877#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
new file mode 100644
index 000000000000..337583842b51
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -0,0 +1,963 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2C_DEFS_H__
29#define __CVMX_L2C_DEFS_H__
30
31#define CVMX_L2C_BST0 \
32 CVMX_ADD_IO_SEG(0x00011800800007F8ull)
33#define CVMX_L2C_BST1 \
34 CVMX_ADD_IO_SEG(0x00011800800007F0ull)
35#define CVMX_L2C_BST2 \
36 CVMX_ADD_IO_SEG(0x00011800800007E8ull)
37#define CVMX_L2C_CFG \
38 CVMX_ADD_IO_SEG(0x0001180080000000ull)
39#define CVMX_L2C_DBG \
40 CVMX_ADD_IO_SEG(0x0001180080000030ull)
41#define CVMX_L2C_DUT \
42 CVMX_ADD_IO_SEG(0x0001180080000050ull)
43#define CVMX_L2C_GRPWRR0 \
44 CVMX_ADD_IO_SEG(0x00011800800000C8ull)
45#define CVMX_L2C_GRPWRR1 \
46 CVMX_ADD_IO_SEG(0x00011800800000D0ull)
47#define CVMX_L2C_INT_EN \
48 CVMX_ADD_IO_SEG(0x0001180080000100ull)
49#define CVMX_L2C_INT_STAT \
50 CVMX_ADD_IO_SEG(0x00011800800000F8ull)
51#define CVMX_L2C_LCKBASE \
52 CVMX_ADD_IO_SEG(0x0001180080000058ull)
53#define CVMX_L2C_LCKOFF \
54 CVMX_ADD_IO_SEG(0x0001180080000060ull)
55#define CVMX_L2C_LFB0 \
56 CVMX_ADD_IO_SEG(0x0001180080000038ull)
57#define CVMX_L2C_LFB1 \
58 CVMX_ADD_IO_SEG(0x0001180080000040ull)
59#define CVMX_L2C_LFB2 \
60 CVMX_ADD_IO_SEG(0x0001180080000048ull)
61#define CVMX_L2C_LFB3 \
62 CVMX_ADD_IO_SEG(0x00011800800000B8ull)
63#define CVMX_L2C_OOB \
64 CVMX_ADD_IO_SEG(0x00011800800000D8ull)
65#define CVMX_L2C_OOB1 \
66 CVMX_ADD_IO_SEG(0x00011800800000E0ull)
67#define CVMX_L2C_OOB2 \
68 CVMX_ADD_IO_SEG(0x00011800800000E8ull)
69#define CVMX_L2C_OOB3 \
70 CVMX_ADD_IO_SEG(0x00011800800000F0ull)
71#define CVMX_L2C_PFC0 \
72 CVMX_ADD_IO_SEG(0x0001180080000098ull)
73#define CVMX_L2C_PFC1 \
74 CVMX_ADD_IO_SEG(0x00011800800000A0ull)
75#define CVMX_L2C_PFC2 \
76 CVMX_ADD_IO_SEG(0x00011800800000A8ull)
77#define CVMX_L2C_PFC3 \
78 CVMX_ADD_IO_SEG(0x00011800800000B0ull)
79#define CVMX_L2C_PFCTL \
80 CVMX_ADD_IO_SEG(0x0001180080000090ull)
81#define CVMX_L2C_PFCX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
83#define CVMX_L2C_PPGRP \
84 CVMX_ADD_IO_SEG(0x00011800800000C0ull)
85#define CVMX_L2C_SPAR0 \
86 CVMX_ADD_IO_SEG(0x0001180080000068ull)
87#define CVMX_L2C_SPAR1 \
88 CVMX_ADD_IO_SEG(0x0001180080000070ull)
89#define CVMX_L2C_SPAR2 \
90 CVMX_ADD_IO_SEG(0x0001180080000078ull)
91#define CVMX_L2C_SPAR3 \
92 CVMX_ADD_IO_SEG(0x0001180080000080ull)
93#define CVMX_L2C_SPAR4 \
94 CVMX_ADD_IO_SEG(0x0001180080000088ull)
95
96union cvmx_l2c_bst0 {
97 uint64_t u64;
98 struct cvmx_l2c_bst0_s {
99 uint64_t reserved_24_63:40;
100 uint64_t dtbnk:1;
101 uint64_t wlb_msk:4;
102 uint64_t dtcnt:13;
103 uint64_t dt:1;
104 uint64_t stin_msk:1;
105 uint64_t wlb_dat:4;
106 } s;
107 struct cvmx_l2c_bst0_cn30xx {
108 uint64_t reserved_23_63:41;
109 uint64_t wlb_msk:4;
110 uint64_t reserved_15_18:4;
111 uint64_t dtcnt:9;
112 uint64_t dt:1;
113 uint64_t reserved_4_4:1;
114 uint64_t wlb_dat:4;
115 } cn30xx;
116 struct cvmx_l2c_bst0_cn31xx {
117 uint64_t reserved_23_63:41;
118 uint64_t wlb_msk:4;
119 uint64_t reserved_16_18:3;
120 uint64_t dtcnt:10;
121 uint64_t dt:1;
122 uint64_t stin_msk:1;
123 uint64_t wlb_dat:4;
124 } cn31xx;
125 struct cvmx_l2c_bst0_cn38xx {
126 uint64_t reserved_19_63:45;
127 uint64_t dtcnt:13;
128 uint64_t dt:1;
129 uint64_t stin_msk:1;
130 uint64_t wlb_dat:4;
131 } cn38xx;
132 struct cvmx_l2c_bst0_cn38xx cn38xxp2;
133 struct cvmx_l2c_bst0_cn50xx {
134 uint64_t reserved_24_63:40;
135 uint64_t dtbnk:1;
136 uint64_t wlb_msk:4;
137 uint64_t reserved_16_18:3;
138 uint64_t dtcnt:10;
139 uint64_t dt:1;
140 uint64_t stin_msk:1;
141 uint64_t wlb_dat:4;
142 } cn50xx;
143 struct cvmx_l2c_bst0_cn50xx cn52xx;
144 struct cvmx_l2c_bst0_cn50xx cn52xxp1;
145 struct cvmx_l2c_bst0_s cn56xx;
146 struct cvmx_l2c_bst0_s cn56xxp1;
147 struct cvmx_l2c_bst0_s cn58xx;
148 struct cvmx_l2c_bst0_s cn58xxp1;
149};
150
151union cvmx_l2c_bst1 {
152 uint64_t u64;
153 struct cvmx_l2c_bst1_s {
154 uint64_t reserved_9_63:55;
155 uint64_t l2t:9;
156 } s;
157 struct cvmx_l2c_bst1_cn30xx {
158 uint64_t reserved_16_63:48;
159 uint64_t vwdf:4;
160 uint64_t lrf:2;
161 uint64_t vab_vwcf:1;
162 uint64_t reserved_5_8:4;
163 uint64_t l2t:5;
164 } cn30xx;
165 struct cvmx_l2c_bst1_cn30xx cn31xx;
166 struct cvmx_l2c_bst1_cn38xx {
167 uint64_t reserved_16_63:48;
168 uint64_t vwdf:4;
169 uint64_t lrf:2;
170 uint64_t vab_vwcf:1;
171 uint64_t l2t:9;
172 } cn38xx;
173 struct cvmx_l2c_bst1_cn38xx cn38xxp2;
174 struct cvmx_l2c_bst1_cn38xx cn50xx;
175 struct cvmx_l2c_bst1_cn52xx {
176 uint64_t reserved_19_63:45;
177 uint64_t plc2:1;
178 uint64_t plc1:1;
179 uint64_t plc0:1;
180 uint64_t vwdf:4;
181 uint64_t reserved_11_11:1;
182 uint64_t ilc:1;
183 uint64_t vab_vwcf:1;
184 uint64_t l2t:9;
185 } cn52xx;
186 struct cvmx_l2c_bst1_cn52xx cn52xxp1;
187 struct cvmx_l2c_bst1_cn56xx {
188 uint64_t reserved_24_63:40;
189 uint64_t plc2:1;
190 uint64_t plc1:1;
191 uint64_t plc0:1;
192 uint64_t ilc:1;
193 uint64_t vwdf1:4;
194 uint64_t vwdf0:4;
195 uint64_t vab_vwcf1:1;
196 uint64_t reserved_10_10:1;
197 uint64_t vab_vwcf0:1;
198 uint64_t l2t:9;
199 } cn56xx;
200 struct cvmx_l2c_bst1_cn56xx cn56xxp1;
201 struct cvmx_l2c_bst1_cn38xx cn58xx;
202 struct cvmx_l2c_bst1_cn38xx cn58xxp1;
203};
204
205union cvmx_l2c_bst2 {
206 uint64_t u64;
207 struct cvmx_l2c_bst2_s {
208 uint64_t reserved_16_63:48;
209 uint64_t mrb:4;
210 uint64_t reserved_4_11:8;
211 uint64_t ipcbst:1;
212 uint64_t picbst:1;
213 uint64_t xrdmsk:1;
214 uint64_t xrddat:1;
215 } s;
216 struct cvmx_l2c_bst2_cn30xx {
217 uint64_t reserved_16_63:48;
218 uint64_t mrb:4;
219 uint64_t rmdf:4;
220 uint64_t reserved_4_7:4;
221 uint64_t ipcbst:1;
222 uint64_t reserved_2_2:1;
223 uint64_t xrdmsk:1;
224 uint64_t xrddat:1;
225 } cn30xx;
226 struct cvmx_l2c_bst2_cn30xx cn31xx;
227 struct cvmx_l2c_bst2_cn38xx {
228 uint64_t reserved_16_63:48;
229 uint64_t mrb:4;
230 uint64_t rmdf:4;
231 uint64_t rhdf:4;
232 uint64_t ipcbst:1;
233 uint64_t picbst:1;
234 uint64_t xrdmsk:1;
235 uint64_t xrddat:1;
236 } cn38xx;
237 struct cvmx_l2c_bst2_cn38xx cn38xxp2;
238 struct cvmx_l2c_bst2_cn30xx cn50xx;
239 struct cvmx_l2c_bst2_cn30xx cn52xx;
240 struct cvmx_l2c_bst2_cn30xx cn52xxp1;
241 struct cvmx_l2c_bst2_cn56xx {
242 uint64_t reserved_16_63:48;
243 uint64_t mrb:4;
244 uint64_t rmdb:4;
245 uint64_t rhdb:4;
246 uint64_t ipcbst:1;
247 uint64_t picbst:1;
248 uint64_t xrdmsk:1;
249 uint64_t xrddat:1;
250 } cn56xx;
251 struct cvmx_l2c_bst2_cn56xx cn56xxp1;
252 struct cvmx_l2c_bst2_cn56xx cn58xx;
253 struct cvmx_l2c_bst2_cn56xx cn58xxp1;
254};
255
256union cvmx_l2c_cfg {
257 uint64_t u64;
258 struct cvmx_l2c_cfg_s {
259 uint64_t reserved_20_63:44;
260 uint64_t bstrun:1;
261 uint64_t lbist:1;
262 uint64_t xor_bank:1;
263 uint64_t dpres1:1;
264 uint64_t dpres0:1;
265 uint64_t dfill_dis:1;
266 uint64_t fpexp:4;
267 uint64_t fpempty:1;
268 uint64_t fpen:1;
269 uint64_t idxalias:1;
270 uint64_t mwf_crd:4;
271 uint64_t rsp_arb_mode:1;
272 uint64_t rfb_arb_mode:1;
273 uint64_t lrf_arb_mode:1;
274 } s;
275 struct cvmx_l2c_cfg_cn30xx {
276 uint64_t reserved_14_63:50;
277 uint64_t fpexp:4;
278 uint64_t fpempty:1;
279 uint64_t fpen:1;
280 uint64_t idxalias:1;
281 uint64_t mwf_crd:4;
282 uint64_t rsp_arb_mode:1;
283 uint64_t rfb_arb_mode:1;
284 uint64_t lrf_arb_mode:1;
285 } cn30xx;
286 struct cvmx_l2c_cfg_cn30xx cn31xx;
287 struct cvmx_l2c_cfg_cn30xx cn38xx;
288 struct cvmx_l2c_cfg_cn30xx cn38xxp2;
289 struct cvmx_l2c_cfg_cn50xx {
290 uint64_t reserved_20_63:44;
291 uint64_t bstrun:1;
292 uint64_t lbist:1;
293 uint64_t reserved_14_17:4;
294 uint64_t fpexp:4;
295 uint64_t fpempty:1;
296 uint64_t fpen:1;
297 uint64_t idxalias:1;
298 uint64_t mwf_crd:4;
299 uint64_t rsp_arb_mode:1;
300 uint64_t rfb_arb_mode:1;
301 uint64_t lrf_arb_mode:1;
302 } cn50xx;
303 struct cvmx_l2c_cfg_cn50xx cn52xx;
304 struct cvmx_l2c_cfg_cn50xx cn52xxp1;
305 struct cvmx_l2c_cfg_s cn56xx;
306 struct cvmx_l2c_cfg_s cn56xxp1;
307 struct cvmx_l2c_cfg_cn58xx {
308 uint64_t reserved_20_63:44;
309 uint64_t bstrun:1;
310 uint64_t lbist:1;
311 uint64_t reserved_15_17:3;
312 uint64_t dfill_dis:1;
313 uint64_t fpexp:4;
314 uint64_t fpempty:1;
315 uint64_t fpen:1;
316 uint64_t idxalias:1;
317 uint64_t mwf_crd:4;
318 uint64_t rsp_arb_mode:1;
319 uint64_t rfb_arb_mode:1;
320 uint64_t lrf_arb_mode:1;
321 } cn58xx;
322 struct cvmx_l2c_cfg_cn58xxp1 {
323 uint64_t reserved_15_63:49;
324 uint64_t dfill_dis:1;
325 uint64_t fpexp:4;
326 uint64_t fpempty:1;
327 uint64_t fpen:1;
328 uint64_t idxalias:1;
329 uint64_t mwf_crd:4;
330 uint64_t rsp_arb_mode:1;
331 uint64_t rfb_arb_mode:1;
332 uint64_t lrf_arb_mode:1;
333 } cn58xxp1;
334};
335
336union cvmx_l2c_dbg {
337 uint64_t u64;
338 struct cvmx_l2c_dbg_s {
339 uint64_t reserved_15_63:49;
340 uint64_t lfb_enum:4;
341 uint64_t lfb_dmp:1;
342 uint64_t ppnum:4;
343 uint64_t set:3;
344 uint64_t finv:1;
345 uint64_t l2d:1;
346 uint64_t l2t:1;
347 } s;
348 struct cvmx_l2c_dbg_cn30xx {
349 uint64_t reserved_13_63:51;
350 uint64_t lfb_enum:2;
351 uint64_t lfb_dmp:1;
352 uint64_t reserved_5_9:5;
353 uint64_t set:2;
354 uint64_t finv:1;
355 uint64_t l2d:1;
356 uint64_t l2t:1;
357 } cn30xx;
358 struct cvmx_l2c_dbg_cn31xx {
359 uint64_t reserved_14_63:50;
360 uint64_t lfb_enum:3;
361 uint64_t lfb_dmp:1;
362 uint64_t reserved_7_9:3;
363 uint64_t ppnum:1;
364 uint64_t reserved_5_5:1;
365 uint64_t set:2;
366 uint64_t finv:1;
367 uint64_t l2d:1;
368 uint64_t l2t:1;
369 } cn31xx;
370 struct cvmx_l2c_dbg_s cn38xx;
371 struct cvmx_l2c_dbg_s cn38xxp2;
372 struct cvmx_l2c_dbg_cn50xx {
373 uint64_t reserved_14_63:50;
374 uint64_t lfb_enum:3;
375 uint64_t lfb_dmp:1;
376 uint64_t reserved_7_9:3;
377 uint64_t ppnum:1;
378 uint64_t set:3;
379 uint64_t finv:1;
380 uint64_t l2d:1;
381 uint64_t l2t:1;
382 } cn50xx;
383 struct cvmx_l2c_dbg_cn52xx {
384 uint64_t reserved_14_63:50;
385 uint64_t lfb_enum:3;
386 uint64_t lfb_dmp:1;
387 uint64_t reserved_8_9:2;
388 uint64_t ppnum:2;
389 uint64_t set:3;
390 uint64_t finv:1;
391 uint64_t l2d:1;
392 uint64_t l2t:1;
393 } cn52xx;
394 struct cvmx_l2c_dbg_cn52xx cn52xxp1;
395 struct cvmx_l2c_dbg_s cn56xx;
396 struct cvmx_l2c_dbg_s cn56xxp1;
397 struct cvmx_l2c_dbg_s cn58xx;
398 struct cvmx_l2c_dbg_s cn58xxp1;
399};
400
401union cvmx_l2c_dut {
402 uint64_t u64;
403 struct cvmx_l2c_dut_s {
404 uint64_t reserved_32_63:32;
405 uint64_t dtena:1;
406 uint64_t reserved_30_30:1;
407 uint64_t dt_vld:1;
408 uint64_t dt_tag:29;
409 } s;
410 struct cvmx_l2c_dut_s cn30xx;
411 struct cvmx_l2c_dut_s cn31xx;
412 struct cvmx_l2c_dut_s cn38xx;
413 struct cvmx_l2c_dut_s cn38xxp2;
414 struct cvmx_l2c_dut_s cn50xx;
415 struct cvmx_l2c_dut_s cn52xx;
416 struct cvmx_l2c_dut_s cn52xxp1;
417 struct cvmx_l2c_dut_s cn56xx;
418 struct cvmx_l2c_dut_s cn56xxp1;
419 struct cvmx_l2c_dut_s cn58xx;
420 struct cvmx_l2c_dut_s cn58xxp1;
421};
422
423union cvmx_l2c_grpwrr0 {
424 uint64_t u64;
425 struct cvmx_l2c_grpwrr0_s {
426 uint64_t plc1rmsk:32;
427 uint64_t plc0rmsk:32;
428 } s;
429 struct cvmx_l2c_grpwrr0_s cn52xx;
430 struct cvmx_l2c_grpwrr0_s cn52xxp1;
431 struct cvmx_l2c_grpwrr0_s cn56xx;
432 struct cvmx_l2c_grpwrr0_s cn56xxp1;
433};
434
435union cvmx_l2c_grpwrr1 {
436 uint64_t u64;
437 struct cvmx_l2c_grpwrr1_s {
438 uint64_t ilcrmsk:32;
439 uint64_t plc2rmsk:32;
440 } s;
441 struct cvmx_l2c_grpwrr1_s cn52xx;
442 struct cvmx_l2c_grpwrr1_s cn52xxp1;
443 struct cvmx_l2c_grpwrr1_s cn56xx;
444 struct cvmx_l2c_grpwrr1_s cn56xxp1;
445};
446
447union cvmx_l2c_int_en {
448 uint64_t u64;
449 struct cvmx_l2c_int_en_s {
450 uint64_t reserved_9_63:55;
451 uint64_t lck2ena:1;
452 uint64_t lckena:1;
453 uint64_t l2ddeden:1;
454 uint64_t l2dsecen:1;
455 uint64_t l2tdeden:1;
456 uint64_t l2tsecen:1;
457 uint64_t oob3en:1;
458 uint64_t oob2en:1;
459 uint64_t oob1en:1;
460 } s;
461 struct cvmx_l2c_int_en_s cn52xx;
462 struct cvmx_l2c_int_en_s cn52xxp1;
463 struct cvmx_l2c_int_en_s cn56xx;
464 struct cvmx_l2c_int_en_s cn56xxp1;
465};
466
467union cvmx_l2c_int_stat {
468 uint64_t u64;
469 struct cvmx_l2c_int_stat_s {
470 uint64_t reserved_9_63:55;
471 uint64_t lck2:1;
472 uint64_t lck:1;
473 uint64_t l2dded:1;
474 uint64_t l2dsec:1;
475 uint64_t l2tded:1;
476 uint64_t l2tsec:1;
477 uint64_t oob3:1;
478 uint64_t oob2:1;
479 uint64_t oob1:1;
480 } s;
481 struct cvmx_l2c_int_stat_s cn52xx;
482 struct cvmx_l2c_int_stat_s cn52xxp1;
483 struct cvmx_l2c_int_stat_s cn56xx;
484 struct cvmx_l2c_int_stat_s cn56xxp1;
485};
486
487union cvmx_l2c_lckbase {
488 uint64_t u64;
489 struct cvmx_l2c_lckbase_s {
490 uint64_t reserved_31_63:33;
491 uint64_t lck_base:27;
492 uint64_t reserved_1_3:3;
493 uint64_t lck_ena:1;
494 } s;
495 struct cvmx_l2c_lckbase_s cn30xx;
496 struct cvmx_l2c_lckbase_s cn31xx;
497 struct cvmx_l2c_lckbase_s cn38xx;
498 struct cvmx_l2c_lckbase_s cn38xxp2;
499 struct cvmx_l2c_lckbase_s cn50xx;
500 struct cvmx_l2c_lckbase_s cn52xx;
501 struct cvmx_l2c_lckbase_s cn52xxp1;
502 struct cvmx_l2c_lckbase_s cn56xx;
503 struct cvmx_l2c_lckbase_s cn56xxp1;
504 struct cvmx_l2c_lckbase_s cn58xx;
505 struct cvmx_l2c_lckbase_s cn58xxp1;
506};
507
508union cvmx_l2c_lckoff {
509 uint64_t u64;
510 struct cvmx_l2c_lckoff_s {
511 uint64_t reserved_10_63:54;
512 uint64_t lck_offset:10;
513 } s;
514 struct cvmx_l2c_lckoff_s cn30xx;
515 struct cvmx_l2c_lckoff_s cn31xx;
516 struct cvmx_l2c_lckoff_s cn38xx;
517 struct cvmx_l2c_lckoff_s cn38xxp2;
518 struct cvmx_l2c_lckoff_s cn50xx;
519 struct cvmx_l2c_lckoff_s cn52xx;
520 struct cvmx_l2c_lckoff_s cn52xxp1;
521 struct cvmx_l2c_lckoff_s cn56xx;
522 struct cvmx_l2c_lckoff_s cn56xxp1;
523 struct cvmx_l2c_lckoff_s cn58xx;
524 struct cvmx_l2c_lckoff_s cn58xxp1;
525};
526
527union cvmx_l2c_lfb0 {
528 uint64_t u64;
529 struct cvmx_l2c_lfb0_s {
530 uint64_t reserved_32_63:32;
531 uint64_t stcpnd:1;
532 uint64_t stpnd:1;
533 uint64_t stinv:1;
534 uint64_t stcfl:1;
535 uint64_t vam:1;
536 uint64_t inxt:4;
537 uint64_t itl:1;
538 uint64_t ihd:1;
539 uint64_t set:3;
540 uint64_t vabnum:4;
541 uint64_t sid:9;
542 uint64_t cmd:4;
543 uint64_t vld:1;
544 } s;
545 struct cvmx_l2c_lfb0_cn30xx {
546 uint64_t reserved_32_63:32;
547 uint64_t stcpnd:1;
548 uint64_t stpnd:1;
549 uint64_t stinv:1;
550 uint64_t stcfl:1;
551 uint64_t vam:1;
552 uint64_t reserved_25_26:2;
553 uint64_t inxt:2;
554 uint64_t itl:1;
555 uint64_t ihd:1;
556 uint64_t reserved_20_20:1;
557 uint64_t set:2;
558 uint64_t reserved_16_17:2;
559 uint64_t vabnum:2;
560 uint64_t sid:9;
561 uint64_t cmd:4;
562 uint64_t vld:1;
563 } cn30xx;
564 struct cvmx_l2c_lfb0_cn31xx {
565 uint64_t reserved_32_63:32;
566 uint64_t stcpnd:1;
567 uint64_t stpnd:1;
568 uint64_t stinv:1;
569 uint64_t stcfl:1;
570 uint64_t vam:1;
571 uint64_t reserved_26_26:1;
572 uint64_t inxt:3;
573 uint64_t itl:1;
574 uint64_t ihd:1;
575 uint64_t reserved_20_20:1;
576 uint64_t set:2;
577 uint64_t reserved_17_17:1;
578 uint64_t vabnum:3;
579 uint64_t sid:9;
580 uint64_t cmd:4;
581 uint64_t vld:1;
582 } cn31xx;
583 struct cvmx_l2c_lfb0_s cn38xx;
584 struct cvmx_l2c_lfb0_s cn38xxp2;
585 struct cvmx_l2c_lfb0_cn50xx {
586 uint64_t reserved_32_63:32;
587 uint64_t stcpnd:1;
588 uint64_t stpnd:1;
589 uint64_t stinv:1;
590 uint64_t stcfl:1;
591 uint64_t vam:1;
592 uint64_t reserved_26_26:1;
593 uint64_t inxt:3;
594 uint64_t itl:1;
595 uint64_t ihd:1;
596 uint64_t set:3;
597 uint64_t reserved_17_17:1;
598 uint64_t vabnum:3;
599 uint64_t sid:9;
600 uint64_t cmd:4;
601 uint64_t vld:1;
602 } cn50xx;
603 struct cvmx_l2c_lfb0_cn50xx cn52xx;
604 struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
605 struct cvmx_l2c_lfb0_s cn56xx;
606 struct cvmx_l2c_lfb0_s cn56xxp1;
607 struct cvmx_l2c_lfb0_s cn58xx;
608 struct cvmx_l2c_lfb0_s cn58xxp1;
609};
610
611union cvmx_l2c_lfb1 {
612 uint64_t u64;
613 struct cvmx_l2c_lfb1_s {
614 uint64_t reserved_19_63:45;
615 uint64_t dsgoing:1;
616 uint64_t bid:2;
617 uint64_t wtrsp:1;
618 uint64_t wtdw:1;
619 uint64_t wtdq:1;
620 uint64_t wtwhp:1;
621 uint64_t wtwhf:1;
622 uint64_t wtwrm:1;
623 uint64_t wtstm:1;
624 uint64_t wtrda:1;
625 uint64_t wtstdt:1;
626 uint64_t wtstrsp:1;
627 uint64_t wtstrsc:1;
628 uint64_t wtvtm:1;
629 uint64_t wtmfl:1;
630 uint64_t prbrty:1;
631 uint64_t wtprb:1;
632 uint64_t vld:1;
633 } s;
634 struct cvmx_l2c_lfb1_s cn30xx;
635 struct cvmx_l2c_lfb1_s cn31xx;
636 struct cvmx_l2c_lfb1_s cn38xx;
637 struct cvmx_l2c_lfb1_s cn38xxp2;
638 struct cvmx_l2c_lfb1_s cn50xx;
639 struct cvmx_l2c_lfb1_s cn52xx;
640 struct cvmx_l2c_lfb1_s cn52xxp1;
641 struct cvmx_l2c_lfb1_s cn56xx;
642 struct cvmx_l2c_lfb1_s cn56xxp1;
643 struct cvmx_l2c_lfb1_s cn58xx;
644 struct cvmx_l2c_lfb1_s cn58xxp1;
645};
646
647union cvmx_l2c_lfb2 {
648 uint64_t u64;
649 struct cvmx_l2c_lfb2_s {
650 uint64_t reserved_0_63:64;
651 } s;
652 struct cvmx_l2c_lfb2_cn30xx {
653 uint64_t reserved_27_63:37;
654 uint64_t lfb_tag:19;
655 uint64_t lfb_idx:8;
656 } cn30xx;
657 struct cvmx_l2c_lfb2_cn31xx {
658 uint64_t reserved_27_63:37;
659 uint64_t lfb_tag:17;
660 uint64_t lfb_idx:10;
661 } cn31xx;
662 struct cvmx_l2c_lfb2_cn31xx cn38xx;
663 struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
664 struct cvmx_l2c_lfb2_cn50xx {
665 uint64_t reserved_27_63:37;
666 uint64_t lfb_tag:20;
667 uint64_t lfb_idx:7;
668 } cn50xx;
669 struct cvmx_l2c_lfb2_cn52xx {
670 uint64_t reserved_27_63:37;
671 uint64_t lfb_tag:18;
672 uint64_t lfb_idx:9;
673 } cn52xx;
674 struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
675 struct cvmx_l2c_lfb2_cn56xx {
676 uint64_t reserved_27_63:37;
677 uint64_t lfb_tag:16;
678 uint64_t lfb_idx:11;
679 } cn56xx;
680 struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
681 struct cvmx_l2c_lfb2_cn56xx cn58xx;
682 struct cvmx_l2c_lfb2_cn56xx cn58xxp1;
683};
684
685union cvmx_l2c_lfb3 {
686 uint64_t u64;
687 struct cvmx_l2c_lfb3_s {
688 uint64_t reserved_5_63:59;
689 uint64_t stpartdis:1;
690 uint64_t lfb_hwm:4;
691 } s;
692 struct cvmx_l2c_lfb3_cn30xx {
693 uint64_t reserved_5_63:59;
694 uint64_t stpartdis:1;
695 uint64_t reserved_2_3:2;
696 uint64_t lfb_hwm:2;
697 } cn30xx;
698 struct cvmx_l2c_lfb3_cn31xx {
699 uint64_t reserved_5_63:59;
700 uint64_t stpartdis:1;
701 uint64_t reserved_3_3:1;
702 uint64_t lfb_hwm:3;
703 } cn31xx;
704 struct cvmx_l2c_lfb3_s cn38xx;
705 struct cvmx_l2c_lfb3_s cn38xxp2;
706 struct cvmx_l2c_lfb3_cn31xx cn50xx;
707 struct cvmx_l2c_lfb3_cn31xx cn52xx;
708 struct cvmx_l2c_lfb3_cn31xx cn52xxp1;
709 struct cvmx_l2c_lfb3_s cn56xx;
710 struct cvmx_l2c_lfb3_s cn56xxp1;
711 struct cvmx_l2c_lfb3_s cn58xx;
712 struct cvmx_l2c_lfb3_s cn58xxp1;
713};
714
715union cvmx_l2c_oob {
716 uint64_t u64;
717 struct cvmx_l2c_oob_s {
718 uint64_t reserved_2_63:62;
719 uint64_t dwbena:1;
720 uint64_t stena:1;
721 } s;
722 struct cvmx_l2c_oob_s cn52xx;
723 struct cvmx_l2c_oob_s cn52xxp1;
724 struct cvmx_l2c_oob_s cn56xx;
725 struct cvmx_l2c_oob_s cn56xxp1;
726};
727
728union cvmx_l2c_oob1 {
729 uint64_t u64;
730 struct cvmx_l2c_oob1_s {
731 uint64_t fadr:27;
732 uint64_t fsrc:1;
733 uint64_t reserved_34_35:2;
734 uint64_t sadr:14;
735 uint64_t reserved_14_19:6;
736 uint64_t size:14;
737 } s;
738 struct cvmx_l2c_oob1_s cn52xx;
739 struct cvmx_l2c_oob1_s cn52xxp1;
740 struct cvmx_l2c_oob1_s cn56xx;
741 struct cvmx_l2c_oob1_s cn56xxp1;
742};
743
744union cvmx_l2c_oob2 {
745 uint64_t u64;
746 struct cvmx_l2c_oob2_s {
747 uint64_t fadr:27;
748 uint64_t fsrc:1;
749 uint64_t reserved_34_35:2;
750 uint64_t sadr:14;
751 uint64_t reserved_14_19:6;
752 uint64_t size:14;
753 } s;
754 struct cvmx_l2c_oob2_s cn52xx;
755 struct cvmx_l2c_oob2_s cn52xxp1;
756 struct cvmx_l2c_oob2_s cn56xx;
757 struct cvmx_l2c_oob2_s cn56xxp1;
758};
759
760union cvmx_l2c_oob3 {
761 uint64_t u64;
762 struct cvmx_l2c_oob3_s {
763 uint64_t fadr:27;
764 uint64_t fsrc:1;
765 uint64_t reserved_34_35:2;
766 uint64_t sadr:14;
767 uint64_t reserved_14_19:6;
768 uint64_t size:14;
769 } s;
770 struct cvmx_l2c_oob3_s cn52xx;
771 struct cvmx_l2c_oob3_s cn52xxp1;
772 struct cvmx_l2c_oob3_s cn56xx;
773 struct cvmx_l2c_oob3_s cn56xxp1;
774};
775
776union cvmx_l2c_pfcx {
777 uint64_t u64;
778 struct cvmx_l2c_pfcx_s {
779 uint64_t reserved_36_63:28;
780 uint64_t pfcnt0:36;
781 } s;
782 struct cvmx_l2c_pfcx_s cn30xx;
783 struct cvmx_l2c_pfcx_s cn31xx;
784 struct cvmx_l2c_pfcx_s cn38xx;
785 struct cvmx_l2c_pfcx_s cn38xxp2;
786 struct cvmx_l2c_pfcx_s cn50xx;
787 struct cvmx_l2c_pfcx_s cn52xx;
788 struct cvmx_l2c_pfcx_s cn52xxp1;
789 struct cvmx_l2c_pfcx_s cn56xx;
790 struct cvmx_l2c_pfcx_s cn56xxp1;
791 struct cvmx_l2c_pfcx_s cn58xx;
792 struct cvmx_l2c_pfcx_s cn58xxp1;
793};
794
795union cvmx_l2c_pfctl {
796 uint64_t u64;
797 struct cvmx_l2c_pfctl_s {
798 uint64_t reserved_36_63:28;
799 uint64_t cnt3rdclr:1;
800 uint64_t cnt2rdclr:1;
801 uint64_t cnt1rdclr:1;
802 uint64_t cnt0rdclr:1;
803 uint64_t cnt3ena:1;
804 uint64_t cnt3clr:1;
805 uint64_t cnt3sel:6;
806 uint64_t cnt2ena:1;
807 uint64_t cnt2clr:1;
808 uint64_t cnt2sel:6;
809 uint64_t cnt1ena:1;
810 uint64_t cnt1clr:1;
811 uint64_t cnt1sel:6;
812 uint64_t cnt0ena:1;
813 uint64_t cnt0clr:1;
814 uint64_t cnt0sel:6;
815 } s;
816 struct cvmx_l2c_pfctl_s cn30xx;
817 struct cvmx_l2c_pfctl_s cn31xx;
818 struct cvmx_l2c_pfctl_s cn38xx;
819 struct cvmx_l2c_pfctl_s cn38xxp2;
820 struct cvmx_l2c_pfctl_s cn50xx;
821 struct cvmx_l2c_pfctl_s cn52xx;
822 struct cvmx_l2c_pfctl_s cn52xxp1;
823 struct cvmx_l2c_pfctl_s cn56xx;
824 struct cvmx_l2c_pfctl_s cn56xxp1;
825 struct cvmx_l2c_pfctl_s cn58xx;
826 struct cvmx_l2c_pfctl_s cn58xxp1;
827};
828
829union cvmx_l2c_ppgrp {
830 uint64_t u64;
831 struct cvmx_l2c_ppgrp_s {
832 uint64_t reserved_24_63:40;
833 uint64_t pp11grp:2;
834 uint64_t pp10grp:2;
835 uint64_t pp9grp:2;
836 uint64_t pp8grp:2;
837 uint64_t pp7grp:2;
838 uint64_t pp6grp:2;
839 uint64_t pp5grp:2;
840 uint64_t pp4grp:2;
841 uint64_t pp3grp:2;
842 uint64_t pp2grp:2;
843 uint64_t pp1grp:2;
844 uint64_t pp0grp:2;
845 } s;
846 struct cvmx_l2c_ppgrp_cn52xx {
847 uint64_t reserved_8_63:56;
848 uint64_t pp3grp:2;
849 uint64_t pp2grp:2;
850 uint64_t pp1grp:2;
851 uint64_t pp0grp:2;
852 } cn52xx;
853 struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
854 struct cvmx_l2c_ppgrp_s cn56xx;
855 struct cvmx_l2c_ppgrp_s cn56xxp1;
856};
857
858union cvmx_l2c_spar0 {
859 uint64_t u64;
860 struct cvmx_l2c_spar0_s {
861 uint64_t reserved_32_63:32;
862 uint64_t umsk3:8;
863 uint64_t umsk2:8;
864 uint64_t umsk1:8;
865 uint64_t umsk0:8;
866 } s;
867 struct cvmx_l2c_spar0_cn30xx {
868 uint64_t reserved_4_63:60;
869 uint64_t umsk0:4;
870 } cn30xx;
871 struct cvmx_l2c_spar0_cn31xx {
872 uint64_t reserved_12_63:52;
873 uint64_t umsk1:4;
874 uint64_t reserved_4_7:4;
875 uint64_t umsk0:4;
876 } cn31xx;
877 struct cvmx_l2c_spar0_s cn38xx;
878 struct cvmx_l2c_spar0_s cn38xxp2;
879 struct cvmx_l2c_spar0_cn50xx {
880 uint64_t reserved_16_63:48;
881 uint64_t umsk1:8;
882 uint64_t umsk0:8;
883 } cn50xx;
884 struct cvmx_l2c_spar0_s cn52xx;
885 struct cvmx_l2c_spar0_s cn52xxp1;
886 struct cvmx_l2c_spar0_s cn56xx;
887 struct cvmx_l2c_spar0_s cn56xxp1;
888 struct cvmx_l2c_spar0_s cn58xx;
889 struct cvmx_l2c_spar0_s cn58xxp1;
890};
891
892union cvmx_l2c_spar1 {
893 uint64_t u64;
894 struct cvmx_l2c_spar1_s {
895 uint64_t reserved_32_63:32;
896 uint64_t umsk7:8;
897 uint64_t umsk6:8;
898 uint64_t umsk5:8;
899 uint64_t umsk4:8;
900 } s;
901 struct cvmx_l2c_spar1_s cn38xx;
902 struct cvmx_l2c_spar1_s cn38xxp2;
903 struct cvmx_l2c_spar1_s cn56xx;
904 struct cvmx_l2c_spar1_s cn56xxp1;
905 struct cvmx_l2c_spar1_s cn58xx;
906 struct cvmx_l2c_spar1_s cn58xxp1;
907};
908
909union cvmx_l2c_spar2 {
910 uint64_t u64;
911 struct cvmx_l2c_spar2_s {
912 uint64_t reserved_32_63:32;
913 uint64_t umsk11:8;
914 uint64_t umsk10:8;
915 uint64_t umsk9:8;
916 uint64_t umsk8:8;
917 } s;
918 struct cvmx_l2c_spar2_s cn38xx;
919 struct cvmx_l2c_spar2_s cn38xxp2;
920 struct cvmx_l2c_spar2_s cn56xx;
921 struct cvmx_l2c_spar2_s cn56xxp1;
922 struct cvmx_l2c_spar2_s cn58xx;
923 struct cvmx_l2c_spar2_s cn58xxp1;
924};
925
926union cvmx_l2c_spar3 {
927 uint64_t u64;
928 struct cvmx_l2c_spar3_s {
929 uint64_t reserved_32_63:32;
930 uint64_t umsk15:8;
931 uint64_t umsk14:8;
932 uint64_t umsk13:8;
933 uint64_t umsk12:8;
934 } s;
935 struct cvmx_l2c_spar3_s cn38xx;
936 struct cvmx_l2c_spar3_s cn38xxp2;
937 struct cvmx_l2c_spar3_s cn58xx;
938 struct cvmx_l2c_spar3_s cn58xxp1;
939};
940
941union cvmx_l2c_spar4 {
942 uint64_t u64;
943 struct cvmx_l2c_spar4_s {
944 uint64_t reserved_8_63:56;
945 uint64_t umskiob:8;
946 } s;
947 struct cvmx_l2c_spar4_cn30xx {
948 uint64_t reserved_4_63:60;
949 uint64_t umskiob:4;
950 } cn30xx;
951 struct cvmx_l2c_spar4_cn30xx cn31xx;
952 struct cvmx_l2c_spar4_s cn38xx;
953 struct cvmx_l2c_spar4_s cn38xxp2;
954 struct cvmx_l2c_spar4_s cn50xx;
955 struct cvmx_l2c_spar4_s cn52xx;
956 struct cvmx_l2c_spar4_s cn52xxp1;
957 struct cvmx_l2c_spar4_s cn56xx;
958 struct cvmx_l2c_spar4_s cn56xxp1;
959 struct cvmx_l2c_spar4_s cn58xx;
960 struct cvmx_l2c_spar4_s cn58xxp1;
961};
962
963#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
new file mode 100644
index 000000000000..2a8c0902ea50
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -0,0 +1,325 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
31 * facilities.
32 */
33
34#ifndef __CVMX_L2C_H__
35#define __CVMX_L2C_H__
36
37/* Deprecated macro, use function */
38#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
39
40/* Deprecated macro, use function */
41#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
42
43/* Deprecated macro, use function */
44#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
45
46#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
47#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
48
49/* Defines for index aliasing computations */
50#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
51 (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
52
53#define CVMX_L2C_ALIAS_MASK \
54 (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
55
56union cvmx_l2c_tag {
57 uint64_t u64;
58 struct {
59 uint64_t reserved:28;
60 uint64_t V:1; /* Line valid */
61 uint64_t D:1; /* Line dirty */
62 uint64_t L:1; /* Line locked */
63 uint64_t U:1; /* Use, LRU eviction */
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 } s;
66};
67
68 /* L2C Performance Counter events. */
69enum cvmx_l2c_event {
70 CVMX_L2C_EVENT_CYCLES = 0,
71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
73 CVMX_L2C_EVENT_DATA_MISS = 3,
74 CVMX_L2C_EVENT_DATA_HIT = 4,
75 CVMX_L2C_EVENT_MISS = 5,
76 CVMX_L2C_EVENT_HIT = 6,
77 CVMX_L2C_EVENT_VICTIM_HIT = 7,
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
79 CVMX_L2C_EVENT_TAG_PROBE = 9,
80 CVMX_L2C_EVENT_TAG_UPDATE = 10,
81 CVMX_L2C_EVENT_TAG_COMPLETE = 11,
82 CVMX_L2C_EVENT_TAG_DIRTY = 12,
83 CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
84 CVMX_L2C_EVENT_DATA_STORE_READ = 14,
85 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
86 CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
87 CVMX_L2C_EVENT_WRITE_REQUEST = 17,
88 CVMX_L2C_EVENT_READ_REQUEST = 18,
89 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
90 CVMX_L2C_EVENT_XMC_NOP = 20,
91 CVMX_L2C_EVENT_XMC_LDT = 21,
92 CVMX_L2C_EVENT_XMC_LDI = 22,
93 CVMX_L2C_EVENT_XMC_LDD = 23,
94 CVMX_L2C_EVENT_XMC_STF = 24,
95 CVMX_L2C_EVENT_XMC_STT = 25,
96 CVMX_L2C_EVENT_XMC_STP = 26,
97 CVMX_L2C_EVENT_XMC_STC = 27,
98 CVMX_L2C_EVENT_XMC_DWB = 28,
99 CVMX_L2C_EVENT_XMC_PL2 = 29,
100 CVMX_L2C_EVENT_XMC_PSL1 = 30,
101 CVMX_L2C_EVENT_XMC_IOBLD = 31,
102 CVMX_L2C_EVENT_XMC_IOBST = 32,
103 CVMX_L2C_EVENT_XMC_IOBDMA = 33,
104 CVMX_L2C_EVENT_XMC_IOBRSP = 34,
105 CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
106 CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
107 CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
108 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
109 CVMX_L2C_EVENT_RSC_NOP = 39,
110 CVMX_L2C_EVENT_RSC_STDN = 40,
111 CVMX_L2C_EVENT_RSC_FILL = 41,
112 CVMX_L2C_EVENT_RSC_REFL = 42,
113 CVMX_L2C_EVENT_RSC_STIN = 43,
114 CVMX_L2C_EVENT_RSC_SCIN = 44,
115 CVMX_L2C_EVENT_RSC_SCFL = 45,
116 CVMX_L2C_EVENT_RSC_SCDN = 46,
117 CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
118 CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
119 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
120 CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
121 CVMX_L2C_EVENT_LRF_REQ = 51,
122 CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
123 CVMX_L2C_EVENT_DT_WR_INVAL = 53
124};
125
126/**
127 * Configure one of the four L2 Cache performance counters to capture event
128 * occurences.
129 *
130 * @counter: The counter to configure. Range 0..3.
131 * @event: The type of L2 Cache event occurrence to count.
132 * @clear_on_read: When asserted, any read of the performance counter
133 * clears the counter.
134 *
135 * The routine does not clear the counter.
136 */
137void cvmx_l2c_config_perf(uint32_t counter,
138 enum cvmx_l2c_event event, uint32_t clear_on_read);
139/**
140 * Read the given L2 Cache performance counter. The counter must be configured
141 * before reading, but this routine does not enforce this requirement.
142 *
143 * @counter: The counter to configure. Range 0..3.
144 *
145 * Returns The current counter value.
146 */
147uint64_t cvmx_l2c_read_perf(uint32_t counter);
148
149/**
150 * Return the L2 Cache way partitioning for a given core.
151 *
152 * @core: The core processor of interest.
153 *
154 * Returns The mask specifying the partitioning. 0 bits in mask indicates
155 * the cache 'ways' that a core can evict from.
156 * -1 on error
157 */
158int cvmx_l2c_get_core_way_partition(uint32_t core);
159
160/**
161 * Partitions the L2 cache for a core
162 *
163 * @core: The core that the partitioning applies to.
164 *
165 * @mask: The partitioning of the ways expressed as a binary mask. A 0
166 * bit allows the core to evict cache lines from a way, while a
167 * 1 bit blocks the core from evicting any lines from that
168 * way. There must be at least one allowed way (0 bit) in the
169 * mask.
170 *
171 * If any ways are blocked for all cores and the HW blocks, then those
172 * ways will never have any cache lines evicted from them. All cores
173 * and the hardware blocks are free to read from all ways regardless
174 * of the partitioning.
175 */
176int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
177
178/**
179 * Return the L2 Cache way partitioning for the hw blocks.
180 *
181 * Returns The mask specifying the reserved way. 0 bits in mask indicates
182 * the cache 'ways' that a core can evict from.
183 * -1 on error
184 */
185int cvmx_l2c_get_hw_way_partition(void);
186
187/**
188 * Partitions the L2 cache for the hardware blocks.
189 *
190 * @mask: The partitioning of the ways expressed as a binary mask. A 0
191 * bit allows the core to evict cache lines from a way, while a
192 * 1 bit blocks the core from evicting any lines from that
193 * way. There must be at least one allowed way (0 bit) in the
194 * mask.
195 *
196 * If any ways are blocked for all cores and the HW blocks, then those
197 * ways will never have any cache lines evicted from them. All cores
198 * and the hardware blocks are free to read from all ways regardless
199 * of the partitioning.
200 */
201int cvmx_l2c_set_hw_way_partition(uint32_t mask);
202
203/**
204 * Locks a line in the L2 cache at the specified physical address
205 *
206 * @addr: physical address of line to lock
207 *
208 * Returns 0 on success,
209 * 1 if line not locked.
210 */
211int cvmx_l2c_lock_line(uint64_t addr);
212
213/**
214 * Locks a specified memory region in the L2 cache.
215 *
216 * Note that if not all lines can be locked, that means that all
217 * but one of the ways (associations) available to the locking
218 * core are locked. Having only 1 association available for
219 * normal caching may have a significant adverse affect on performance.
220 * Care should be taken to ensure that enough of the L2 cache is left
221 * unlocked to allow for normal caching of DRAM.
222 *
223 * @start: Physical address of the start of the region to lock
224 * @len: Length (in bytes) of region to lock
225 *
226 * Returns Number of requested lines that where not locked.
227 * 0 on success (all locked)
228 */
229int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
230
231/**
232 * Unlock and flush a cache line from the L2 cache.
233 * IMPORTANT: Must only be run by one core at a time due to use
234 * of L2C debug features.
235 * Note that this function will flush a matching but unlocked cache line.
236 * (If address is not in L2, no lines are flushed.)
237 *
238 * @address: Physical address to unlock
239 *
240 * Returns 0: line not unlocked
241 * 1: line unlocked
242 */
243int cvmx_l2c_unlock_line(uint64_t address);
244
245/**
246 * Unlocks a region of memory that is locked in the L2 cache
247 *
248 * @start: start physical address
249 * @len: length (in bytes) to unlock
250 *
251 * Returns Number of locked lines that the call unlocked
252 */
253int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
254
255/**
256 * Read the L2 controller tag for a given location in L2
257 *
258 * @association:
259 * Which association to read line from
260 * @index: Which way to read from.
261 *
262 * Returns l2c tag structure for line requested.
263 */
264union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
265
266/* Wrapper around deprecated old function name */
267static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
268 uint32_t index)
269{
270 return cvmx_l2c_get_tag(association, index);
271}
272
273/**
274 * Returns the cache index for a given physical address
275 *
276 * @addr: physical address
277 *
278 * Returns L2 cache index
279 */
280uint32_t cvmx_l2c_address_to_index(uint64_t addr);
281
282/**
283 * Flushes (and unlocks) the entire L2 cache.
284 * IMPORTANT: Must only be run by one core at a time due to use
285 * of L2C debug features.
286 */
287void cvmx_l2c_flush(void);
288
289/**
290 *
291 * Returns Returns the size of the L2 cache in bytes,
292 * -1 on error (unrecognized model)
293 */
294int cvmx_l2c_get_cache_size_bytes(void);
295
296/**
297 * Return the number of sets in the L2 Cache
298 *
299 * Returns
300 */
301int cvmx_l2c_get_num_sets(void);
302
303/**
304 * Return log base 2 of the number of sets in the L2 cache
305 * Returns
306 */
307int cvmx_l2c_get_set_bits(void);
308/**
309 * Return the number of associations in the L2 Cache
310 *
311 * Returns
312 */
313int cvmx_l2c_get_num_assoc(void);
314
315/**
316 * Flush a line from the L2 cache
317 * This should only be called from one core at a time, as this routine
318 * sets the core to the 'debug' core in order to flush the line.
319 *
320 * @assoc: Association (or way) to flush
321 * @index: Index to flush
322 */
323void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
324
325#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
new file mode 100644
index 000000000000..d7102d455e1b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -0,0 +1,369 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2D_DEFS_H__
29#define __CVMX_L2D_DEFS_H__
30
31#define CVMX_L2D_BST0 \
32 CVMX_ADD_IO_SEG(0x0001180080000780ull)
33#define CVMX_L2D_BST1 \
34 CVMX_ADD_IO_SEG(0x0001180080000788ull)
35#define CVMX_L2D_BST2 \
36 CVMX_ADD_IO_SEG(0x0001180080000790ull)
37#define CVMX_L2D_BST3 \
38 CVMX_ADD_IO_SEG(0x0001180080000798ull)
39#define CVMX_L2D_ERR \
40 CVMX_ADD_IO_SEG(0x0001180080000010ull)
41#define CVMX_L2D_FADR \
42 CVMX_ADD_IO_SEG(0x0001180080000018ull)
43#define CVMX_L2D_FSYN0 \
44 CVMX_ADD_IO_SEG(0x0001180080000020ull)
45#define CVMX_L2D_FSYN1 \
46 CVMX_ADD_IO_SEG(0x0001180080000028ull)
47#define CVMX_L2D_FUS0 \
48 CVMX_ADD_IO_SEG(0x00011800800007A0ull)
49#define CVMX_L2D_FUS1 \
50 CVMX_ADD_IO_SEG(0x00011800800007A8ull)
51#define CVMX_L2D_FUS2 \
52 CVMX_ADD_IO_SEG(0x00011800800007B0ull)
53#define CVMX_L2D_FUS3 \
54 CVMX_ADD_IO_SEG(0x00011800800007B8ull)
55
56union cvmx_l2d_bst0 {
57 uint64_t u64;
58 struct cvmx_l2d_bst0_s {
59 uint64_t reserved_35_63:29;
60 uint64_t ftl:1;
61 uint64_t q0stat:34;
62 } s;
63 struct cvmx_l2d_bst0_s cn30xx;
64 struct cvmx_l2d_bst0_s cn31xx;
65 struct cvmx_l2d_bst0_s cn38xx;
66 struct cvmx_l2d_bst0_s cn38xxp2;
67 struct cvmx_l2d_bst0_s cn50xx;
68 struct cvmx_l2d_bst0_s cn52xx;
69 struct cvmx_l2d_bst0_s cn52xxp1;
70 struct cvmx_l2d_bst0_s cn56xx;
71 struct cvmx_l2d_bst0_s cn56xxp1;
72 struct cvmx_l2d_bst0_s cn58xx;
73 struct cvmx_l2d_bst0_s cn58xxp1;
74};
75
76union cvmx_l2d_bst1 {
77 uint64_t u64;
78 struct cvmx_l2d_bst1_s {
79 uint64_t reserved_34_63:30;
80 uint64_t q1stat:34;
81 } s;
82 struct cvmx_l2d_bst1_s cn30xx;
83 struct cvmx_l2d_bst1_s cn31xx;
84 struct cvmx_l2d_bst1_s cn38xx;
85 struct cvmx_l2d_bst1_s cn38xxp2;
86 struct cvmx_l2d_bst1_s cn50xx;
87 struct cvmx_l2d_bst1_s cn52xx;
88 struct cvmx_l2d_bst1_s cn52xxp1;
89 struct cvmx_l2d_bst1_s cn56xx;
90 struct cvmx_l2d_bst1_s cn56xxp1;
91 struct cvmx_l2d_bst1_s cn58xx;
92 struct cvmx_l2d_bst1_s cn58xxp1;
93};
94
95union cvmx_l2d_bst2 {
96 uint64_t u64;
97 struct cvmx_l2d_bst2_s {
98 uint64_t reserved_34_63:30;
99 uint64_t q2stat:34;
100 } s;
101 struct cvmx_l2d_bst2_s cn30xx;
102 struct cvmx_l2d_bst2_s cn31xx;
103 struct cvmx_l2d_bst2_s cn38xx;
104 struct cvmx_l2d_bst2_s cn38xxp2;
105 struct cvmx_l2d_bst2_s cn50xx;
106 struct cvmx_l2d_bst2_s cn52xx;
107 struct cvmx_l2d_bst2_s cn52xxp1;
108 struct cvmx_l2d_bst2_s cn56xx;
109 struct cvmx_l2d_bst2_s cn56xxp1;
110 struct cvmx_l2d_bst2_s cn58xx;
111 struct cvmx_l2d_bst2_s cn58xxp1;
112};
113
114union cvmx_l2d_bst3 {
115 uint64_t u64;
116 struct cvmx_l2d_bst3_s {
117 uint64_t reserved_34_63:30;
118 uint64_t q3stat:34;
119 } s;
120 struct cvmx_l2d_bst3_s cn30xx;
121 struct cvmx_l2d_bst3_s cn31xx;
122 struct cvmx_l2d_bst3_s cn38xx;
123 struct cvmx_l2d_bst3_s cn38xxp2;
124 struct cvmx_l2d_bst3_s cn50xx;
125 struct cvmx_l2d_bst3_s cn52xx;
126 struct cvmx_l2d_bst3_s cn52xxp1;
127 struct cvmx_l2d_bst3_s cn56xx;
128 struct cvmx_l2d_bst3_s cn56xxp1;
129 struct cvmx_l2d_bst3_s cn58xx;
130 struct cvmx_l2d_bst3_s cn58xxp1;
131};
132
133union cvmx_l2d_err {
134 uint64_t u64;
135 struct cvmx_l2d_err_s {
136 uint64_t reserved_6_63:58;
137 uint64_t bmhclsel:1;
138 uint64_t ded_err:1;
139 uint64_t sec_err:1;
140 uint64_t ded_intena:1;
141 uint64_t sec_intena:1;
142 uint64_t ecc_ena:1;
143 } s;
144 struct cvmx_l2d_err_s cn30xx;
145 struct cvmx_l2d_err_s cn31xx;
146 struct cvmx_l2d_err_s cn38xx;
147 struct cvmx_l2d_err_s cn38xxp2;
148 struct cvmx_l2d_err_s cn50xx;
149 struct cvmx_l2d_err_s cn52xx;
150 struct cvmx_l2d_err_s cn52xxp1;
151 struct cvmx_l2d_err_s cn56xx;
152 struct cvmx_l2d_err_s cn56xxp1;
153 struct cvmx_l2d_err_s cn58xx;
154 struct cvmx_l2d_err_s cn58xxp1;
155};
156
157union cvmx_l2d_fadr {
158 uint64_t u64;
159 struct cvmx_l2d_fadr_s {
160 uint64_t reserved_19_63:45;
161 uint64_t fadru:1;
162 uint64_t fowmsk:4;
163 uint64_t fset:3;
164 uint64_t fadr:11;
165 } s;
166 struct cvmx_l2d_fadr_cn30xx {
167 uint64_t reserved_18_63:46;
168 uint64_t fowmsk:4;
169 uint64_t reserved_13_13:1;
170 uint64_t fset:2;
171 uint64_t reserved_9_10:2;
172 uint64_t fadr:9;
173 } cn30xx;
174 struct cvmx_l2d_fadr_cn31xx {
175 uint64_t reserved_18_63:46;
176 uint64_t fowmsk:4;
177 uint64_t reserved_13_13:1;
178 uint64_t fset:2;
179 uint64_t reserved_10_10:1;
180 uint64_t fadr:10;
181 } cn31xx;
182 struct cvmx_l2d_fadr_cn38xx {
183 uint64_t reserved_18_63:46;
184 uint64_t fowmsk:4;
185 uint64_t fset:3;
186 uint64_t fadr:11;
187 } cn38xx;
188 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
189 struct cvmx_l2d_fadr_cn50xx {
190 uint64_t reserved_18_63:46;
191 uint64_t fowmsk:4;
192 uint64_t fset:3;
193 uint64_t reserved_8_10:3;
194 uint64_t fadr:8;
195 } cn50xx;
196 struct cvmx_l2d_fadr_cn52xx {
197 uint64_t reserved_18_63:46;
198 uint64_t fowmsk:4;
199 uint64_t fset:3;
200 uint64_t reserved_10_10:1;
201 uint64_t fadr:10;
202 } cn52xx;
203 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
204 struct cvmx_l2d_fadr_s cn56xx;
205 struct cvmx_l2d_fadr_s cn56xxp1;
206 struct cvmx_l2d_fadr_s cn58xx;
207 struct cvmx_l2d_fadr_s cn58xxp1;
208};
209
210union cvmx_l2d_fsyn0 {
211 uint64_t u64;
212 struct cvmx_l2d_fsyn0_s {
213 uint64_t reserved_20_63:44;
214 uint64_t fsyn_ow1:10;
215 uint64_t fsyn_ow0:10;
216 } s;
217 struct cvmx_l2d_fsyn0_s cn30xx;
218 struct cvmx_l2d_fsyn0_s cn31xx;
219 struct cvmx_l2d_fsyn0_s cn38xx;
220 struct cvmx_l2d_fsyn0_s cn38xxp2;
221 struct cvmx_l2d_fsyn0_s cn50xx;
222 struct cvmx_l2d_fsyn0_s cn52xx;
223 struct cvmx_l2d_fsyn0_s cn52xxp1;
224 struct cvmx_l2d_fsyn0_s cn56xx;
225 struct cvmx_l2d_fsyn0_s cn56xxp1;
226 struct cvmx_l2d_fsyn0_s cn58xx;
227 struct cvmx_l2d_fsyn0_s cn58xxp1;
228};
229
230union cvmx_l2d_fsyn1 {
231 uint64_t u64;
232 struct cvmx_l2d_fsyn1_s {
233 uint64_t reserved_20_63:44;
234 uint64_t fsyn_ow3:10;
235 uint64_t fsyn_ow2:10;
236 } s;
237 struct cvmx_l2d_fsyn1_s cn30xx;
238 struct cvmx_l2d_fsyn1_s cn31xx;
239 struct cvmx_l2d_fsyn1_s cn38xx;
240 struct cvmx_l2d_fsyn1_s cn38xxp2;
241 struct cvmx_l2d_fsyn1_s cn50xx;
242 struct cvmx_l2d_fsyn1_s cn52xx;
243 struct cvmx_l2d_fsyn1_s cn52xxp1;
244 struct cvmx_l2d_fsyn1_s cn56xx;
245 struct cvmx_l2d_fsyn1_s cn56xxp1;
246 struct cvmx_l2d_fsyn1_s cn58xx;
247 struct cvmx_l2d_fsyn1_s cn58xxp1;
248};
249
250union cvmx_l2d_fus0 {
251 uint64_t u64;
252 struct cvmx_l2d_fus0_s {
253 uint64_t reserved_34_63:30;
254 uint64_t q0fus:34;
255 } s;
256 struct cvmx_l2d_fus0_s cn30xx;
257 struct cvmx_l2d_fus0_s cn31xx;
258 struct cvmx_l2d_fus0_s cn38xx;
259 struct cvmx_l2d_fus0_s cn38xxp2;
260 struct cvmx_l2d_fus0_s cn50xx;
261 struct cvmx_l2d_fus0_s cn52xx;
262 struct cvmx_l2d_fus0_s cn52xxp1;
263 struct cvmx_l2d_fus0_s cn56xx;
264 struct cvmx_l2d_fus0_s cn56xxp1;
265 struct cvmx_l2d_fus0_s cn58xx;
266 struct cvmx_l2d_fus0_s cn58xxp1;
267};
268
269union cvmx_l2d_fus1 {
270 uint64_t u64;
271 struct cvmx_l2d_fus1_s {
272 uint64_t reserved_34_63:30;
273 uint64_t q1fus:34;
274 } s;
275 struct cvmx_l2d_fus1_s cn30xx;
276 struct cvmx_l2d_fus1_s cn31xx;
277 struct cvmx_l2d_fus1_s cn38xx;
278 struct cvmx_l2d_fus1_s cn38xxp2;
279 struct cvmx_l2d_fus1_s cn50xx;
280 struct cvmx_l2d_fus1_s cn52xx;
281 struct cvmx_l2d_fus1_s cn52xxp1;
282 struct cvmx_l2d_fus1_s cn56xx;
283 struct cvmx_l2d_fus1_s cn56xxp1;
284 struct cvmx_l2d_fus1_s cn58xx;
285 struct cvmx_l2d_fus1_s cn58xxp1;
286};
287
288union cvmx_l2d_fus2 {
289 uint64_t u64;
290 struct cvmx_l2d_fus2_s {
291 uint64_t reserved_34_63:30;
292 uint64_t q2fus:34;
293 } s;
294 struct cvmx_l2d_fus2_s cn30xx;
295 struct cvmx_l2d_fus2_s cn31xx;
296 struct cvmx_l2d_fus2_s cn38xx;
297 struct cvmx_l2d_fus2_s cn38xxp2;
298 struct cvmx_l2d_fus2_s cn50xx;
299 struct cvmx_l2d_fus2_s cn52xx;
300 struct cvmx_l2d_fus2_s cn52xxp1;
301 struct cvmx_l2d_fus2_s cn56xx;
302 struct cvmx_l2d_fus2_s cn56xxp1;
303 struct cvmx_l2d_fus2_s cn58xx;
304 struct cvmx_l2d_fus2_s cn58xxp1;
305};
306
307union cvmx_l2d_fus3 {
308 uint64_t u64;
309 struct cvmx_l2d_fus3_s {
310 uint64_t reserved_40_63:24;
311 uint64_t ema_ctl:3;
312 uint64_t reserved_34_36:3;
313 uint64_t q3fus:34;
314 } s;
315 struct cvmx_l2d_fus3_cn30xx {
316 uint64_t reserved_35_63:29;
317 uint64_t crip_64k:1;
318 uint64_t q3fus:34;
319 } cn30xx;
320 struct cvmx_l2d_fus3_cn31xx {
321 uint64_t reserved_35_63:29;
322 uint64_t crip_128k:1;
323 uint64_t q3fus:34;
324 } cn31xx;
325 struct cvmx_l2d_fus3_cn38xx {
326 uint64_t reserved_36_63:28;
327 uint64_t crip_256k:1;
328 uint64_t crip_512k:1;
329 uint64_t q3fus:34;
330 } cn38xx;
331 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
332 struct cvmx_l2d_fus3_cn50xx {
333 uint64_t reserved_40_63:24;
334 uint64_t ema_ctl:3;
335 uint64_t reserved_36_36:1;
336 uint64_t crip_32k:1;
337 uint64_t crip_64k:1;
338 uint64_t q3fus:34;
339 } cn50xx;
340 struct cvmx_l2d_fus3_cn52xx {
341 uint64_t reserved_40_63:24;
342 uint64_t ema_ctl:3;
343 uint64_t reserved_36_36:1;
344 uint64_t crip_128k:1;
345 uint64_t crip_256k:1;
346 uint64_t q3fus:34;
347 } cn52xx;
348 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
349 struct cvmx_l2d_fus3_cn56xx {
350 uint64_t reserved_40_63:24;
351 uint64_t ema_ctl:3;
352 uint64_t reserved_36_36:1;
353 uint64_t crip_512k:1;
354 uint64_t crip_1024k:1;
355 uint64_t q3fus:34;
356 } cn56xx;
357 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
358 struct cvmx_l2d_fus3_cn58xx {
359 uint64_t reserved_39_63:25;
360 uint64_t ema_ctl:2;
361 uint64_t reserved_36_36:1;
362 uint64_t crip_512k:1;
363 uint64_t crip_1024k:1;
364 uint64_t q3fus:34;
365 } cn58xx;
366 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
367};
368
369#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
new file mode 100644
index 000000000000..2639a3f5ffc2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -0,0 +1,141 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__
30
31#define CVMX_L2T_ERR \
32 CVMX_ADD_IO_SEG(0x0001180080000008ull)
33
34union cvmx_l2t_err {
35 uint64_t u64;
36 struct cvmx_l2t_err_s {
37 uint64_t reserved_29_63:35;
38 uint64_t fadru:1;
39 uint64_t lck_intena2:1;
40 uint64_t lckerr2:1;
41 uint64_t lck_intena:1;
42 uint64_t lckerr:1;
43 uint64_t fset:3;
44 uint64_t fadr:10;
45 uint64_t fsyn:6;
46 uint64_t ded_err:1;
47 uint64_t sec_err:1;
48 uint64_t ded_intena:1;
49 uint64_t sec_intena:1;
50 uint64_t ecc_ena:1;
51 } s;
52 struct cvmx_l2t_err_cn30xx {
53 uint64_t reserved_28_63:36;
54 uint64_t lck_intena2:1;
55 uint64_t lckerr2:1;
56 uint64_t lck_intena:1;
57 uint64_t lckerr:1;
58 uint64_t reserved_23_23:1;
59 uint64_t fset:2;
60 uint64_t reserved_19_20:2;
61 uint64_t fadr:8;
62 uint64_t fsyn:6;
63 uint64_t ded_err:1;
64 uint64_t sec_err:1;
65 uint64_t ded_intena:1;
66 uint64_t sec_intena:1;
67 uint64_t ecc_ena:1;
68 } cn30xx;
69 struct cvmx_l2t_err_cn31xx {
70 uint64_t reserved_28_63:36;
71 uint64_t lck_intena2:1;
72 uint64_t lckerr2:1;
73 uint64_t lck_intena:1;
74 uint64_t lckerr:1;
75 uint64_t reserved_23_23:1;
76 uint64_t fset:2;
77 uint64_t reserved_20_20:1;
78 uint64_t fadr:9;
79 uint64_t fsyn:6;
80 uint64_t ded_err:1;
81 uint64_t sec_err:1;
82 uint64_t ded_intena:1;
83 uint64_t sec_intena:1;
84 uint64_t ecc_ena:1;
85 } cn31xx;
86 struct cvmx_l2t_err_cn38xx {
87 uint64_t reserved_28_63:36;
88 uint64_t lck_intena2:1;
89 uint64_t lckerr2:1;
90 uint64_t lck_intena:1;
91 uint64_t lckerr:1;
92 uint64_t fset:3;
93 uint64_t fadr:10;
94 uint64_t fsyn:6;
95 uint64_t ded_err:1;
96 uint64_t sec_err:1;
97 uint64_t ded_intena:1;
98 uint64_t sec_intena:1;
99 uint64_t ecc_ena:1;
100 } cn38xx;
101 struct cvmx_l2t_err_cn38xx cn38xxp2;
102 struct cvmx_l2t_err_cn50xx {
103 uint64_t reserved_28_63:36;
104 uint64_t lck_intena2:1;
105 uint64_t lckerr2:1;
106 uint64_t lck_intena:1;
107 uint64_t lckerr:1;
108 uint64_t fset:3;
109 uint64_t reserved_18_20:3;
110 uint64_t fadr:7;
111 uint64_t fsyn:6;
112 uint64_t ded_err:1;
113 uint64_t sec_err:1;
114 uint64_t ded_intena:1;
115 uint64_t sec_intena:1;
116 uint64_t ecc_ena:1;
117 } cn50xx;
118 struct cvmx_l2t_err_cn52xx {
119 uint64_t reserved_28_63:36;
120 uint64_t lck_intena2:1;
121 uint64_t lckerr2:1;
122 uint64_t lck_intena:1;
123 uint64_t lckerr:1;
124 uint64_t fset:3;
125 uint64_t reserved_20_20:1;
126 uint64_t fadr:9;
127 uint64_t fsyn:6;
128 uint64_t ded_err:1;
129 uint64_t sec_err:1;
130 uint64_t ded_intena:1;
131 uint64_t sec_intena:1;
132 uint64_t ecc_ena:1;
133 } cn52xx;
134 struct cvmx_l2t_err_cn52xx cn52xxp1;
135 struct cvmx_l2t_err_s cn56xx;
136 struct cvmx_l2t_err_s cn56xxp1;
137 struct cvmx_l2t_err_s cn58xx;
138 struct cvmx_l2t_err_s cn58xxp1;
139};
140
141#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
new file mode 100644
index 000000000000..16f174a4dadf
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -0,0 +1,240 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_LED_DEFS_H__
29#define __CVMX_LED_DEFS_H__
30
31#define CVMX_LED_BLINK \
32 CVMX_ADD_IO_SEG(0x0001180000001A48ull)
33#define CVMX_LED_CLK_PHASE \
34 CVMX_ADD_IO_SEG(0x0001180000001A08ull)
35#define CVMX_LED_CYLON \
36 CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
37#define CVMX_LED_DBG \
38 CVMX_ADD_IO_SEG(0x0001180000001A18ull)
39#define CVMX_LED_EN \
40 CVMX_ADD_IO_SEG(0x0001180000001A00ull)
41#define CVMX_LED_POLARITY \
42 CVMX_ADD_IO_SEG(0x0001180000001A50ull)
43#define CVMX_LED_PRT \
44 CVMX_ADD_IO_SEG(0x0001180000001A10ull)
45#define CVMX_LED_PRT_FMT \
46 CVMX_ADD_IO_SEG(0x0001180000001A30ull)
47#define CVMX_LED_PRT_STATUSX(offset) \
48 CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
49#define CVMX_LED_UDD_CNTX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
51#define CVMX_LED_UDD_DATX(offset) \
52 CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
53#define CVMX_LED_UDD_DAT_CLRX(offset) \
54 CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
55#define CVMX_LED_UDD_DAT_SETX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
57
58union cvmx_led_blink {
59 uint64_t u64;
60 struct cvmx_led_blink_s {
61 uint64_t reserved_8_63:56;
62 uint64_t rate:8;
63 } s;
64 struct cvmx_led_blink_s cn38xx;
65 struct cvmx_led_blink_s cn38xxp2;
66 struct cvmx_led_blink_s cn56xx;
67 struct cvmx_led_blink_s cn56xxp1;
68 struct cvmx_led_blink_s cn58xx;
69 struct cvmx_led_blink_s cn58xxp1;
70};
71
72union cvmx_led_clk_phase {
73 uint64_t u64;
74 struct cvmx_led_clk_phase_s {
75 uint64_t reserved_7_63:57;
76 uint64_t phase:7;
77 } s;
78 struct cvmx_led_clk_phase_s cn38xx;
79 struct cvmx_led_clk_phase_s cn38xxp2;
80 struct cvmx_led_clk_phase_s cn56xx;
81 struct cvmx_led_clk_phase_s cn56xxp1;
82 struct cvmx_led_clk_phase_s cn58xx;
83 struct cvmx_led_clk_phase_s cn58xxp1;
84};
85
86union cvmx_led_cylon {
87 uint64_t u64;
88 struct cvmx_led_cylon_s {
89 uint64_t reserved_16_63:48;
90 uint64_t rate:16;
91 } s;
92 struct cvmx_led_cylon_s cn38xx;
93 struct cvmx_led_cylon_s cn38xxp2;
94 struct cvmx_led_cylon_s cn56xx;
95 struct cvmx_led_cylon_s cn56xxp1;
96 struct cvmx_led_cylon_s cn58xx;
97 struct cvmx_led_cylon_s cn58xxp1;
98};
99
100union cvmx_led_dbg {
101 uint64_t u64;
102 struct cvmx_led_dbg_s {
103 uint64_t reserved_1_63:63;
104 uint64_t dbg_en:1;
105 } s;
106 struct cvmx_led_dbg_s cn38xx;
107 struct cvmx_led_dbg_s cn38xxp2;
108 struct cvmx_led_dbg_s cn56xx;
109 struct cvmx_led_dbg_s cn56xxp1;
110 struct cvmx_led_dbg_s cn58xx;
111 struct cvmx_led_dbg_s cn58xxp1;
112};
113
114union cvmx_led_en {
115 uint64_t u64;
116 struct cvmx_led_en_s {
117 uint64_t reserved_1_63:63;
118 uint64_t en:1;
119 } s;
120 struct cvmx_led_en_s cn38xx;
121 struct cvmx_led_en_s cn38xxp2;
122 struct cvmx_led_en_s cn56xx;
123 struct cvmx_led_en_s cn56xxp1;
124 struct cvmx_led_en_s cn58xx;
125 struct cvmx_led_en_s cn58xxp1;
126};
127
128union cvmx_led_polarity {
129 uint64_t u64;
130 struct cvmx_led_polarity_s {
131 uint64_t reserved_1_63:63;
132 uint64_t polarity:1;
133 } s;
134 struct cvmx_led_polarity_s cn38xx;
135 struct cvmx_led_polarity_s cn38xxp2;
136 struct cvmx_led_polarity_s cn56xx;
137 struct cvmx_led_polarity_s cn56xxp1;
138 struct cvmx_led_polarity_s cn58xx;
139 struct cvmx_led_polarity_s cn58xxp1;
140};
141
142union cvmx_led_prt {
143 uint64_t u64;
144 struct cvmx_led_prt_s {
145 uint64_t reserved_8_63:56;
146 uint64_t prt_en:8;
147 } s;
148 struct cvmx_led_prt_s cn38xx;
149 struct cvmx_led_prt_s cn38xxp2;
150 struct cvmx_led_prt_s cn56xx;
151 struct cvmx_led_prt_s cn56xxp1;
152 struct cvmx_led_prt_s cn58xx;
153 struct cvmx_led_prt_s cn58xxp1;
154};
155
156union cvmx_led_prt_fmt {
157 uint64_t u64;
158 struct cvmx_led_prt_fmt_s {
159 uint64_t reserved_4_63:60;
160 uint64_t format:4;
161 } s;
162 struct cvmx_led_prt_fmt_s cn38xx;
163 struct cvmx_led_prt_fmt_s cn38xxp2;
164 struct cvmx_led_prt_fmt_s cn56xx;
165 struct cvmx_led_prt_fmt_s cn56xxp1;
166 struct cvmx_led_prt_fmt_s cn58xx;
167 struct cvmx_led_prt_fmt_s cn58xxp1;
168};
169
170union cvmx_led_prt_statusx {
171 uint64_t u64;
172 struct cvmx_led_prt_statusx_s {
173 uint64_t reserved_6_63:58;
174 uint64_t status:6;
175 } s;
176 struct cvmx_led_prt_statusx_s cn38xx;
177 struct cvmx_led_prt_statusx_s cn38xxp2;
178 struct cvmx_led_prt_statusx_s cn56xx;
179 struct cvmx_led_prt_statusx_s cn56xxp1;
180 struct cvmx_led_prt_statusx_s cn58xx;
181 struct cvmx_led_prt_statusx_s cn58xxp1;
182};
183
184union cvmx_led_udd_cntx {
185 uint64_t u64;
186 struct cvmx_led_udd_cntx_s {
187 uint64_t reserved_6_63:58;
188 uint64_t cnt:6;
189 } s;
190 struct cvmx_led_udd_cntx_s cn38xx;
191 struct cvmx_led_udd_cntx_s cn38xxp2;
192 struct cvmx_led_udd_cntx_s cn56xx;
193 struct cvmx_led_udd_cntx_s cn56xxp1;
194 struct cvmx_led_udd_cntx_s cn58xx;
195 struct cvmx_led_udd_cntx_s cn58xxp1;
196};
197
198union cvmx_led_udd_datx {
199 uint64_t u64;
200 struct cvmx_led_udd_datx_s {
201 uint64_t reserved_32_63:32;
202 uint64_t dat:32;
203 } s;
204 struct cvmx_led_udd_datx_s cn38xx;
205 struct cvmx_led_udd_datx_s cn38xxp2;
206 struct cvmx_led_udd_datx_s cn56xx;
207 struct cvmx_led_udd_datx_s cn56xxp1;
208 struct cvmx_led_udd_datx_s cn58xx;
209 struct cvmx_led_udd_datx_s cn58xxp1;
210};
211
212union cvmx_led_udd_dat_clrx {
213 uint64_t u64;
214 struct cvmx_led_udd_dat_clrx_s {
215 uint64_t reserved_32_63:32;
216 uint64_t clr:32;
217 } s;
218 struct cvmx_led_udd_dat_clrx_s cn38xx;
219 struct cvmx_led_udd_dat_clrx_s cn38xxp2;
220 struct cvmx_led_udd_dat_clrx_s cn56xx;
221 struct cvmx_led_udd_dat_clrx_s cn56xxp1;
222 struct cvmx_led_udd_dat_clrx_s cn58xx;
223 struct cvmx_led_udd_dat_clrx_s cn58xxp1;
224};
225
226union cvmx_led_udd_dat_setx {
227 uint64_t u64;
228 struct cvmx_led_udd_dat_setx_s {
229 uint64_t reserved_32_63:32;
230 uint64_t set:32;
231 } s;
232 struct cvmx_led_udd_dat_setx_s cn38xx;
233 struct cvmx_led_udd_dat_setx_s cn38xxp2;
234 struct cvmx_led_udd_dat_setx_s cn56xx;
235 struct cvmx_led_udd_dat_setx_s cn56xxp1;
236 struct cvmx_led_udd_dat_setx_s cn58xx;
237 struct cvmx_led_udd_dat_setx_s cn58xxp1;
238};
239
240#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
new file mode 100644
index 000000000000..6555f0530988
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -0,0 +1,2004 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIO_DEFS_H__
29#define __CVMX_MIO_DEFS_H__
30
31#define CVMX_MIO_BOOT_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00011800000000F8ull)
33#define CVMX_MIO_BOOT_COMP \
34 CVMX_ADD_IO_SEG(0x00011800000000B8ull)
35#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
37#define CVMX_MIO_BOOT_DMA_INTX(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
39#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
41#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
42 CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
43#define CVMX_MIO_BOOT_ERR \
44 CVMX_ADD_IO_SEG(0x00011800000000A0ull)
45#define CVMX_MIO_BOOT_INT \
46 CVMX_ADD_IO_SEG(0x00011800000000A8ull)
47#define CVMX_MIO_BOOT_LOC_ADR \
48 CVMX_ADD_IO_SEG(0x0001180000000090ull)
49#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
51#define CVMX_MIO_BOOT_LOC_DAT \
52 CVMX_ADD_IO_SEG(0x0001180000000098ull)
53#define CVMX_MIO_BOOT_PIN_DEFS \
54 CVMX_ADD_IO_SEG(0x00011800000000C0ull)
55#define CVMX_MIO_BOOT_REG_CFGX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
57#define CVMX_MIO_BOOT_REG_TIMX(offset) \
58 CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
59#define CVMX_MIO_BOOT_THR \
60 CVMX_ADD_IO_SEG(0x00011800000000B0ull)
61#define CVMX_MIO_FUS_BNK_DATX(offset) \
62 CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
63#define CVMX_MIO_FUS_DAT0 \
64 CVMX_ADD_IO_SEG(0x0001180000001400ull)
65#define CVMX_MIO_FUS_DAT1 \
66 CVMX_ADD_IO_SEG(0x0001180000001408ull)
67#define CVMX_MIO_FUS_DAT2 \
68 CVMX_ADD_IO_SEG(0x0001180000001410ull)
69#define CVMX_MIO_FUS_DAT3 \
70 CVMX_ADD_IO_SEG(0x0001180000001418ull)
71#define CVMX_MIO_FUS_EMA \
72 CVMX_ADD_IO_SEG(0x0001180000001550ull)
73#define CVMX_MIO_FUS_PDF \
74 CVMX_ADD_IO_SEG(0x0001180000001420ull)
75#define CVMX_MIO_FUS_PLL \
76 CVMX_ADD_IO_SEG(0x0001180000001580ull)
77#define CVMX_MIO_FUS_PROG \
78 CVMX_ADD_IO_SEG(0x0001180000001510ull)
79#define CVMX_MIO_FUS_PROG_TIMES \
80 CVMX_ADD_IO_SEG(0x0001180000001518ull)
81#define CVMX_MIO_FUS_RCMD \
82 CVMX_ADD_IO_SEG(0x0001180000001500ull)
83#define CVMX_MIO_FUS_SPR_REPAIR_RES \
84 CVMX_ADD_IO_SEG(0x0001180000001548ull)
85#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
86 CVMX_ADD_IO_SEG(0x0001180000001540ull)
87#define CVMX_MIO_FUS_UNLOCK \
88 CVMX_ADD_IO_SEG(0x0001180000001578ull)
89#define CVMX_MIO_FUS_WADR \
90 CVMX_ADD_IO_SEG(0x0001180000001508ull)
91#define CVMX_MIO_NDF_DMA_CFG \
92 CVMX_ADD_IO_SEG(0x0001180000000168ull)
93#define CVMX_MIO_NDF_DMA_INT \
94 CVMX_ADD_IO_SEG(0x0001180000000170ull)
95#define CVMX_MIO_NDF_DMA_INT_EN \
96 CVMX_ADD_IO_SEG(0x0001180000000178ull)
97#define CVMX_MIO_PLL_CTL \
98 CVMX_ADD_IO_SEG(0x0001180000001448ull)
99#define CVMX_MIO_PLL_SETTING \
100 CVMX_ADD_IO_SEG(0x0001180000001440ull)
101#define CVMX_MIO_TWSX_INT(offset) \
102 CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
103#define CVMX_MIO_TWSX_SW_TWSI(offset) \
104 CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
105#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
106 CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
107#define CVMX_MIO_TWSX_TWSI_SW(offset) \
108 CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
109#define CVMX_MIO_UART2_DLH \
110 CVMX_ADD_IO_SEG(0x0001180000000488ull)
111#define CVMX_MIO_UART2_DLL \
112 CVMX_ADD_IO_SEG(0x0001180000000480ull)
113#define CVMX_MIO_UART2_FAR \
114 CVMX_ADD_IO_SEG(0x0001180000000520ull)
115#define CVMX_MIO_UART2_FCR \
116 CVMX_ADD_IO_SEG(0x0001180000000450ull)
117#define CVMX_MIO_UART2_HTX \
118 CVMX_ADD_IO_SEG(0x0001180000000708ull)
119#define CVMX_MIO_UART2_IER \
120 CVMX_ADD_IO_SEG(0x0001180000000408ull)
121#define CVMX_MIO_UART2_IIR \
122 CVMX_ADD_IO_SEG(0x0001180000000410ull)
123#define CVMX_MIO_UART2_LCR \
124 CVMX_ADD_IO_SEG(0x0001180000000418ull)
125#define CVMX_MIO_UART2_LSR \
126 CVMX_ADD_IO_SEG(0x0001180000000428ull)
127#define CVMX_MIO_UART2_MCR \
128 CVMX_ADD_IO_SEG(0x0001180000000420ull)
129#define CVMX_MIO_UART2_MSR \
130 CVMX_ADD_IO_SEG(0x0001180000000430ull)
131#define CVMX_MIO_UART2_RBR \
132 CVMX_ADD_IO_SEG(0x0001180000000400ull)
133#define CVMX_MIO_UART2_RFL \
134 CVMX_ADD_IO_SEG(0x0001180000000608ull)
135#define CVMX_MIO_UART2_RFW \
136 CVMX_ADD_IO_SEG(0x0001180000000530ull)
137#define CVMX_MIO_UART2_SBCR \
138 CVMX_ADD_IO_SEG(0x0001180000000620ull)
139#define CVMX_MIO_UART2_SCR \
140 CVMX_ADD_IO_SEG(0x0001180000000438ull)
141#define CVMX_MIO_UART2_SFE \
142 CVMX_ADD_IO_SEG(0x0001180000000630ull)
143#define CVMX_MIO_UART2_SRR \
144 CVMX_ADD_IO_SEG(0x0001180000000610ull)
145#define CVMX_MIO_UART2_SRT \
146 CVMX_ADD_IO_SEG(0x0001180000000638ull)
147#define CVMX_MIO_UART2_SRTS \
148 CVMX_ADD_IO_SEG(0x0001180000000618ull)
149#define CVMX_MIO_UART2_STT \
150 CVMX_ADD_IO_SEG(0x0001180000000700ull)
151#define CVMX_MIO_UART2_TFL \
152 CVMX_ADD_IO_SEG(0x0001180000000600ull)
153#define CVMX_MIO_UART2_TFR \
154 CVMX_ADD_IO_SEG(0x0001180000000528ull)
155#define CVMX_MIO_UART2_THR \
156 CVMX_ADD_IO_SEG(0x0001180000000440ull)
157#define CVMX_MIO_UART2_USR \
158 CVMX_ADD_IO_SEG(0x0001180000000538ull)
159#define CVMX_MIO_UARTX_DLH(offset) \
160 CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
161#define CVMX_MIO_UARTX_DLL(offset) \
162 CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
163#define CVMX_MIO_UARTX_FAR(offset) \
164 CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
165#define CVMX_MIO_UARTX_FCR(offset) \
166 CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
167#define CVMX_MIO_UARTX_HTX(offset) \
168 CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
169#define CVMX_MIO_UARTX_IER(offset) \
170 CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
171#define CVMX_MIO_UARTX_IIR(offset) \
172 CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
173#define CVMX_MIO_UARTX_LCR(offset) \
174 CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
175#define CVMX_MIO_UARTX_LSR(offset) \
176 CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
177#define CVMX_MIO_UARTX_MCR(offset) \
178 CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
179#define CVMX_MIO_UARTX_MSR(offset) \
180 CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
181#define CVMX_MIO_UARTX_RBR(offset) \
182 CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
183#define CVMX_MIO_UARTX_RFL(offset) \
184 CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
185#define CVMX_MIO_UARTX_RFW(offset) \
186 CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
187#define CVMX_MIO_UARTX_SBCR(offset) \
188 CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
189#define CVMX_MIO_UARTX_SCR(offset) \
190 CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
191#define CVMX_MIO_UARTX_SFE(offset) \
192 CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
193#define CVMX_MIO_UARTX_SRR(offset) \
194 CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
195#define CVMX_MIO_UARTX_SRT(offset) \
196 CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
197#define CVMX_MIO_UARTX_SRTS(offset) \
198 CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
199#define CVMX_MIO_UARTX_STT(offset) \
200 CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
201#define CVMX_MIO_UARTX_TFL(offset) \
202 CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
203#define CVMX_MIO_UARTX_TFR(offset) \
204 CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
205#define CVMX_MIO_UARTX_THR(offset) \
206 CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
207#define CVMX_MIO_UARTX_USR(offset) \
208 CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
209
210union cvmx_mio_boot_bist_stat {
211 uint64_t u64;
212 struct cvmx_mio_boot_bist_stat_s {
213 uint64_t reserved_2_63:62;
214 uint64_t loc:1;
215 uint64_t ncbi:1;
216 } s;
217 struct cvmx_mio_boot_bist_stat_cn30xx {
218 uint64_t reserved_4_63:60;
219 uint64_t ncbo_1:1;
220 uint64_t ncbo_0:1;
221 uint64_t loc:1;
222 uint64_t ncbi:1;
223 } cn30xx;
224 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
225 struct cvmx_mio_boot_bist_stat_cn38xx {
226 uint64_t reserved_3_63:61;
227 uint64_t ncbo_0:1;
228 uint64_t loc:1;
229 uint64_t ncbi:1;
230 } cn38xx;
231 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
232 struct cvmx_mio_boot_bist_stat_cn50xx {
233 uint64_t reserved_6_63:58;
234 uint64_t pcm_1:1;
235 uint64_t pcm_0:1;
236 uint64_t ncbo_1:1;
237 uint64_t ncbo_0:1;
238 uint64_t loc:1;
239 uint64_t ncbi:1;
240 } cn50xx;
241 struct cvmx_mio_boot_bist_stat_cn52xx {
242 uint64_t reserved_6_63:58;
243 uint64_t ndf:2;
244 uint64_t ncbo_0:1;
245 uint64_t dma:1;
246 uint64_t loc:1;
247 uint64_t ncbi:1;
248 } cn52xx;
249 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
250 uint64_t reserved_4_63:60;
251 uint64_t ncbo_0:1;
252 uint64_t dma:1;
253 uint64_t loc:1;
254 uint64_t ncbi:1;
255 } cn52xxp1;
256 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
258 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
260};
261
262union cvmx_mio_boot_comp {
263 uint64_t u64;
264 struct cvmx_mio_boot_comp_s {
265 uint64_t reserved_10_63:54;
266 uint64_t pctl:5;
267 uint64_t nctl:5;
268 } s;
269 struct cvmx_mio_boot_comp_s cn50xx;
270 struct cvmx_mio_boot_comp_s cn52xx;
271 struct cvmx_mio_boot_comp_s cn52xxp1;
272 struct cvmx_mio_boot_comp_s cn56xx;
273 struct cvmx_mio_boot_comp_s cn56xxp1;
274};
275
276union cvmx_mio_boot_dma_cfgx {
277 uint64_t u64;
278 struct cvmx_mio_boot_dma_cfgx_s {
279 uint64_t en:1;
280 uint64_t rw:1;
281 uint64_t clr:1;
282 uint64_t reserved_60_60:1;
283 uint64_t swap32:1;
284 uint64_t swap16:1;
285 uint64_t swap8:1;
286 uint64_t endian:1;
287 uint64_t size:20;
288 uint64_t adr:36;
289 } s;
290 struct cvmx_mio_boot_dma_cfgx_s cn52xx;
291 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
292 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
293 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
294};
295
296union cvmx_mio_boot_dma_intx {
297 uint64_t u64;
298 struct cvmx_mio_boot_dma_intx_s {
299 uint64_t reserved_2_63:62;
300 uint64_t dmarq:1;
301 uint64_t done:1;
302 } s;
303 struct cvmx_mio_boot_dma_intx_s cn52xx;
304 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
305 struct cvmx_mio_boot_dma_intx_s cn56xx;
306 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
307};
308
309union cvmx_mio_boot_dma_int_enx {
310 uint64_t u64;
311 struct cvmx_mio_boot_dma_int_enx_s {
312 uint64_t reserved_2_63:62;
313 uint64_t dmarq:1;
314 uint64_t done:1;
315 } s;
316 struct cvmx_mio_boot_dma_int_enx_s cn52xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
318 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
319 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
320};
321
322union cvmx_mio_boot_dma_timx {
323 uint64_t u64;
324 struct cvmx_mio_boot_dma_timx_s {
325 uint64_t dmack_pi:1;
326 uint64_t dmarq_pi:1;
327 uint64_t tim_mult:2;
328 uint64_t rd_dly:3;
329 uint64_t ddr:1;
330 uint64_t width:1;
331 uint64_t reserved_48_54:7;
332 uint64_t pause:6;
333 uint64_t dmack_h:6;
334 uint64_t we_n:6;
335 uint64_t we_a:6;
336 uint64_t oe_n:6;
337 uint64_t oe_a:6;
338 uint64_t dmack_s:6;
339 uint64_t dmarq:6;
340 } s;
341 struct cvmx_mio_boot_dma_timx_s cn52xx;
342 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
343 struct cvmx_mio_boot_dma_timx_s cn56xx;
344 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
345};
346
347union cvmx_mio_boot_err {
348 uint64_t u64;
349 struct cvmx_mio_boot_err_s {
350 uint64_t reserved_2_63:62;
351 uint64_t wait_err:1;
352 uint64_t adr_err:1;
353 } s;
354 struct cvmx_mio_boot_err_s cn30xx;
355 struct cvmx_mio_boot_err_s cn31xx;
356 struct cvmx_mio_boot_err_s cn38xx;
357 struct cvmx_mio_boot_err_s cn38xxp2;
358 struct cvmx_mio_boot_err_s cn50xx;
359 struct cvmx_mio_boot_err_s cn52xx;
360 struct cvmx_mio_boot_err_s cn52xxp1;
361 struct cvmx_mio_boot_err_s cn56xx;
362 struct cvmx_mio_boot_err_s cn56xxp1;
363 struct cvmx_mio_boot_err_s cn58xx;
364 struct cvmx_mio_boot_err_s cn58xxp1;
365};
366
367union cvmx_mio_boot_int {
368 uint64_t u64;
369 struct cvmx_mio_boot_int_s {
370 uint64_t reserved_2_63:62;
371 uint64_t wait_int:1;
372 uint64_t adr_int:1;
373 } s;
374 struct cvmx_mio_boot_int_s cn30xx;
375 struct cvmx_mio_boot_int_s cn31xx;
376 struct cvmx_mio_boot_int_s cn38xx;
377 struct cvmx_mio_boot_int_s cn38xxp2;
378 struct cvmx_mio_boot_int_s cn50xx;
379 struct cvmx_mio_boot_int_s cn52xx;
380 struct cvmx_mio_boot_int_s cn52xxp1;
381 struct cvmx_mio_boot_int_s cn56xx;
382 struct cvmx_mio_boot_int_s cn56xxp1;
383 struct cvmx_mio_boot_int_s cn58xx;
384 struct cvmx_mio_boot_int_s cn58xxp1;
385};
386
387union cvmx_mio_boot_loc_adr {
388 uint64_t u64;
389 struct cvmx_mio_boot_loc_adr_s {
390 uint64_t reserved_8_63:56;
391 uint64_t adr:5;
392 uint64_t reserved_0_2:3;
393 } s;
394 struct cvmx_mio_boot_loc_adr_s cn30xx;
395 struct cvmx_mio_boot_loc_adr_s cn31xx;
396 struct cvmx_mio_boot_loc_adr_s cn38xx;
397 struct cvmx_mio_boot_loc_adr_s cn38xxp2;
398 struct cvmx_mio_boot_loc_adr_s cn50xx;
399 struct cvmx_mio_boot_loc_adr_s cn52xx;
400 struct cvmx_mio_boot_loc_adr_s cn52xxp1;
401 struct cvmx_mio_boot_loc_adr_s cn56xx;
402 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
403 struct cvmx_mio_boot_loc_adr_s cn58xx;
404 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
405};
406
407union cvmx_mio_boot_loc_cfgx {
408 uint64_t u64;
409 struct cvmx_mio_boot_loc_cfgx_s {
410 uint64_t reserved_32_63:32;
411 uint64_t en:1;
412 uint64_t reserved_28_30:3;
413 uint64_t base:25;
414 uint64_t reserved_0_2:3;
415 } s;
416 struct cvmx_mio_boot_loc_cfgx_s cn30xx;
417 struct cvmx_mio_boot_loc_cfgx_s cn31xx;
418 struct cvmx_mio_boot_loc_cfgx_s cn38xx;
419 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
420 struct cvmx_mio_boot_loc_cfgx_s cn50xx;
421 struct cvmx_mio_boot_loc_cfgx_s cn52xx;
422 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
423 struct cvmx_mio_boot_loc_cfgx_s cn56xx;
424 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
425 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
426 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
427};
428
429union cvmx_mio_boot_loc_dat {
430 uint64_t u64;
431 struct cvmx_mio_boot_loc_dat_s {
432 uint64_t data:64;
433 } s;
434 struct cvmx_mio_boot_loc_dat_s cn30xx;
435 struct cvmx_mio_boot_loc_dat_s cn31xx;
436 struct cvmx_mio_boot_loc_dat_s cn38xx;
437 struct cvmx_mio_boot_loc_dat_s cn38xxp2;
438 struct cvmx_mio_boot_loc_dat_s cn50xx;
439 struct cvmx_mio_boot_loc_dat_s cn52xx;
440 struct cvmx_mio_boot_loc_dat_s cn52xxp1;
441 struct cvmx_mio_boot_loc_dat_s cn56xx;
442 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
443 struct cvmx_mio_boot_loc_dat_s cn58xx;
444 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
445};
446
447union cvmx_mio_boot_pin_defs {
448 uint64_t u64;
449 struct cvmx_mio_boot_pin_defs_s {
450 uint64_t reserved_16_63:48;
451 uint64_t ale:1;
452 uint64_t width:1;
453 uint64_t dmack_p2:1;
454 uint64_t dmack_p1:1;
455 uint64_t dmack_p0:1;
456 uint64_t term:2;
457 uint64_t nand:1;
458 uint64_t reserved_0_7:8;
459 } s;
460 struct cvmx_mio_boot_pin_defs_cn52xx {
461 uint64_t reserved_16_63:48;
462 uint64_t ale:1;
463 uint64_t width:1;
464 uint64_t reserved_13_13:1;
465 uint64_t dmack_p1:1;
466 uint64_t dmack_p0:1;
467 uint64_t term:2;
468 uint64_t nand:1;
469 uint64_t reserved_0_7:8;
470 } cn52xx;
471 struct cvmx_mio_boot_pin_defs_cn56xx {
472 uint64_t reserved_16_63:48;
473 uint64_t ale:1;
474 uint64_t width:1;
475 uint64_t dmack_p2:1;
476 uint64_t dmack_p1:1;
477 uint64_t dmack_p0:1;
478 uint64_t term:2;
479 uint64_t reserved_0_8:9;
480 } cn56xx;
481};
482
483union cvmx_mio_boot_reg_cfgx {
484 uint64_t u64;
485 struct cvmx_mio_boot_reg_cfgx_s {
486 uint64_t reserved_44_63:20;
487 uint64_t dmack:2;
488 uint64_t tim_mult:2;
489 uint64_t rd_dly:3;
490 uint64_t sam:1;
491 uint64_t we_ext:2;
492 uint64_t oe_ext:2;
493 uint64_t en:1;
494 uint64_t orbit:1;
495 uint64_t ale:1;
496 uint64_t width:1;
497 uint64_t size:12;
498 uint64_t base:16;
499 } s;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx {
501 uint64_t reserved_37_63:27;
502 uint64_t sam:1;
503 uint64_t we_ext:2;
504 uint64_t oe_ext:2;
505 uint64_t en:1;
506 uint64_t orbit:1;
507 uint64_t ale:1;
508 uint64_t width:1;
509 uint64_t size:12;
510 uint64_t base:16;
511 } cn30xx;
512 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
513 struct cvmx_mio_boot_reg_cfgx_cn38xx {
514 uint64_t reserved_32_63:32;
515 uint64_t en:1;
516 uint64_t orbit:1;
517 uint64_t reserved_28_29:2;
518 uint64_t size:12;
519 uint64_t base:16;
520 } cn38xx;
521 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
522 struct cvmx_mio_boot_reg_cfgx_cn50xx {
523 uint64_t reserved_42_63:22;
524 uint64_t tim_mult:2;
525 uint64_t rd_dly:3;
526 uint64_t sam:1;
527 uint64_t we_ext:2;
528 uint64_t oe_ext:2;
529 uint64_t en:1;
530 uint64_t orbit:1;
531 uint64_t ale:1;
532 uint64_t width:1;
533 uint64_t size:12;
534 uint64_t base:16;
535 } cn50xx;
536 struct cvmx_mio_boot_reg_cfgx_s cn52xx;
537 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
538 struct cvmx_mio_boot_reg_cfgx_s cn56xx;
539 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
540 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
541 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
542};
543
544union cvmx_mio_boot_reg_timx {
545 uint64_t u64;
546 struct cvmx_mio_boot_reg_timx_s {
547 uint64_t pagem:1;
548 uint64_t waitm:1;
549 uint64_t pages:2;
550 uint64_t ale:6;
551 uint64_t page:6;
552 uint64_t wait:6;
553 uint64_t pause:6;
554 uint64_t wr_hld:6;
555 uint64_t rd_hld:6;
556 uint64_t we:6;
557 uint64_t oe:6;
558 uint64_t ce:6;
559 uint64_t adr:6;
560 } s;
561 struct cvmx_mio_boot_reg_timx_s cn30xx;
562 struct cvmx_mio_boot_reg_timx_s cn31xx;
563 struct cvmx_mio_boot_reg_timx_cn38xx {
564 uint64_t pagem:1;
565 uint64_t waitm:1;
566 uint64_t pages:2;
567 uint64_t reserved_54_59:6;
568 uint64_t page:6;
569 uint64_t wait:6;
570 uint64_t pause:6;
571 uint64_t wr_hld:6;
572 uint64_t rd_hld:6;
573 uint64_t we:6;
574 uint64_t oe:6;
575 uint64_t ce:6;
576 uint64_t adr:6;
577 } cn38xx;
578 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
579 struct cvmx_mio_boot_reg_timx_s cn50xx;
580 struct cvmx_mio_boot_reg_timx_s cn52xx;
581 struct cvmx_mio_boot_reg_timx_s cn52xxp1;
582 struct cvmx_mio_boot_reg_timx_s cn56xx;
583 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
584 struct cvmx_mio_boot_reg_timx_s cn58xx;
585 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
586};
587
588union cvmx_mio_boot_thr {
589 uint64_t u64;
590 struct cvmx_mio_boot_thr_s {
591 uint64_t reserved_22_63:42;
592 uint64_t dma_thr:6;
593 uint64_t reserved_14_15:2;
594 uint64_t fif_cnt:6;
595 uint64_t reserved_6_7:2;
596 uint64_t fif_thr:6;
597 } s;
598 struct cvmx_mio_boot_thr_cn30xx {
599 uint64_t reserved_14_63:50;
600 uint64_t fif_cnt:6;
601 uint64_t reserved_6_7:2;
602 uint64_t fif_thr:6;
603 } cn30xx;
604 struct cvmx_mio_boot_thr_cn30xx cn31xx;
605 struct cvmx_mio_boot_thr_cn30xx cn38xx;
606 struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
607 struct cvmx_mio_boot_thr_cn30xx cn50xx;
608 struct cvmx_mio_boot_thr_s cn52xx;
609 struct cvmx_mio_boot_thr_s cn52xxp1;
610 struct cvmx_mio_boot_thr_s cn56xx;
611 struct cvmx_mio_boot_thr_s cn56xxp1;
612 struct cvmx_mio_boot_thr_cn30xx cn58xx;
613 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
614};
615
616union cvmx_mio_fus_bnk_datx {
617 uint64_t u64;
618 struct cvmx_mio_fus_bnk_datx_s {
619 uint64_t dat:64;
620 } s;
621 struct cvmx_mio_fus_bnk_datx_s cn50xx;
622 struct cvmx_mio_fus_bnk_datx_s cn52xx;
623 struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
624 struct cvmx_mio_fus_bnk_datx_s cn56xx;
625 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
626 struct cvmx_mio_fus_bnk_datx_s cn58xx;
627 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
628};
629
630union cvmx_mio_fus_dat0 {
631 uint64_t u64;
632 struct cvmx_mio_fus_dat0_s {
633 uint64_t reserved_32_63:32;
634 uint64_t man_info:32;
635 } s;
636 struct cvmx_mio_fus_dat0_s cn30xx;
637 struct cvmx_mio_fus_dat0_s cn31xx;
638 struct cvmx_mio_fus_dat0_s cn38xx;
639 struct cvmx_mio_fus_dat0_s cn38xxp2;
640 struct cvmx_mio_fus_dat0_s cn50xx;
641 struct cvmx_mio_fus_dat0_s cn52xx;
642 struct cvmx_mio_fus_dat0_s cn52xxp1;
643 struct cvmx_mio_fus_dat0_s cn56xx;
644 struct cvmx_mio_fus_dat0_s cn56xxp1;
645 struct cvmx_mio_fus_dat0_s cn58xx;
646 struct cvmx_mio_fus_dat0_s cn58xxp1;
647};
648
649union cvmx_mio_fus_dat1 {
650 uint64_t u64;
651 struct cvmx_mio_fus_dat1_s {
652 uint64_t reserved_32_63:32;
653 uint64_t man_info:32;
654 } s;
655 struct cvmx_mio_fus_dat1_s cn30xx;
656 struct cvmx_mio_fus_dat1_s cn31xx;
657 struct cvmx_mio_fus_dat1_s cn38xx;
658 struct cvmx_mio_fus_dat1_s cn38xxp2;
659 struct cvmx_mio_fus_dat1_s cn50xx;
660 struct cvmx_mio_fus_dat1_s cn52xx;
661 struct cvmx_mio_fus_dat1_s cn52xxp1;
662 struct cvmx_mio_fus_dat1_s cn56xx;
663 struct cvmx_mio_fus_dat1_s cn56xxp1;
664 struct cvmx_mio_fus_dat1_s cn58xx;
665 struct cvmx_mio_fus_dat1_s cn58xxp1;
666};
667
668union cvmx_mio_fus_dat2 {
669 uint64_t u64;
670 struct cvmx_mio_fus_dat2_s {
671 uint64_t reserved_34_63:30;
672 uint64_t fus318:1;
673 uint64_t raid_en:1;
674 uint64_t reserved_30_31:2;
675 uint64_t nokasu:1;
676 uint64_t nodfa_cp2:1;
677 uint64_t nomul:1;
678 uint64_t nocrypto:1;
679 uint64_t rst_sht:1;
680 uint64_t bist_dis:1;
681 uint64_t chip_id:8;
682 uint64_t reserved_0_15:16;
683 } s;
684 struct cvmx_mio_fus_dat2_cn30xx {
685 uint64_t reserved_29_63:35;
686 uint64_t nodfa_cp2:1;
687 uint64_t nomul:1;
688 uint64_t nocrypto:1;
689 uint64_t rst_sht:1;
690 uint64_t bist_dis:1;
691 uint64_t chip_id:8;
692 uint64_t pll_off:4;
693 uint64_t reserved_1_11:11;
694 uint64_t pp_dis:1;
695 } cn30xx;
696 struct cvmx_mio_fus_dat2_cn31xx {
697 uint64_t reserved_29_63:35;
698 uint64_t nodfa_cp2:1;
699 uint64_t nomul:1;
700 uint64_t nocrypto:1;
701 uint64_t rst_sht:1;
702 uint64_t bist_dis:1;
703 uint64_t chip_id:8;
704 uint64_t pll_off:4;
705 uint64_t reserved_2_11:10;
706 uint64_t pp_dis:2;
707 } cn31xx;
708 struct cvmx_mio_fus_dat2_cn38xx {
709 uint64_t reserved_29_63:35;
710 uint64_t nodfa_cp2:1;
711 uint64_t nomul:1;
712 uint64_t nocrypto:1;
713 uint64_t rst_sht:1;
714 uint64_t bist_dis:1;
715 uint64_t chip_id:8;
716 uint64_t pp_dis:16;
717 } cn38xx;
718 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
719 struct cvmx_mio_fus_dat2_cn50xx {
720 uint64_t reserved_34_63:30;
721 uint64_t fus318:1;
722 uint64_t raid_en:1;
723 uint64_t reserved_30_31:2;
724 uint64_t nokasu:1;
725 uint64_t nodfa_cp2:1;
726 uint64_t nomul:1;
727 uint64_t nocrypto:1;
728 uint64_t rst_sht:1;
729 uint64_t bist_dis:1;
730 uint64_t chip_id:8;
731 uint64_t reserved_2_15:14;
732 uint64_t pp_dis:2;
733 } cn50xx;
734 struct cvmx_mio_fus_dat2_cn52xx {
735 uint64_t reserved_34_63:30;
736 uint64_t fus318:1;
737 uint64_t raid_en:1;
738 uint64_t reserved_30_31:2;
739 uint64_t nokasu:1;
740 uint64_t nodfa_cp2:1;
741 uint64_t nomul:1;
742 uint64_t nocrypto:1;
743 uint64_t rst_sht:1;
744 uint64_t bist_dis:1;
745 uint64_t chip_id:8;
746 uint64_t reserved_4_15:12;
747 uint64_t pp_dis:4;
748 } cn52xx;
749 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
750 struct cvmx_mio_fus_dat2_cn56xx {
751 uint64_t reserved_34_63:30;
752 uint64_t fus318:1;
753 uint64_t raid_en:1;
754 uint64_t reserved_30_31:2;
755 uint64_t nokasu:1;
756 uint64_t nodfa_cp2:1;
757 uint64_t nomul:1;
758 uint64_t nocrypto:1;
759 uint64_t rst_sht:1;
760 uint64_t bist_dis:1;
761 uint64_t chip_id:8;
762 uint64_t reserved_12_15:4;
763 uint64_t pp_dis:12;
764 } cn56xx;
765 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
766 struct cvmx_mio_fus_dat2_cn58xx {
767 uint64_t reserved_30_63:34;
768 uint64_t nokasu:1;
769 uint64_t nodfa_cp2:1;
770 uint64_t nomul:1;
771 uint64_t nocrypto:1;
772 uint64_t rst_sht:1;
773 uint64_t bist_dis:1;
774 uint64_t chip_id:8;
775 uint64_t pp_dis:16;
776 } cn58xx;
777 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
778};
779
780union cvmx_mio_fus_dat3 {
781 uint64_t u64;
782 struct cvmx_mio_fus_dat3_s {
783 uint64_t reserved_32_63:32;
784 uint64_t pll_div4:1;
785 uint64_t zip_crip:2;
786 uint64_t bar2_en:1;
787 uint64_t efus_lck:1;
788 uint64_t efus_ign:1;
789 uint64_t nozip:1;
790 uint64_t nodfa_dte:1;
791 uint64_t icache:24;
792 } s;
793 struct cvmx_mio_fus_dat3_cn30xx {
794 uint64_t reserved_32_63:32;
795 uint64_t pll_div4:1;
796 uint64_t reserved_29_30:2;
797 uint64_t bar2_en:1;
798 uint64_t efus_lck:1;
799 uint64_t efus_ign:1;
800 uint64_t nozip:1;
801 uint64_t nodfa_dte:1;
802 uint64_t icache:24;
803 } cn30xx;
804 struct cvmx_mio_fus_dat3_s cn31xx;
805 struct cvmx_mio_fus_dat3_cn38xx {
806 uint64_t reserved_31_63:33;
807 uint64_t zip_crip:2;
808 uint64_t bar2_en:1;
809 uint64_t efus_lck:1;
810 uint64_t efus_ign:1;
811 uint64_t nozip:1;
812 uint64_t nodfa_dte:1;
813 uint64_t icache:24;
814 } cn38xx;
815 struct cvmx_mio_fus_dat3_cn38xxp2 {
816 uint64_t reserved_29_63:35;
817 uint64_t bar2_en:1;
818 uint64_t efus_lck:1;
819 uint64_t efus_ign:1;
820 uint64_t nozip:1;
821 uint64_t nodfa_dte:1;
822 uint64_t icache:24;
823 } cn38xxp2;
824 struct cvmx_mio_fus_dat3_cn38xx cn50xx;
825 struct cvmx_mio_fus_dat3_cn38xx cn52xx;
826 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
827 struct cvmx_mio_fus_dat3_cn38xx cn56xx;
828 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
829 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
830 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
831};
832
833union cvmx_mio_fus_ema {
834 uint64_t u64;
835 struct cvmx_mio_fus_ema_s {
836 uint64_t reserved_7_63:57;
837 uint64_t eff_ema:3;
838 uint64_t reserved_3_3:1;
839 uint64_t ema:3;
840 } s;
841 struct cvmx_mio_fus_ema_s cn50xx;
842 struct cvmx_mio_fus_ema_s cn52xx;
843 struct cvmx_mio_fus_ema_s cn52xxp1;
844 struct cvmx_mio_fus_ema_s cn56xx;
845 struct cvmx_mio_fus_ema_s cn56xxp1;
846 struct cvmx_mio_fus_ema_cn58xx {
847 uint64_t reserved_2_63:62;
848 uint64_t ema:2;
849 } cn58xx;
850 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
851};
852
853union cvmx_mio_fus_pdf {
854 uint64_t u64;
855 struct cvmx_mio_fus_pdf_s {
856 uint64_t pdf:64;
857 } s;
858 struct cvmx_mio_fus_pdf_s cn50xx;
859 struct cvmx_mio_fus_pdf_s cn52xx;
860 struct cvmx_mio_fus_pdf_s cn52xxp1;
861 struct cvmx_mio_fus_pdf_s cn56xx;
862 struct cvmx_mio_fus_pdf_s cn56xxp1;
863 struct cvmx_mio_fus_pdf_s cn58xx;
864};
865
866union cvmx_mio_fus_pll {
867 uint64_t u64;
868 struct cvmx_mio_fus_pll_s {
869 uint64_t reserved_2_63:62;
870 uint64_t rfslip:1;
871 uint64_t fbslip:1;
872 } s;
873 struct cvmx_mio_fus_pll_s cn50xx;
874 struct cvmx_mio_fus_pll_s cn52xx;
875 struct cvmx_mio_fus_pll_s cn52xxp1;
876 struct cvmx_mio_fus_pll_s cn56xx;
877 struct cvmx_mio_fus_pll_s cn56xxp1;
878 struct cvmx_mio_fus_pll_s cn58xx;
879 struct cvmx_mio_fus_pll_s cn58xxp1;
880};
881
882union cvmx_mio_fus_prog {
883 uint64_t u64;
884 struct cvmx_mio_fus_prog_s {
885 uint64_t reserved_1_63:63;
886 uint64_t prog:1;
887 } s;
888 struct cvmx_mio_fus_prog_s cn30xx;
889 struct cvmx_mio_fus_prog_s cn31xx;
890 struct cvmx_mio_fus_prog_s cn38xx;
891 struct cvmx_mio_fus_prog_s cn38xxp2;
892 struct cvmx_mio_fus_prog_s cn50xx;
893 struct cvmx_mio_fus_prog_s cn52xx;
894 struct cvmx_mio_fus_prog_s cn52xxp1;
895 struct cvmx_mio_fus_prog_s cn56xx;
896 struct cvmx_mio_fus_prog_s cn56xxp1;
897 struct cvmx_mio_fus_prog_s cn58xx;
898 struct cvmx_mio_fus_prog_s cn58xxp1;
899};
900
901union cvmx_mio_fus_prog_times {
902 uint64_t u64;
903 struct cvmx_mio_fus_prog_times_s {
904 uint64_t reserved_33_63:31;
905 uint64_t prog_pin:1;
906 uint64_t out:8;
907 uint64_t sclk_lo:4;
908 uint64_t sclk_hi:12;
909 uint64_t setup:8;
910 } s;
911 struct cvmx_mio_fus_prog_times_s cn50xx;
912 struct cvmx_mio_fus_prog_times_s cn52xx;
913 struct cvmx_mio_fus_prog_times_s cn52xxp1;
914 struct cvmx_mio_fus_prog_times_s cn56xx;
915 struct cvmx_mio_fus_prog_times_s cn56xxp1;
916 struct cvmx_mio_fus_prog_times_s cn58xx;
917 struct cvmx_mio_fus_prog_times_s cn58xxp1;
918};
919
920union cvmx_mio_fus_rcmd {
921 uint64_t u64;
922 struct cvmx_mio_fus_rcmd_s {
923 uint64_t reserved_24_63:40;
924 uint64_t dat:8;
925 uint64_t reserved_13_15:3;
926 uint64_t pend:1;
927 uint64_t reserved_9_11:3;
928 uint64_t efuse:1;
929 uint64_t addr:8;
930 } s;
931 struct cvmx_mio_fus_rcmd_cn30xx {
932 uint64_t reserved_24_63:40;
933 uint64_t dat:8;
934 uint64_t reserved_13_15:3;
935 uint64_t pend:1;
936 uint64_t reserved_9_11:3;
937 uint64_t efuse:1;
938 uint64_t reserved_7_7:1;
939 uint64_t addr:7;
940 } cn30xx;
941 struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
942 struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
943 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
944 struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
945 struct cvmx_mio_fus_rcmd_s cn52xx;
946 struct cvmx_mio_fus_rcmd_s cn52xxp1;
947 struct cvmx_mio_fus_rcmd_s cn56xx;
948 struct cvmx_mio_fus_rcmd_s cn56xxp1;
949 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
950 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
951};
952
953union cvmx_mio_fus_spr_repair_res {
954 uint64_t u64;
955 struct cvmx_mio_fus_spr_repair_res_s {
956 uint64_t reserved_42_63:22;
957 uint64_t repair2:14;
958 uint64_t repair1:14;
959 uint64_t repair0:14;
960 } s;
961 struct cvmx_mio_fus_spr_repair_res_s cn30xx;
962 struct cvmx_mio_fus_spr_repair_res_s cn31xx;
963 struct cvmx_mio_fus_spr_repair_res_s cn38xx;
964 struct cvmx_mio_fus_spr_repair_res_s cn50xx;
965 struct cvmx_mio_fus_spr_repair_res_s cn52xx;
966 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
967 struct cvmx_mio_fus_spr_repair_res_s cn56xx;
968 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
969 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
970 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
971};
972
973union cvmx_mio_fus_spr_repair_sum {
974 uint64_t u64;
975 struct cvmx_mio_fus_spr_repair_sum_s {
976 uint64_t reserved_1_63:63;
977 uint64_t too_many:1;
978 } s;
979 struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
980 struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
981 struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
982 struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
983 struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
984 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
985 struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
986 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
987 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
988 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
989};
990
991union cvmx_mio_fus_unlock {
992 uint64_t u64;
993 struct cvmx_mio_fus_unlock_s {
994 uint64_t reserved_24_63:40;
995 uint64_t key:24;
996 } s;
997 struct cvmx_mio_fus_unlock_s cn30xx;
998 struct cvmx_mio_fus_unlock_s cn31xx;
999};
1000
1001union cvmx_mio_fus_wadr {
1002 uint64_t u64;
1003 struct cvmx_mio_fus_wadr_s {
1004 uint64_t reserved_10_63:54;
1005 uint64_t addr:10;
1006 } s;
1007 struct cvmx_mio_fus_wadr_s cn30xx;
1008 struct cvmx_mio_fus_wadr_s cn31xx;
1009 struct cvmx_mio_fus_wadr_s cn38xx;
1010 struct cvmx_mio_fus_wadr_s cn38xxp2;
1011 struct cvmx_mio_fus_wadr_cn50xx {
1012 uint64_t reserved_2_63:62;
1013 uint64_t addr:2;
1014 } cn50xx;
1015 struct cvmx_mio_fus_wadr_cn52xx {
1016 uint64_t reserved_3_63:61;
1017 uint64_t addr:3;
1018 } cn52xx;
1019 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
1020 struct cvmx_mio_fus_wadr_cn52xx cn56xx;
1021 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1022 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1023 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1024};
1025
1026union cvmx_mio_ndf_dma_cfg {
1027 uint64_t u64;
1028 struct cvmx_mio_ndf_dma_cfg_s {
1029 uint64_t en:1;
1030 uint64_t rw:1;
1031 uint64_t clr:1;
1032 uint64_t reserved_60_60:1;
1033 uint64_t swap32:1;
1034 uint64_t swap16:1;
1035 uint64_t swap8:1;
1036 uint64_t endian:1;
1037 uint64_t size:20;
1038 uint64_t adr:36;
1039 } s;
1040 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1041};
1042
1043union cvmx_mio_ndf_dma_int {
1044 uint64_t u64;
1045 struct cvmx_mio_ndf_dma_int_s {
1046 uint64_t reserved_1_63:63;
1047 uint64_t done:1;
1048 } s;
1049 struct cvmx_mio_ndf_dma_int_s cn52xx;
1050};
1051
1052union cvmx_mio_ndf_dma_int_en {
1053 uint64_t u64;
1054 struct cvmx_mio_ndf_dma_int_en_s {
1055 uint64_t reserved_1_63:63;
1056 uint64_t done:1;
1057 } s;
1058 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1059};
1060
1061union cvmx_mio_pll_ctl {
1062 uint64_t u64;
1063 struct cvmx_mio_pll_ctl_s {
1064 uint64_t reserved_5_63:59;
1065 uint64_t bw_ctl:5;
1066 } s;
1067 struct cvmx_mio_pll_ctl_s cn30xx;
1068 struct cvmx_mio_pll_ctl_s cn31xx;
1069};
1070
1071union cvmx_mio_pll_setting {
1072 uint64_t u64;
1073 struct cvmx_mio_pll_setting_s {
1074 uint64_t reserved_17_63:47;
1075 uint64_t setting:17;
1076 } s;
1077 struct cvmx_mio_pll_setting_s cn30xx;
1078 struct cvmx_mio_pll_setting_s cn31xx;
1079};
1080
1081union cvmx_mio_twsx_int {
1082 uint64_t u64;
1083 struct cvmx_mio_twsx_int_s {
1084 uint64_t reserved_12_63:52;
1085 uint64_t scl:1;
1086 uint64_t sda:1;
1087 uint64_t scl_ovr:1;
1088 uint64_t sda_ovr:1;
1089 uint64_t reserved_7_7:1;
1090 uint64_t core_en:1;
1091 uint64_t ts_en:1;
1092 uint64_t st_en:1;
1093 uint64_t reserved_3_3:1;
1094 uint64_t core_int:1;
1095 uint64_t ts_int:1;
1096 uint64_t st_int:1;
1097 } s;
1098 struct cvmx_mio_twsx_int_s cn30xx;
1099 struct cvmx_mio_twsx_int_s cn31xx;
1100 struct cvmx_mio_twsx_int_s cn38xx;
1101 struct cvmx_mio_twsx_int_cn38xxp2 {
1102 uint64_t reserved_7_63:57;
1103 uint64_t core_en:1;
1104 uint64_t ts_en:1;
1105 uint64_t st_en:1;
1106 uint64_t reserved_3_3:1;
1107 uint64_t core_int:1;
1108 uint64_t ts_int:1;
1109 uint64_t st_int:1;
1110 } cn38xxp2;
1111 struct cvmx_mio_twsx_int_s cn50xx;
1112 struct cvmx_mio_twsx_int_s cn52xx;
1113 struct cvmx_mio_twsx_int_s cn52xxp1;
1114 struct cvmx_mio_twsx_int_s cn56xx;
1115 struct cvmx_mio_twsx_int_s cn56xxp1;
1116 struct cvmx_mio_twsx_int_s cn58xx;
1117 struct cvmx_mio_twsx_int_s cn58xxp1;
1118};
1119
1120union cvmx_mio_twsx_sw_twsi {
1121 uint64_t u64;
1122 struct cvmx_mio_twsx_sw_twsi_s {
1123 uint64_t v:1;
1124 uint64_t slonly:1;
1125 uint64_t eia:1;
1126 uint64_t op:4;
1127 uint64_t r:1;
1128 uint64_t sovr:1;
1129 uint64_t size:3;
1130 uint64_t scr:2;
1131 uint64_t a:10;
1132 uint64_t ia:5;
1133 uint64_t eop_ia:3;
1134 uint64_t d:32;
1135 } s;
1136 struct cvmx_mio_twsx_sw_twsi_s cn30xx;
1137 struct cvmx_mio_twsx_sw_twsi_s cn31xx;
1138 struct cvmx_mio_twsx_sw_twsi_s cn38xx;
1139 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
1140 struct cvmx_mio_twsx_sw_twsi_s cn50xx;
1141 struct cvmx_mio_twsx_sw_twsi_s cn52xx;
1142 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
1143 struct cvmx_mio_twsx_sw_twsi_s cn56xx;
1144 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1145 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1146 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
1147};
1148
1149union cvmx_mio_twsx_sw_twsi_ext {
1150 uint64_t u64;
1151 struct cvmx_mio_twsx_sw_twsi_ext_s {
1152 uint64_t reserved_40_63:24;
1153 uint64_t ia:8;
1154 uint64_t d:32;
1155 } s;
1156 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
1157 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
1158 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
1159 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
1160 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
1161 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
1162 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
1163 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
1164 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1165 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1166 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
1167};
1168
1169union cvmx_mio_twsx_twsi_sw {
1170 uint64_t u64;
1171 struct cvmx_mio_twsx_twsi_sw_s {
1172 uint64_t v:2;
1173 uint64_t reserved_32_61:30;
1174 uint64_t d:32;
1175 } s;
1176 struct cvmx_mio_twsx_twsi_sw_s cn30xx;
1177 struct cvmx_mio_twsx_twsi_sw_s cn31xx;
1178 struct cvmx_mio_twsx_twsi_sw_s cn38xx;
1179 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
1180 struct cvmx_mio_twsx_twsi_sw_s cn50xx;
1181 struct cvmx_mio_twsx_twsi_sw_s cn52xx;
1182 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
1183 struct cvmx_mio_twsx_twsi_sw_s cn56xx;
1184 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1185 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1186 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
1187};
1188
1189union cvmx_mio_uartx_dlh {
1190 uint64_t u64;
1191 struct cvmx_mio_uartx_dlh_s {
1192 uint64_t reserved_8_63:56;
1193 uint64_t dlh:8;
1194 } s;
1195 struct cvmx_mio_uartx_dlh_s cn30xx;
1196 struct cvmx_mio_uartx_dlh_s cn31xx;
1197 struct cvmx_mio_uartx_dlh_s cn38xx;
1198 struct cvmx_mio_uartx_dlh_s cn38xxp2;
1199 struct cvmx_mio_uartx_dlh_s cn50xx;
1200 struct cvmx_mio_uartx_dlh_s cn52xx;
1201 struct cvmx_mio_uartx_dlh_s cn52xxp1;
1202 struct cvmx_mio_uartx_dlh_s cn56xx;
1203 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1204 struct cvmx_mio_uartx_dlh_s cn58xx;
1205 struct cvmx_mio_uartx_dlh_s cn58xxp1;
1206};
1207
1208union cvmx_mio_uartx_dll {
1209 uint64_t u64;
1210 struct cvmx_mio_uartx_dll_s {
1211 uint64_t reserved_8_63:56;
1212 uint64_t dll:8;
1213 } s;
1214 struct cvmx_mio_uartx_dll_s cn30xx;
1215 struct cvmx_mio_uartx_dll_s cn31xx;
1216 struct cvmx_mio_uartx_dll_s cn38xx;
1217 struct cvmx_mio_uartx_dll_s cn38xxp2;
1218 struct cvmx_mio_uartx_dll_s cn50xx;
1219 struct cvmx_mio_uartx_dll_s cn52xx;
1220 struct cvmx_mio_uartx_dll_s cn52xxp1;
1221 struct cvmx_mio_uartx_dll_s cn56xx;
1222 struct cvmx_mio_uartx_dll_s cn56xxp1;
1223 struct cvmx_mio_uartx_dll_s cn58xx;
1224 struct cvmx_mio_uartx_dll_s cn58xxp1;
1225};
1226
1227union cvmx_mio_uartx_far {
1228 uint64_t u64;
1229 struct cvmx_mio_uartx_far_s {
1230 uint64_t reserved_1_63:63;
1231 uint64_t far:1;
1232 } s;
1233 struct cvmx_mio_uartx_far_s cn30xx;
1234 struct cvmx_mio_uartx_far_s cn31xx;
1235 struct cvmx_mio_uartx_far_s cn38xx;
1236 struct cvmx_mio_uartx_far_s cn38xxp2;
1237 struct cvmx_mio_uartx_far_s cn50xx;
1238 struct cvmx_mio_uartx_far_s cn52xx;
1239 struct cvmx_mio_uartx_far_s cn52xxp1;
1240 struct cvmx_mio_uartx_far_s cn56xx;
1241 struct cvmx_mio_uartx_far_s cn56xxp1;
1242 struct cvmx_mio_uartx_far_s cn58xx;
1243 struct cvmx_mio_uartx_far_s cn58xxp1;
1244};
1245
1246union cvmx_mio_uartx_fcr {
1247 uint64_t u64;
1248 struct cvmx_mio_uartx_fcr_s {
1249 uint64_t reserved_8_63:56;
1250 uint64_t rxtrig:2;
1251 uint64_t txtrig:2;
1252 uint64_t reserved_3_3:1;
1253 uint64_t txfr:1;
1254 uint64_t rxfr:1;
1255 uint64_t en:1;
1256 } s;
1257 struct cvmx_mio_uartx_fcr_s cn30xx;
1258 struct cvmx_mio_uartx_fcr_s cn31xx;
1259 struct cvmx_mio_uartx_fcr_s cn38xx;
1260 struct cvmx_mio_uartx_fcr_s cn38xxp2;
1261 struct cvmx_mio_uartx_fcr_s cn50xx;
1262 struct cvmx_mio_uartx_fcr_s cn52xx;
1263 struct cvmx_mio_uartx_fcr_s cn52xxp1;
1264 struct cvmx_mio_uartx_fcr_s cn56xx;
1265 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1266 struct cvmx_mio_uartx_fcr_s cn58xx;
1267 struct cvmx_mio_uartx_fcr_s cn58xxp1;
1268};
1269
1270union cvmx_mio_uartx_htx {
1271 uint64_t u64;
1272 struct cvmx_mio_uartx_htx_s {
1273 uint64_t reserved_1_63:63;
1274 uint64_t htx:1;
1275 } s;
1276 struct cvmx_mio_uartx_htx_s cn30xx;
1277 struct cvmx_mio_uartx_htx_s cn31xx;
1278 struct cvmx_mio_uartx_htx_s cn38xx;
1279 struct cvmx_mio_uartx_htx_s cn38xxp2;
1280 struct cvmx_mio_uartx_htx_s cn50xx;
1281 struct cvmx_mio_uartx_htx_s cn52xx;
1282 struct cvmx_mio_uartx_htx_s cn52xxp1;
1283 struct cvmx_mio_uartx_htx_s cn56xx;
1284 struct cvmx_mio_uartx_htx_s cn56xxp1;
1285 struct cvmx_mio_uartx_htx_s cn58xx;
1286 struct cvmx_mio_uartx_htx_s cn58xxp1;
1287};
1288
1289union cvmx_mio_uartx_ier {
1290 uint64_t u64;
1291 struct cvmx_mio_uartx_ier_s {
1292 uint64_t reserved_8_63:56;
1293 uint64_t ptime:1;
1294 uint64_t reserved_4_6:3;
1295 uint64_t edssi:1;
1296 uint64_t elsi:1;
1297 uint64_t etbei:1;
1298 uint64_t erbfi:1;
1299 } s;
1300 struct cvmx_mio_uartx_ier_s cn30xx;
1301 struct cvmx_mio_uartx_ier_s cn31xx;
1302 struct cvmx_mio_uartx_ier_s cn38xx;
1303 struct cvmx_mio_uartx_ier_s cn38xxp2;
1304 struct cvmx_mio_uartx_ier_s cn50xx;
1305 struct cvmx_mio_uartx_ier_s cn52xx;
1306 struct cvmx_mio_uartx_ier_s cn52xxp1;
1307 struct cvmx_mio_uartx_ier_s cn56xx;
1308 struct cvmx_mio_uartx_ier_s cn56xxp1;
1309 struct cvmx_mio_uartx_ier_s cn58xx;
1310 struct cvmx_mio_uartx_ier_s cn58xxp1;
1311};
1312
1313union cvmx_mio_uartx_iir {
1314 uint64_t u64;
1315 struct cvmx_mio_uartx_iir_s {
1316 uint64_t reserved_8_63:56;
1317 uint64_t fen:2;
1318 uint64_t reserved_4_5:2;
1319 uint64_t iid:4;
1320 } s;
1321 struct cvmx_mio_uartx_iir_s cn30xx;
1322 struct cvmx_mio_uartx_iir_s cn31xx;
1323 struct cvmx_mio_uartx_iir_s cn38xx;
1324 struct cvmx_mio_uartx_iir_s cn38xxp2;
1325 struct cvmx_mio_uartx_iir_s cn50xx;
1326 struct cvmx_mio_uartx_iir_s cn52xx;
1327 struct cvmx_mio_uartx_iir_s cn52xxp1;
1328 struct cvmx_mio_uartx_iir_s cn56xx;
1329 struct cvmx_mio_uartx_iir_s cn56xxp1;
1330 struct cvmx_mio_uartx_iir_s cn58xx;
1331 struct cvmx_mio_uartx_iir_s cn58xxp1;
1332};
1333
1334union cvmx_mio_uartx_lcr {
1335 uint64_t u64;
1336 struct cvmx_mio_uartx_lcr_s {
1337 uint64_t reserved_8_63:56;
1338 uint64_t dlab:1;
1339 uint64_t brk:1;
1340 uint64_t reserved_5_5:1;
1341 uint64_t eps:1;
1342 uint64_t pen:1;
1343 uint64_t stop:1;
1344 uint64_t cls:2;
1345 } s;
1346 struct cvmx_mio_uartx_lcr_s cn30xx;
1347 struct cvmx_mio_uartx_lcr_s cn31xx;
1348 struct cvmx_mio_uartx_lcr_s cn38xx;
1349 struct cvmx_mio_uartx_lcr_s cn38xxp2;
1350 struct cvmx_mio_uartx_lcr_s cn50xx;
1351 struct cvmx_mio_uartx_lcr_s cn52xx;
1352 struct cvmx_mio_uartx_lcr_s cn52xxp1;
1353 struct cvmx_mio_uartx_lcr_s cn56xx;
1354 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1355 struct cvmx_mio_uartx_lcr_s cn58xx;
1356 struct cvmx_mio_uartx_lcr_s cn58xxp1;
1357};
1358
1359union cvmx_mio_uartx_lsr {
1360 uint64_t u64;
1361 struct cvmx_mio_uartx_lsr_s {
1362 uint64_t reserved_8_63:56;
1363 uint64_t ferr:1;
1364 uint64_t temt:1;
1365 uint64_t thre:1;
1366 uint64_t bi:1;
1367 uint64_t fe:1;
1368 uint64_t pe:1;
1369 uint64_t oe:1;
1370 uint64_t dr:1;
1371 } s;
1372 struct cvmx_mio_uartx_lsr_s cn30xx;
1373 struct cvmx_mio_uartx_lsr_s cn31xx;
1374 struct cvmx_mio_uartx_lsr_s cn38xx;
1375 struct cvmx_mio_uartx_lsr_s cn38xxp2;
1376 struct cvmx_mio_uartx_lsr_s cn50xx;
1377 struct cvmx_mio_uartx_lsr_s cn52xx;
1378 struct cvmx_mio_uartx_lsr_s cn52xxp1;
1379 struct cvmx_mio_uartx_lsr_s cn56xx;
1380 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1381 struct cvmx_mio_uartx_lsr_s cn58xx;
1382 struct cvmx_mio_uartx_lsr_s cn58xxp1;
1383};
1384
1385union cvmx_mio_uartx_mcr {
1386 uint64_t u64;
1387 struct cvmx_mio_uartx_mcr_s {
1388 uint64_t reserved_6_63:58;
1389 uint64_t afce:1;
1390 uint64_t loop:1;
1391 uint64_t out2:1;
1392 uint64_t out1:1;
1393 uint64_t rts:1;
1394 uint64_t dtr:1;
1395 } s;
1396 struct cvmx_mio_uartx_mcr_s cn30xx;
1397 struct cvmx_mio_uartx_mcr_s cn31xx;
1398 struct cvmx_mio_uartx_mcr_s cn38xx;
1399 struct cvmx_mio_uartx_mcr_s cn38xxp2;
1400 struct cvmx_mio_uartx_mcr_s cn50xx;
1401 struct cvmx_mio_uartx_mcr_s cn52xx;
1402 struct cvmx_mio_uartx_mcr_s cn52xxp1;
1403 struct cvmx_mio_uartx_mcr_s cn56xx;
1404 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1405 struct cvmx_mio_uartx_mcr_s cn58xx;
1406 struct cvmx_mio_uartx_mcr_s cn58xxp1;
1407};
1408
1409union cvmx_mio_uartx_msr {
1410 uint64_t u64;
1411 struct cvmx_mio_uartx_msr_s {
1412 uint64_t reserved_8_63:56;
1413 uint64_t dcd:1;
1414 uint64_t ri:1;
1415 uint64_t dsr:1;
1416 uint64_t cts:1;
1417 uint64_t ddcd:1;
1418 uint64_t teri:1;
1419 uint64_t ddsr:1;
1420 uint64_t dcts:1;
1421 } s;
1422 struct cvmx_mio_uartx_msr_s cn30xx;
1423 struct cvmx_mio_uartx_msr_s cn31xx;
1424 struct cvmx_mio_uartx_msr_s cn38xx;
1425 struct cvmx_mio_uartx_msr_s cn38xxp2;
1426 struct cvmx_mio_uartx_msr_s cn50xx;
1427 struct cvmx_mio_uartx_msr_s cn52xx;
1428 struct cvmx_mio_uartx_msr_s cn52xxp1;
1429 struct cvmx_mio_uartx_msr_s cn56xx;
1430 struct cvmx_mio_uartx_msr_s cn56xxp1;
1431 struct cvmx_mio_uartx_msr_s cn58xx;
1432 struct cvmx_mio_uartx_msr_s cn58xxp1;
1433};
1434
1435union cvmx_mio_uartx_rbr {
1436 uint64_t u64;
1437 struct cvmx_mio_uartx_rbr_s {
1438 uint64_t reserved_8_63:56;
1439 uint64_t rbr:8;
1440 } s;
1441 struct cvmx_mio_uartx_rbr_s cn30xx;
1442 struct cvmx_mio_uartx_rbr_s cn31xx;
1443 struct cvmx_mio_uartx_rbr_s cn38xx;
1444 struct cvmx_mio_uartx_rbr_s cn38xxp2;
1445 struct cvmx_mio_uartx_rbr_s cn50xx;
1446 struct cvmx_mio_uartx_rbr_s cn52xx;
1447 struct cvmx_mio_uartx_rbr_s cn52xxp1;
1448 struct cvmx_mio_uartx_rbr_s cn56xx;
1449 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1450 struct cvmx_mio_uartx_rbr_s cn58xx;
1451 struct cvmx_mio_uartx_rbr_s cn58xxp1;
1452};
1453
1454union cvmx_mio_uartx_rfl {
1455 uint64_t u64;
1456 struct cvmx_mio_uartx_rfl_s {
1457 uint64_t reserved_7_63:57;
1458 uint64_t rfl:7;
1459 } s;
1460 struct cvmx_mio_uartx_rfl_s cn30xx;
1461 struct cvmx_mio_uartx_rfl_s cn31xx;
1462 struct cvmx_mio_uartx_rfl_s cn38xx;
1463 struct cvmx_mio_uartx_rfl_s cn38xxp2;
1464 struct cvmx_mio_uartx_rfl_s cn50xx;
1465 struct cvmx_mio_uartx_rfl_s cn52xx;
1466 struct cvmx_mio_uartx_rfl_s cn52xxp1;
1467 struct cvmx_mio_uartx_rfl_s cn56xx;
1468 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1469 struct cvmx_mio_uartx_rfl_s cn58xx;
1470 struct cvmx_mio_uartx_rfl_s cn58xxp1;
1471};
1472
1473union cvmx_mio_uartx_rfw {
1474 uint64_t u64;
1475 struct cvmx_mio_uartx_rfw_s {
1476 uint64_t reserved_10_63:54;
1477 uint64_t rffe:1;
1478 uint64_t rfpe:1;
1479 uint64_t rfwd:8;
1480 } s;
1481 struct cvmx_mio_uartx_rfw_s cn30xx;
1482 struct cvmx_mio_uartx_rfw_s cn31xx;
1483 struct cvmx_mio_uartx_rfw_s cn38xx;
1484 struct cvmx_mio_uartx_rfw_s cn38xxp2;
1485 struct cvmx_mio_uartx_rfw_s cn50xx;
1486 struct cvmx_mio_uartx_rfw_s cn52xx;
1487 struct cvmx_mio_uartx_rfw_s cn52xxp1;
1488 struct cvmx_mio_uartx_rfw_s cn56xx;
1489 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1490 struct cvmx_mio_uartx_rfw_s cn58xx;
1491 struct cvmx_mio_uartx_rfw_s cn58xxp1;
1492};
1493
1494union cvmx_mio_uartx_sbcr {
1495 uint64_t u64;
1496 struct cvmx_mio_uartx_sbcr_s {
1497 uint64_t reserved_1_63:63;
1498 uint64_t sbcr:1;
1499 } s;
1500 struct cvmx_mio_uartx_sbcr_s cn30xx;
1501 struct cvmx_mio_uartx_sbcr_s cn31xx;
1502 struct cvmx_mio_uartx_sbcr_s cn38xx;
1503 struct cvmx_mio_uartx_sbcr_s cn38xxp2;
1504 struct cvmx_mio_uartx_sbcr_s cn50xx;
1505 struct cvmx_mio_uartx_sbcr_s cn52xx;
1506 struct cvmx_mio_uartx_sbcr_s cn52xxp1;
1507 struct cvmx_mio_uartx_sbcr_s cn56xx;
1508 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1509 struct cvmx_mio_uartx_sbcr_s cn58xx;
1510 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
1511};
1512
1513union cvmx_mio_uartx_scr {
1514 uint64_t u64;
1515 struct cvmx_mio_uartx_scr_s {
1516 uint64_t reserved_8_63:56;
1517 uint64_t scr:8;
1518 } s;
1519 struct cvmx_mio_uartx_scr_s cn30xx;
1520 struct cvmx_mio_uartx_scr_s cn31xx;
1521 struct cvmx_mio_uartx_scr_s cn38xx;
1522 struct cvmx_mio_uartx_scr_s cn38xxp2;
1523 struct cvmx_mio_uartx_scr_s cn50xx;
1524 struct cvmx_mio_uartx_scr_s cn52xx;
1525 struct cvmx_mio_uartx_scr_s cn52xxp1;
1526 struct cvmx_mio_uartx_scr_s cn56xx;
1527 struct cvmx_mio_uartx_scr_s cn56xxp1;
1528 struct cvmx_mio_uartx_scr_s cn58xx;
1529 struct cvmx_mio_uartx_scr_s cn58xxp1;
1530};
1531
1532union cvmx_mio_uartx_sfe {
1533 uint64_t u64;
1534 struct cvmx_mio_uartx_sfe_s {
1535 uint64_t reserved_1_63:63;
1536 uint64_t sfe:1;
1537 } s;
1538 struct cvmx_mio_uartx_sfe_s cn30xx;
1539 struct cvmx_mio_uartx_sfe_s cn31xx;
1540 struct cvmx_mio_uartx_sfe_s cn38xx;
1541 struct cvmx_mio_uartx_sfe_s cn38xxp2;
1542 struct cvmx_mio_uartx_sfe_s cn50xx;
1543 struct cvmx_mio_uartx_sfe_s cn52xx;
1544 struct cvmx_mio_uartx_sfe_s cn52xxp1;
1545 struct cvmx_mio_uartx_sfe_s cn56xx;
1546 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1547 struct cvmx_mio_uartx_sfe_s cn58xx;
1548 struct cvmx_mio_uartx_sfe_s cn58xxp1;
1549};
1550
1551union cvmx_mio_uartx_srr {
1552 uint64_t u64;
1553 struct cvmx_mio_uartx_srr_s {
1554 uint64_t reserved_3_63:61;
1555 uint64_t stfr:1;
1556 uint64_t srfr:1;
1557 uint64_t usr:1;
1558 } s;
1559 struct cvmx_mio_uartx_srr_s cn30xx;
1560 struct cvmx_mio_uartx_srr_s cn31xx;
1561 struct cvmx_mio_uartx_srr_s cn38xx;
1562 struct cvmx_mio_uartx_srr_s cn38xxp2;
1563 struct cvmx_mio_uartx_srr_s cn50xx;
1564 struct cvmx_mio_uartx_srr_s cn52xx;
1565 struct cvmx_mio_uartx_srr_s cn52xxp1;
1566 struct cvmx_mio_uartx_srr_s cn56xx;
1567 struct cvmx_mio_uartx_srr_s cn56xxp1;
1568 struct cvmx_mio_uartx_srr_s cn58xx;
1569 struct cvmx_mio_uartx_srr_s cn58xxp1;
1570};
1571
1572union cvmx_mio_uartx_srt {
1573 uint64_t u64;
1574 struct cvmx_mio_uartx_srt_s {
1575 uint64_t reserved_2_63:62;
1576 uint64_t srt:2;
1577 } s;
1578 struct cvmx_mio_uartx_srt_s cn30xx;
1579 struct cvmx_mio_uartx_srt_s cn31xx;
1580 struct cvmx_mio_uartx_srt_s cn38xx;
1581 struct cvmx_mio_uartx_srt_s cn38xxp2;
1582 struct cvmx_mio_uartx_srt_s cn50xx;
1583 struct cvmx_mio_uartx_srt_s cn52xx;
1584 struct cvmx_mio_uartx_srt_s cn52xxp1;
1585 struct cvmx_mio_uartx_srt_s cn56xx;
1586 struct cvmx_mio_uartx_srt_s cn56xxp1;
1587 struct cvmx_mio_uartx_srt_s cn58xx;
1588 struct cvmx_mio_uartx_srt_s cn58xxp1;
1589};
1590
1591union cvmx_mio_uartx_srts {
1592 uint64_t u64;
1593 struct cvmx_mio_uartx_srts_s {
1594 uint64_t reserved_1_63:63;
1595 uint64_t srts:1;
1596 } s;
1597 struct cvmx_mio_uartx_srts_s cn30xx;
1598 struct cvmx_mio_uartx_srts_s cn31xx;
1599 struct cvmx_mio_uartx_srts_s cn38xx;
1600 struct cvmx_mio_uartx_srts_s cn38xxp2;
1601 struct cvmx_mio_uartx_srts_s cn50xx;
1602 struct cvmx_mio_uartx_srts_s cn52xx;
1603 struct cvmx_mio_uartx_srts_s cn52xxp1;
1604 struct cvmx_mio_uartx_srts_s cn56xx;
1605 struct cvmx_mio_uartx_srts_s cn56xxp1;
1606 struct cvmx_mio_uartx_srts_s cn58xx;
1607 struct cvmx_mio_uartx_srts_s cn58xxp1;
1608};
1609
1610union cvmx_mio_uartx_stt {
1611 uint64_t u64;
1612 struct cvmx_mio_uartx_stt_s {
1613 uint64_t reserved_2_63:62;
1614 uint64_t stt:2;
1615 } s;
1616 struct cvmx_mio_uartx_stt_s cn30xx;
1617 struct cvmx_mio_uartx_stt_s cn31xx;
1618 struct cvmx_mio_uartx_stt_s cn38xx;
1619 struct cvmx_mio_uartx_stt_s cn38xxp2;
1620 struct cvmx_mio_uartx_stt_s cn50xx;
1621 struct cvmx_mio_uartx_stt_s cn52xx;
1622 struct cvmx_mio_uartx_stt_s cn52xxp1;
1623 struct cvmx_mio_uartx_stt_s cn56xx;
1624 struct cvmx_mio_uartx_stt_s cn56xxp1;
1625 struct cvmx_mio_uartx_stt_s cn58xx;
1626 struct cvmx_mio_uartx_stt_s cn58xxp1;
1627};
1628
1629union cvmx_mio_uartx_tfl {
1630 uint64_t u64;
1631 struct cvmx_mio_uartx_tfl_s {
1632 uint64_t reserved_7_63:57;
1633 uint64_t tfl:7;
1634 } s;
1635 struct cvmx_mio_uartx_tfl_s cn30xx;
1636 struct cvmx_mio_uartx_tfl_s cn31xx;
1637 struct cvmx_mio_uartx_tfl_s cn38xx;
1638 struct cvmx_mio_uartx_tfl_s cn38xxp2;
1639 struct cvmx_mio_uartx_tfl_s cn50xx;
1640 struct cvmx_mio_uartx_tfl_s cn52xx;
1641 struct cvmx_mio_uartx_tfl_s cn52xxp1;
1642 struct cvmx_mio_uartx_tfl_s cn56xx;
1643 struct cvmx_mio_uartx_tfl_s cn56xxp1;
1644 struct cvmx_mio_uartx_tfl_s cn58xx;
1645 struct cvmx_mio_uartx_tfl_s cn58xxp1;
1646};
1647
1648union cvmx_mio_uartx_tfr {
1649 uint64_t u64;
1650 struct cvmx_mio_uartx_tfr_s {
1651 uint64_t reserved_8_63:56;
1652 uint64_t tfr:8;
1653 } s;
1654 struct cvmx_mio_uartx_tfr_s cn30xx;
1655 struct cvmx_mio_uartx_tfr_s cn31xx;
1656 struct cvmx_mio_uartx_tfr_s cn38xx;
1657 struct cvmx_mio_uartx_tfr_s cn38xxp2;
1658 struct cvmx_mio_uartx_tfr_s cn50xx;
1659 struct cvmx_mio_uartx_tfr_s cn52xx;
1660 struct cvmx_mio_uartx_tfr_s cn52xxp1;
1661 struct cvmx_mio_uartx_tfr_s cn56xx;
1662 struct cvmx_mio_uartx_tfr_s cn56xxp1;
1663 struct cvmx_mio_uartx_tfr_s cn58xx;
1664 struct cvmx_mio_uartx_tfr_s cn58xxp1;
1665};
1666
1667union cvmx_mio_uartx_thr {
1668 uint64_t u64;
1669 struct cvmx_mio_uartx_thr_s {
1670 uint64_t reserved_8_63:56;
1671 uint64_t thr:8;
1672 } s;
1673 struct cvmx_mio_uartx_thr_s cn30xx;
1674 struct cvmx_mio_uartx_thr_s cn31xx;
1675 struct cvmx_mio_uartx_thr_s cn38xx;
1676 struct cvmx_mio_uartx_thr_s cn38xxp2;
1677 struct cvmx_mio_uartx_thr_s cn50xx;
1678 struct cvmx_mio_uartx_thr_s cn52xx;
1679 struct cvmx_mio_uartx_thr_s cn52xxp1;
1680 struct cvmx_mio_uartx_thr_s cn56xx;
1681 struct cvmx_mio_uartx_thr_s cn56xxp1;
1682 struct cvmx_mio_uartx_thr_s cn58xx;
1683 struct cvmx_mio_uartx_thr_s cn58xxp1;
1684};
1685
1686union cvmx_mio_uartx_usr {
1687 uint64_t u64;
1688 struct cvmx_mio_uartx_usr_s {
1689 uint64_t reserved_5_63:59;
1690 uint64_t rff:1;
1691 uint64_t rfne:1;
1692 uint64_t tfe:1;
1693 uint64_t tfnf:1;
1694 uint64_t busy:1;
1695 } s;
1696 struct cvmx_mio_uartx_usr_s cn30xx;
1697 struct cvmx_mio_uartx_usr_s cn31xx;
1698 struct cvmx_mio_uartx_usr_s cn38xx;
1699 struct cvmx_mio_uartx_usr_s cn38xxp2;
1700 struct cvmx_mio_uartx_usr_s cn50xx;
1701 struct cvmx_mio_uartx_usr_s cn52xx;
1702 struct cvmx_mio_uartx_usr_s cn52xxp1;
1703 struct cvmx_mio_uartx_usr_s cn56xx;
1704 struct cvmx_mio_uartx_usr_s cn56xxp1;
1705 struct cvmx_mio_uartx_usr_s cn58xx;
1706 struct cvmx_mio_uartx_usr_s cn58xxp1;
1707};
1708
1709union cvmx_mio_uart2_dlh {
1710 uint64_t u64;
1711 struct cvmx_mio_uart2_dlh_s {
1712 uint64_t reserved_8_63:56;
1713 uint64_t dlh:8;
1714 } s;
1715 struct cvmx_mio_uart2_dlh_s cn52xx;
1716 struct cvmx_mio_uart2_dlh_s cn52xxp1;
1717};
1718
1719union cvmx_mio_uart2_dll {
1720 uint64_t u64;
1721 struct cvmx_mio_uart2_dll_s {
1722 uint64_t reserved_8_63:56;
1723 uint64_t dll:8;
1724 } s;
1725 struct cvmx_mio_uart2_dll_s cn52xx;
1726 struct cvmx_mio_uart2_dll_s cn52xxp1;
1727};
1728
1729union cvmx_mio_uart2_far {
1730 uint64_t u64;
1731 struct cvmx_mio_uart2_far_s {
1732 uint64_t reserved_1_63:63;
1733 uint64_t far:1;
1734 } s;
1735 struct cvmx_mio_uart2_far_s cn52xx;
1736 struct cvmx_mio_uart2_far_s cn52xxp1;
1737};
1738
1739union cvmx_mio_uart2_fcr {
1740 uint64_t u64;
1741 struct cvmx_mio_uart2_fcr_s {
1742 uint64_t reserved_8_63:56;
1743 uint64_t rxtrig:2;
1744 uint64_t txtrig:2;
1745 uint64_t reserved_3_3:1;
1746 uint64_t txfr:1;
1747 uint64_t rxfr:1;
1748 uint64_t en:1;
1749 } s;
1750 struct cvmx_mio_uart2_fcr_s cn52xx;
1751 struct cvmx_mio_uart2_fcr_s cn52xxp1;
1752};
1753
1754union cvmx_mio_uart2_htx {
1755 uint64_t u64;
1756 struct cvmx_mio_uart2_htx_s {
1757 uint64_t reserved_1_63:63;
1758 uint64_t htx:1;
1759 } s;
1760 struct cvmx_mio_uart2_htx_s cn52xx;
1761 struct cvmx_mio_uart2_htx_s cn52xxp1;
1762};
1763
1764union cvmx_mio_uart2_ier {
1765 uint64_t u64;
1766 struct cvmx_mio_uart2_ier_s {
1767 uint64_t reserved_8_63:56;
1768 uint64_t ptime:1;
1769 uint64_t reserved_4_6:3;
1770 uint64_t edssi:1;
1771 uint64_t elsi:1;
1772 uint64_t etbei:1;
1773 uint64_t erbfi:1;
1774 } s;
1775 struct cvmx_mio_uart2_ier_s cn52xx;
1776 struct cvmx_mio_uart2_ier_s cn52xxp1;
1777};
1778
1779union cvmx_mio_uart2_iir {
1780 uint64_t u64;
1781 struct cvmx_mio_uart2_iir_s {
1782 uint64_t reserved_8_63:56;
1783 uint64_t fen:2;
1784 uint64_t reserved_4_5:2;
1785 uint64_t iid:4;
1786 } s;
1787 struct cvmx_mio_uart2_iir_s cn52xx;
1788 struct cvmx_mio_uart2_iir_s cn52xxp1;
1789};
1790
1791union cvmx_mio_uart2_lcr {
1792 uint64_t u64;
1793 struct cvmx_mio_uart2_lcr_s {
1794 uint64_t reserved_8_63:56;
1795 uint64_t dlab:1;
1796 uint64_t brk:1;
1797 uint64_t reserved_5_5:1;
1798 uint64_t eps:1;
1799 uint64_t pen:1;
1800 uint64_t stop:1;
1801 uint64_t cls:2;
1802 } s;
1803 struct cvmx_mio_uart2_lcr_s cn52xx;
1804 struct cvmx_mio_uart2_lcr_s cn52xxp1;
1805};
1806
1807union cvmx_mio_uart2_lsr {
1808 uint64_t u64;
1809 struct cvmx_mio_uart2_lsr_s {
1810 uint64_t reserved_8_63:56;
1811 uint64_t ferr:1;
1812 uint64_t temt:1;
1813 uint64_t thre:1;
1814 uint64_t bi:1;
1815 uint64_t fe:1;
1816 uint64_t pe:1;
1817 uint64_t oe:1;
1818 uint64_t dr:1;
1819 } s;
1820 struct cvmx_mio_uart2_lsr_s cn52xx;
1821 struct cvmx_mio_uart2_lsr_s cn52xxp1;
1822};
1823
1824union cvmx_mio_uart2_mcr {
1825 uint64_t u64;
1826 struct cvmx_mio_uart2_mcr_s {
1827 uint64_t reserved_6_63:58;
1828 uint64_t afce:1;
1829 uint64_t loop:1;
1830 uint64_t out2:1;
1831 uint64_t out1:1;
1832 uint64_t rts:1;
1833 uint64_t dtr:1;
1834 } s;
1835 struct cvmx_mio_uart2_mcr_s cn52xx;
1836 struct cvmx_mio_uart2_mcr_s cn52xxp1;
1837};
1838
1839union cvmx_mio_uart2_msr {
1840 uint64_t u64;
1841 struct cvmx_mio_uart2_msr_s {
1842 uint64_t reserved_8_63:56;
1843 uint64_t dcd:1;
1844 uint64_t ri:1;
1845 uint64_t dsr:1;
1846 uint64_t cts:1;
1847 uint64_t ddcd:1;
1848 uint64_t teri:1;
1849 uint64_t ddsr:1;
1850 uint64_t dcts:1;
1851 } s;
1852 struct cvmx_mio_uart2_msr_s cn52xx;
1853 struct cvmx_mio_uart2_msr_s cn52xxp1;
1854};
1855
1856union cvmx_mio_uart2_rbr {
1857 uint64_t u64;
1858 struct cvmx_mio_uart2_rbr_s {
1859 uint64_t reserved_8_63:56;
1860 uint64_t rbr:8;
1861 } s;
1862 struct cvmx_mio_uart2_rbr_s cn52xx;
1863 struct cvmx_mio_uart2_rbr_s cn52xxp1;
1864};
1865
1866union cvmx_mio_uart2_rfl {
1867 uint64_t u64;
1868 struct cvmx_mio_uart2_rfl_s {
1869 uint64_t reserved_7_63:57;
1870 uint64_t rfl:7;
1871 } s;
1872 struct cvmx_mio_uart2_rfl_s cn52xx;
1873 struct cvmx_mio_uart2_rfl_s cn52xxp1;
1874};
1875
1876union cvmx_mio_uart2_rfw {
1877 uint64_t u64;
1878 struct cvmx_mio_uart2_rfw_s {
1879 uint64_t reserved_10_63:54;
1880 uint64_t rffe:1;
1881 uint64_t rfpe:1;
1882 uint64_t rfwd:8;
1883 } s;
1884 struct cvmx_mio_uart2_rfw_s cn52xx;
1885 struct cvmx_mio_uart2_rfw_s cn52xxp1;
1886};
1887
1888union cvmx_mio_uart2_sbcr {
1889 uint64_t u64;
1890 struct cvmx_mio_uart2_sbcr_s {
1891 uint64_t reserved_1_63:63;
1892 uint64_t sbcr:1;
1893 } s;
1894 struct cvmx_mio_uart2_sbcr_s cn52xx;
1895 struct cvmx_mio_uart2_sbcr_s cn52xxp1;
1896};
1897
1898union cvmx_mio_uart2_scr {
1899 uint64_t u64;
1900 struct cvmx_mio_uart2_scr_s {
1901 uint64_t reserved_8_63:56;
1902 uint64_t scr:8;
1903 } s;
1904 struct cvmx_mio_uart2_scr_s cn52xx;
1905 struct cvmx_mio_uart2_scr_s cn52xxp1;
1906};
1907
1908union cvmx_mio_uart2_sfe {
1909 uint64_t u64;
1910 struct cvmx_mio_uart2_sfe_s {
1911 uint64_t reserved_1_63:63;
1912 uint64_t sfe:1;
1913 } s;
1914 struct cvmx_mio_uart2_sfe_s cn52xx;
1915 struct cvmx_mio_uart2_sfe_s cn52xxp1;
1916};
1917
1918union cvmx_mio_uart2_srr {
1919 uint64_t u64;
1920 struct cvmx_mio_uart2_srr_s {
1921 uint64_t reserved_3_63:61;
1922 uint64_t stfr:1;
1923 uint64_t srfr:1;
1924 uint64_t usr:1;
1925 } s;
1926 struct cvmx_mio_uart2_srr_s cn52xx;
1927 struct cvmx_mio_uart2_srr_s cn52xxp1;
1928};
1929
1930union cvmx_mio_uart2_srt {
1931 uint64_t u64;
1932 struct cvmx_mio_uart2_srt_s {
1933 uint64_t reserved_2_63:62;
1934 uint64_t srt:2;
1935 } s;
1936 struct cvmx_mio_uart2_srt_s cn52xx;
1937 struct cvmx_mio_uart2_srt_s cn52xxp1;
1938};
1939
1940union cvmx_mio_uart2_srts {
1941 uint64_t u64;
1942 struct cvmx_mio_uart2_srts_s {
1943 uint64_t reserved_1_63:63;
1944 uint64_t srts:1;
1945 } s;
1946 struct cvmx_mio_uart2_srts_s cn52xx;
1947 struct cvmx_mio_uart2_srts_s cn52xxp1;
1948};
1949
1950union cvmx_mio_uart2_stt {
1951 uint64_t u64;
1952 struct cvmx_mio_uart2_stt_s {
1953 uint64_t reserved_2_63:62;
1954 uint64_t stt:2;
1955 } s;
1956 struct cvmx_mio_uart2_stt_s cn52xx;
1957 struct cvmx_mio_uart2_stt_s cn52xxp1;
1958};
1959
1960union cvmx_mio_uart2_tfl {
1961 uint64_t u64;
1962 struct cvmx_mio_uart2_tfl_s {
1963 uint64_t reserved_7_63:57;
1964 uint64_t tfl:7;
1965 } s;
1966 struct cvmx_mio_uart2_tfl_s cn52xx;
1967 struct cvmx_mio_uart2_tfl_s cn52xxp1;
1968};
1969
1970union cvmx_mio_uart2_tfr {
1971 uint64_t u64;
1972 struct cvmx_mio_uart2_tfr_s {
1973 uint64_t reserved_8_63:56;
1974 uint64_t tfr:8;
1975 } s;
1976 struct cvmx_mio_uart2_tfr_s cn52xx;
1977 struct cvmx_mio_uart2_tfr_s cn52xxp1;
1978};
1979
1980union cvmx_mio_uart2_thr {
1981 uint64_t u64;
1982 struct cvmx_mio_uart2_thr_s {
1983 uint64_t reserved_8_63:56;
1984 uint64_t thr:8;
1985 } s;
1986 struct cvmx_mio_uart2_thr_s cn52xx;
1987 struct cvmx_mio_uart2_thr_s cn52xxp1;
1988};
1989
1990union cvmx_mio_uart2_usr {
1991 uint64_t u64;
1992 struct cvmx_mio_uart2_usr_s {
1993 uint64_t reserved_5_63:59;
1994 uint64_t rff:1;
1995 uint64_t rfne:1;
1996 uint64_t tfe:1;
1997 uint64_t tfnf:1;
1998 uint64_t busy:1;
1999 } s;
2000 struct cvmx_mio_uart2_usr_s cn52xx;
2001 struct cvmx_mio_uart2_usr_s cn52xxp1;
2002};
2003
2004#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
new file mode 100644
index 000000000000..38aefa1bab9d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Packet buffer defines.
30 */
31
32#ifndef __CVMX_PACKET_H__
33#define __CVMX_PACKET_H__
34
35/**
36 * This structure defines a buffer pointer on Octeon
37 */
38union cvmx_buf_ptr {
39 void *ptr;
40 uint64_t u64;
41 struct {
42 /* if set, invert the "free" pick of the overall
43 * packet. HW always sets this bit to 0 on inbound
44 * packet */
45 uint64_t i:1;
46
47 /* Indicates the amount to back up to get to the
48 * buffer start in cache lines. In most cases this is
49 * less than one complete cache line, so the value is
50 * zero */
51 uint64_t back:4;
52 /* The pool that the buffer came from / goes to */
53 uint64_t pool:3;
54 /* The size of the segment pointed to by addr (in bytes) */
55 uint64_t size:16;
56 /* Pointer to the first byte of the data, NOT buffer */
57 uint64_t addr:40;
58 } s;
59};
60
61#endif /* __CVMX_PACKET_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
new file mode 100644
index 000000000000..2d82e24be51c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -0,0 +1,698 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_POW_DEFS_H__
29#define __CVMX_POW_DEFS_H__
30
31#define CVMX_POW_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00016700000003F8ull)
33#define CVMX_POW_DS_PC \
34 CVMX_ADD_IO_SEG(0x0001670000000398ull)
35#define CVMX_POW_ECC_ERR \
36 CVMX_ADD_IO_SEG(0x0001670000000218ull)
37#define CVMX_POW_INT_CTL \
38 CVMX_ADD_IO_SEG(0x0001670000000220ull)
39#define CVMX_POW_IQ_CNTX(offset) \
40 CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
41#define CVMX_POW_IQ_COM_CNT \
42 CVMX_ADD_IO_SEG(0x0001670000000388ull)
43#define CVMX_POW_IQ_INT \
44 CVMX_ADD_IO_SEG(0x0001670000000238ull)
45#define CVMX_POW_IQ_INT_EN \
46 CVMX_ADD_IO_SEG(0x0001670000000240ull)
47#define CVMX_POW_IQ_THRX(offset) \
48 CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
49#define CVMX_POW_NOS_CNT \
50 CVMX_ADD_IO_SEG(0x0001670000000228ull)
51#define CVMX_POW_NW_TIM \
52 CVMX_ADD_IO_SEG(0x0001670000000210ull)
53#define CVMX_POW_PF_RST_MSK \
54 CVMX_ADD_IO_SEG(0x0001670000000230ull)
55#define CVMX_POW_PP_GRP_MSKX(offset) \
56 CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
57#define CVMX_POW_QOS_RNDX(offset) \
58 CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
59#define CVMX_POW_QOS_THRX(offset) \
60 CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
61#define CVMX_POW_TS_PC \
62 CVMX_ADD_IO_SEG(0x0001670000000390ull)
63#define CVMX_POW_WA_COM_PC \
64 CVMX_ADD_IO_SEG(0x0001670000000380ull)
65#define CVMX_POW_WA_PCX(offset) \
66 CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
67#define CVMX_POW_WQ_INT \
68 CVMX_ADD_IO_SEG(0x0001670000000200ull)
69#define CVMX_POW_WQ_INT_CNTX(offset) \
70 CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
71#define CVMX_POW_WQ_INT_PC \
72 CVMX_ADD_IO_SEG(0x0001670000000208ull)
73#define CVMX_POW_WQ_INT_THRX(offset) \
74 CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
75#define CVMX_POW_WS_PCX(offset) \
76 CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
77
78union cvmx_pow_bist_stat {
79 uint64_t u64;
80 struct cvmx_pow_bist_stat_s {
81 uint64_t reserved_32_63:32;
82 uint64_t pp:16;
83 uint64_t reserved_0_15:16;
84 } s;
85 struct cvmx_pow_bist_stat_cn30xx {
86 uint64_t reserved_17_63:47;
87 uint64_t pp:1;
88 uint64_t reserved_9_15:7;
89 uint64_t cam:1;
90 uint64_t nbt1:1;
91 uint64_t nbt0:1;
92 uint64_t index:1;
93 uint64_t fidx:1;
94 uint64_t nbr1:1;
95 uint64_t nbr0:1;
96 uint64_t pend:1;
97 uint64_t adr:1;
98 } cn30xx;
99 struct cvmx_pow_bist_stat_cn31xx {
100 uint64_t reserved_18_63:46;
101 uint64_t pp:2;
102 uint64_t reserved_9_15:7;
103 uint64_t cam:1;
104 uint64_t nbt1:1;
105 uint64_t nbt0:1;
106 uint64_t index:1;
107 uint64_t fidx:1;
108 uint64_t nbr1:1;
109 uint64_t nbr0:1;
110 uint64_t pend:1;
111 uint64_t adr:1;
112 } cn31xx;
113 struct cvmx_pow_bist_stat_cn38xx {
114 uint64_t reserved_32_63:32;
115 uint64_t pp:16;
116 uint64_t reserved_10_15:6;
117 uint64_t cam:1;
118 uint64_t nbt:1;
119 uint64_t index:1;
120 uint64_t fidx:1;
121 uint64_t nbr1:1;
122 uint64_t nbr0:1;
123 uint64_t pend1:1;
124 uint64_t pend0:1;
125 uint64_t adr1:1;
126 uint64_t adr0:1;
127 } cn38xx;
128 struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
129 struct cvmx_pow_bist_stat_cn31xx cn50xx;
130 struct cvmx_pow_bist_stat_cn52xx {
131 uint64_t reserved_20_63:44;
132 uint64_t pp:4;
133 uint64_t reserved_9_15:7;
134 uint64_t cam:1;
135 uint64_t nbt1:1;
136 uint64_t nbt0:1;
137 uint64_t index:1;
138 uint64_t fidx:1;
139 uint64_t nbr1:1;
140 uint64_t nbr0:1;
141 uint64_t pend:1;
142 uint64_t adr:1;
143 } cn52xx;
144 struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
145 struct cvmx_pow_bist_stat_cn56xx {
146 uint64_t reserved_28_63:36;
147 uint64_t pp:12;
148 uint64_t reserved_10_15:6;
149 uint64_t cam:1;
150 uint64_t nbt:1;
151 uint64_t index:1;
152 uint64_t fidx:1;
153 uint64_t nbr1:1;
154 uint64_t nbr0:1;
155 uint64_t pend1:1;
156 uint64_t pend0:1;
157 uint64_t adr1:1;
158 uint64_t adr0:1;
159 } cn56xx;
160 struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
161 struct cvmx_pow_bist_stat_cn38xx cn58xx;
162 struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
163};
164
165union cvmx_pow_ds_pc {
166 uint64_t u64;
167 struct cvmx_pow_ds_pc_s {
168 uint64_t reserved_32_63:32;
169 uint64_t ds_pc:32;
170 } s;
171 struct cvmx_pow_ds_pc_s cn30xx;
172 struct cvmx_pow_ds_pc_s cn31xx;
173 struct cvmx_pow_ds_pc_s cn38xx;
174 struct cvmx_pow_ds_pc_s cn38xxp2;
175 struct cvmx_pow_ds_pc_s cn50xx;
176 struct cvmx_pow_ds_pc_s cn52xx;
177 struct cvmx_pow_ds_pc_s cn52xxp1;
178 struct cvmx_pow_ds_pc_s cn56xx;
179 struct cvmx_pow_ds_pc_s cn56xxp1;
180 struct cvmx_pow_ds_pc_s cn58xx;
181 struct cvmx_pow_ds_pc_s cn58xxp1;
182};
183
184union cvmx_pow_ecc_err {
185 uint64_t u64;
186 struct cvmx_pow_ecc_err_s {
187 uint64_t reserved_45_63:19;
188 uint64_t iop_ie:13;
189 uint64_t reserved_29_31:3;
190 uint64_t iop:13;
191 uint64_t reserved_14_15:2;
192 uint64_t rpe_ie:1;
193 uint64_t rpe:1;
194 uint64_t reserved_9_11:3;
195 uint64_t syn:5;
196 uint64_t dbe_ie:1;
197 uint64_t sbe_ie:1;
198 uint64_t dbe:1;
199 uint64_t sbe:1;
200 } s;
201 struct cvmx_pow_ecc_err_s cn30xx;
202 struct cvmx_pow_ecc_err_cn31xx {
203 uint64_t reserved_14_63:50;
204 uint64_t rpe_ie:1;
205 uint64_t rpe:1;
206 uint64_t reserved_9_11:3;
207 uint64_t syn:5;
208 uint64_t dbe_ie:1;
209 uint64_t sbe_ie:1;
210 uint64_t dbe:1;
211 uint64_t sbe:1;
212 } cn31xx;
213 struct cvmx_pow_ecc_err_s cn38xx;
214 struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
215 struct cvmx_pow_ecc_err_s cn50xx;
216 struct cvmx_pow_ecc_err_s cn52xx;
217 struct cvmx_pow_ecc_err_s cn52xxp1;
218 struct cvmx_pow_ecc_err_s cn56xx;
219 struct cvmx_pow_ecc_err_s cn56xxp1;
220 struct cvmx_pow_ecc_err_s cn58xx;
221 struct cvmx_pow_ecc_err_s cn58xxp1;
222};
223
224union cvmx_pow_int_ctl {
225 uint64_t u64;
226 struct cvmx_pow_int_ctl_s {
227 uint64_t reserved_6_63:58;
228 uint64_t pfr_dis:1;
229 uint64_t nbr_thr:5;
230 } s;
231 struct cvmx_pow_int_ctl_s cn30xx;
232 struct cvmx_pow_int_ctl_s cn31xx;
233 struct cvmx_pow_int_ctl_s cn38xx;
234 struct cvmx_pow_int_ctl_s cn38xxp2;
235 struct cvmx_pow_int_ctl_s cn50xx;
236 struct cvmx_pow_int_ctl_s cn52xx;
237 struct cvmx_pow_int_ctl_s cn52xxp1;
238 struct cvmx_pow_int_ctl_s cn56xx;
239 struct cvmx_pow_int_ctl_s cn56xxp1;
240 struct cvmx_pow_int_ctl_s cn58xx;
241 struct cvmx_pow_int_ctl_s cn58xxp1;
242};
243
244union cvmx_pow_iq_cntx {
245 uint64_t u64;
246 struct cvmx_pow_iq_cntx_s {
247 uint64_t reserved_32_63:32;
248 uint64_t iq_cnt:32;
249 } s;
250 struct cvmx_pow_iq_cntx_s cn30xx;
251 struct cvmx_pow_iq_cntx_s cn31xx;
252 struct cvmx_pow_iq_cntx_s cn38xx;
253 struct cvmx_pow_iq_cntx_s cn38xxp2;
254 struct cvmx_pow_iq_cntx_s cn50xx;
255 struct cvmx_pow_iq_cntx_s cn52xx;
256 struct cvmx_pow_iq_cntx_s cn52xxp1;
257 struct cvmx_pow_iq_cntx_s cn56xx;
258 struct cvmx_pow_iq_cntx_s cn56xxp1;
259 struct cvmx_pow_iq_cntx_s cn58xx;
260 struct cvmx_pow_iq_cntx_s cn58xxp1;
261};
262
263union cvmx_pow_iq_com_cnt {
264 uint64_t u64;
265 struct cvmx_pow_iq_com_cnt_s {
266 uint64_t reserved_32_63:32;
267 uint64_t iq_cnt:32;
268 } s;
269 struct cvmx_pow_iq_com_cnt_s cn30xx;
270 struct cvmx_pow_iq_com_cnt_s cn31xx;
271 struct cvmx_pow_iq_com_cnt_s cn38xx;
272 struct cvmx_pow_iq_com_cnt_s cn38xxp2;
273 struct cvmx_pow_iq_com_cnt_s cn50xx;
274 struct cvmx_pow_iq_com_cnt_s cn52xx;
275 struct cvmx_pow_iq_com_cnt_s cn52xxp1;
276 struct cvmx_pow_iq_com_cnt_s cn56xx;
277 struct cvmx_pow_iq_com_cnt_s cn56xxp1;
278 struct cvmx_pow_iq_com_cnt_s cn58xx;
279 struct cvmx_pow_iq_com_cnt_s cn58xxp1;
280};
281
282union cvmx_pow_iq_int {
283 uint64_t u64;
284 struct cvmx_pow_iq_int_s {
285 uint64_t reserved_8_63:56;
286 uint64_t iq_int:8;
287 } s;
288 struct cvmx_pow_iq_int_s cn52xx;
289 struct cvmx_pow_iq_int_s cn52xxp1;
290 struct cvmx_pow_iq_int_s cn56xx;
291 struct cvmx_pow_iq_int_s cn56xxp1;
292};
293
294union cvmx_pow_iq_int_en {
295 uint64_t u64;
296 struct cvmx_pow_iq_int_en_s {
297 uint64_t reserved_8_63:56;
298 uint64_t int_en:8;
299 } s;
300 struct cvmx_pow_iq_int_en_s cn52xx;
301 struct cvmx_pow_iq_int_en_s cn52xxp1;
302 struct cvmx_pow_iq_int_en_s cn56xx;
303 struct cvmx_pow_iq_int_en_s cn56xxp1;
304};
305
306union cvmx_pow_iq_thrx {
307 uint64_t u64;
308 struct cvmx_pow_iq_thrx_s {
309 uint64_t reserved_32_63:32;
310 uint64_t iq_thr:32;
311 } s;
312 struct cvmx_pow_iq_thrx_s cn52xx;
313 struct cvmx_pow_iq_thrx_s cn52xxp1;
314 struct cvmx_pow_iq_thrx_s cn56xx;
315 struct cvmx_pow_iq_thrx_s cn56xxp1;
316};
317
318union cvmx_pow_nos_cnt {
319 uint64_t u64;
320 struct cvmx_pow_nos_cnt_s {
321 uint64_t reserved_12_63:52;
322 uint64_t nos_cnt:12;
323 } s;
324 struct cvmx_pow_nos_cnt_cn30xx {
325 uint64_t reserved_7_63:57;
326 uint64_t nos_cnt:7;
327 } cn30xx;
328 struct cvmx_pow_nos_cnt_cn31xx {
329 uint64_t reserved_9_63:55;
330 uint64_t nos_cnt:9;
331 } cn31xx;
332 struct cvmx_pow_nos_cnt_s cn38xx;
333 struct cvmx_pow_nos_cnt_s cn38xxp2;
334 struct cvmx_pow_nos_cnt_cn31xx cn50xx;
335 struct cvmx_pow_nos_cnt_cn52xx {
336 uint64_t reserved_10_63:54;
337 uint64_t nos_cnt:10;
338 } cn52xx;
339 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
340 struct cvmx_pow_nos_cnt_s cn56xx;
341 struct cvmx_pow_nos_cnt_s cn56xxp1;
342 struct cvmx_pow_nos_cnt_s cn58xx;
343 struct cvmx_pow_nos_cnt_s cn58xxp1;
344};
345
346union cvmx_pow_nw_tim {
347 uint64_t u64;
348 struct cvmx_pow_nw_tim_s {
349 uint64_t reserved_10_63:54;
350 uint64_t nw_tim:10;
351 } s;
352 struct cvmx_pow_nw_tim_s cn30xx;
353 struct cvmx_pow_nw_tim_s cn31xx;
354 struct cvmx_pow_nw_tim_s cn38xx;
355 struct cvmx_pow_nw_tim_s cn38xxp2;
356 struct cvmx_pow_nw_tim_s cn50xx;
357 struct cvmx_pow_nw_tim_s cn52xx;
358 struct cvmx_pow_nw_tim_s cn52xxp1;
359 struct cvmx_pow_nw_tim_s cn56xx;
360 struct cvmx_pow_nw_tim_s cn56xxp1;
361 struct cvmx_pow_nw_tim_s cn58xx;
362 struct cvmx_pow_nw_tim_s cn58xxp1;
363};
364
365union cvmx_pow_pf_rst_msk {
366 uint64_t u64;
367 struct cvmx_pow_pf_rst_msk_s {
368 uint64_t reserved_8_63:56;
369 uint64_t rst_msk:8;
370 } s;
371 struct cvmx_pow_pf_rst_msk_s cn50xx;
372 struct cvmx_pow_pf_rst_msk_s cn52xx;
373 struct cvmx_pow_pf_rst_msk_s cn52xxp1;
374 struct cvmx_pow_pf_rst_msk_s cn56xx;
375 struct cvmx_pow_pf_rst_msk_s cn56xxp1;
376 struct cvmx_pow_pf_rst_msk_s cn58xx;
377 struct cvmx_pow_pf_rst_msk_s cn58xxp1;
378};
379
380union cvmx_pow_pp_grp_mskx {
381 uint64_t u64;
382 struct cvmx_pow_pp_grp_mskx_s {
383 uint64_t reserved_48_63:16;
384 uint64_t qos7_pri:4;
385 uint64_t qos6_pri:4;
386 uint64_t qos5_pri:4;
387 uint64_t qos4_pri:4;
388 uint64_t qos3_pri:4;
389 uint64_t qos2_pri:4;
390 uint64_t qos1_pri:4;
391 uint64_t qos0_pri:4;
392 uint64_t grp_msk:16;
393 } s;
394 struct cvmx_pow_pp_grp_mskx_cn30xx {
395 uint64_t reserved_16_63:48;
396 uint64_t grp_msk:16;
397 } cn30xx;
398 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
399 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
400 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
401 struct cvmx_pow_pp_grp_mskx_s cn50xx;
402 struct cvmx_pow_pp_grp_mskx_s cn52xx;
403 struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
404 struct cvmx_pow_pp_grp_mskx_s cn56xx;
405 struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
406 struct cvmx_pow_pp_grp_mskx_s cn58xx;
407 struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
408};
409
410union cvmx_pow_qos_rndx {
411 uint64_t u64;
412 struct cvmx_pow_qos_rndx_s {
413 uint64_t reserved_32_63:32;
414 uint64_t rnd_p3:8;
415 uint64_t rnd_p2:8;
416 uint64_t rnd_p1:8;
417 uint64_t rnd:8;
418 } s;
419 struct cvmx_pow_qos_rndx_s cn30xx;
420 struct cvmx_pow_qos_rndx_s cn31xx;
421 struct cvmx_pow_qos_rndx_s cn38xx;
422 struct cvmx_pow_qos_rndx_s cn38xxp2;
423 struct cvmx_pow_qos_rndx_s cn50xx;
424 struct cvmx_pow_qos_rndx_s cn52xx;
425 struct cvmx_pow_qos_rndx_s cn52xxp1;
426 struct cvmx_pow_qos_rndx_s cn56xx;
427 struct cvmx_pow_qos_rndx_s cn56xxp1;
428 struct cvmx_pow_qos_rndx_s cn58xx;
429 struct cvmx_pow_qos_rndx_s cn58xxp1;
430};
431
432union cvmx_pow_qos_thrx {
433 uint64_t u64;
434 struct cvmx_pow_qos_thrx_s {
435 uint64_t reserved_60_63:4;
436 uint64_t des_cnt:12;
437 uint64_t buf_cnt:12;
438 uint64_t free_cnt:12;
439 uint64_t reserved_23_23:1;
440 uint64_t max_thr:11;
441 uint64_t reserved_11_11:1;
442 uint64_t min_thr:11;
443 } s;
444 struct cvmx_pow_qos_thrx_cn30xx {
445 uint64_t reserved_55_63:9;
446 uint64_t des_cnt:7;
447 uint64_t reserved_43_47:5;
448 uint64_t buf_cnt:7;
449 uint64_t reserved_31_35:5;
450 uint64_t free_cnt:7;
451 uint64_t reserved_18_23:6;
452 uint64_t max_thr:6;
453 uint64_t reserved_6_11:6;
454 uint64_t min_thr:6;
455 } cn30xx;
456 struct cvmx_pow_qos_thrx_cn31xx {
457 uint64_t reserved_57_63:7;
458 uint64_t des_cnt:9;
459 uint64_t reserved_45_47:3;
460 uint64_t buf_cnt:9;
461 uint64_t reserved_33_35:3;
462 uint64_t free_cnt:9;
463 uint64_t reserved_20_23:4;
464 uint64_t max_thr:8;
465 uint64_t reserved_8_11:4;
466 uint64_t min_thr:8;
467 } cn31xx;
468 struct cvmx_pow_qos_thrx_s cn38xx;
469 struct cvmx_pow_qos_thrx_s cn38xxp2;
470 struct cvmx_pow_qos_thrx_cn31xx cn50xx;
471 struct cvmx_pow_qos_thrx_cn52xx {
472 uint64_t reserved_58_63:6;
473 uint64_t des_cnt:10;
474 uint64_t reserved_46_47:2;
475 uint64_t buf_cnt:10;
476 uint64_t reserved_34_35:2;
477 uint64_t free_cnt:10;
478 uint64_t reserved_21_23:3;
479 uint64_t max_thr:9;
480 uint64_t reserved_9_11:3;
481 uint64_t min_thr:9;
482 } cn52xx;
483 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
484 struct cvmx_pow_qos_thrx_s cn56xx;
485 struct cvmx_pow_qos_thrx_s cn56xxp1;
486 struct cvmx_pow_qos_thrx_s cn58xx;
487 struct cvmx_pow_qos_thrx_s cn58xxp1;
488};
489
490union cvmx_pow_ts_pc {
491 uint64_t u64;
492 struct cvmx_pow_ts_pc_s {
493 uint64_t reserved_32_63:32;
494 uint64_t ts_pc:32;
495 } s;
496 struct cvmx_pow_ts_pc_s cn30xx;
497 struct cvmx_pow_ts_pc_s cn31xx;
498 struct cvmx_pow_ts_pc_s cn38xx;
499 struct cvmx_pow_ts_pc_s cn38xxp2;
500 struct cvmx_pow_ts_pc_s cn50xx;
501 struct cvmx_pow_ts_pc_s cn52xx;
502 struct cvmx_pow_ts_pc_s cn52xxp1;
503 struct cvmx_pow_ts_pc_s cn56xx;
504 struct cvmx_pow_ts_pc_s cn56xxp1;
505 struct cvmx_pow_ts_pc_s cn58xx;
506 struct cvmx_pow_ts_pc_s cn58xxp1;
507};
508
509union cvmx_pow_wa_com_pc {
510 uint64_t u64;
511 struct cvmx_pow_wa_com_pc_s {
512 uint64_t reserved_32_63:32;
513 uint64_t wa_pc:32;
514 } s;
515 struct cvmx_pow_wa_com_pc_s cn30xx;
516 struct cvmx_pow_wa_com_pc_s cn31xx;
517 struct cvmx_pow_wa_com_pc_s cn38xx;
518 struct cvmx_pow_wa_com_pc_s cn38xxp2;
519 struct cvmx_pow_wa_com_pc_s cn50xx;
520 struct cvmx_pow_wa_com_pc_s cn52xx;
521 struct cvmx_pow_wa_com_pc_s cn52xxp1;
522 struct cvmx_pow_wa_com_pc_s cn56xx;
523 struct cvmx_pow_wa_com_pc_s cn56xxp1;
524 struct cvmx_pow_wa_com_pc_s cn58xx;
525 struct cvmx_pow_wa_com_pc_s cn58xxp1;
526};
527
528union cvmx_pow_wa_pcx {
529 uint64_t u64;
530 struct cvmx_pow_wa_pcx_s {
531 uint64_t reserved_32_63:32;
532 uint64_t wa_pc:32;
533 } s;
534 struct cvmx_pow_wa_pcx_s cn30xx;
535 struct cvmx_pow_wa_pcx_s cn31xx;
536 struct cvmx_pow_wa_pcx_s cn38xx;
537 struct cvmx_pow_wa_pcx_s cn38xxp2;
538 struct cvmx_pow_wa_pcx_s cn50xx;
539 struct cvmx_pow_wa_pcx_s cn52xx;
540 struct cvmx_pow_wa_pcx_s cn52xxp1;
541 struct cvmx_pow_wa_pcx_s cn56xx;
542 struct cvmx_pow_wa_pcx_s cn56xxp1;
543 struct cvmx_pow_wa_pcx_s cn58xx;
544 struct cvmx_pow_wa_pcx_s cn58xxp1;
545};
546
547union cvmx_pow_wq_int {
548 uint64_t u64;
549 struct cvmx_pow_wq_int_s {
550 uint64_t reserved_32_63:32;
551 uint64_t iq_dis:16;
552 uint64_t wq_int:16;
553 } s;
554 struct cvmx_pow_wq_int_s cn30xx;
555 struct cvmx_pow_wq_int_s cn31xx;
556 struct cvmx_pow_wq_int_s cn38xx;
557 struct cvmx_pow_wq_int_s cn38xxp2;
558 struct cvmx_pow_wq_int_s cn50xx;
559 struct cvmx_pow_wq_int_s cn52xx;
560 struct cvmx_pow_wq_int_s cn52xxp1;
561 struct cvmx_pow_wq_int_s cn56xx;
562 struct cvmx_pow_wq_int_s cn56xxp1;
563 struct cvmx_pow_wq_int_s cn58xx;
564 struct cvmx_pow_wq_int_s cn58xxp1;
565};
566
567union cvmx_pow_wq_int_cntx {
568 uint64_t u64;
569 struct cvmx_pow_wq_int_cntx_s {
570 uint64_t reserved_28_63:36;
571 uint64_t tc_cnt:4;
572 uint64_t ds_cnt:12;
573 uint64_t iq_cnt:12;
574 } s;
575 struct cvmx_pow_wq_int_cntx_cn30xx {
576 uint64_t reserved_28_63:36;
577 uint64_t tc_cnt:4;
578 uint64_t reserved_19_23:5;
579 uint64_t ds_cnt:7;
580 uint64_t reserved_7_11:5;
581 uint64_t iq_cnt:7;
582 } cn30xx;
583 struct cvmx_pow_wq_int_cntx_cn31xx {
584 uint64_t reserved_28_63:36;
585 uint64_t tc_cnt:4;
586 uint64_t reserved_21_23:3;
587 uint64_t ds_cnt:9;
588 uint64_t reserved_9_11:3;
589 uint64_t iq_cnt:9;
590 } cn31xx;
591 struct cvmx_pow_wq_int_cntx_s cn38xx;
592 struct cvmx_pow_wq_int_cntx_s cn38xxp2;
593 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
594 struct cvmx_pow_wq_int_cntx_cn52xx {
595 uint64_t reserved_28_63:36;
596 uint64_t tc_cnt:4;
597 uint64_t reserved_22_23:2;
598 uint64_t ds_cnt:10;
599 uint64_t reserved_10_11:2;
600 uint64_t iq_cnt:10;
601 } cn52xx;
602 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
603 struct cvmx_pow_wq_int_cntx_s cn56xx;
604 struct cvmx_pow_wq_int_cntx_s cn56xxp1;
605 struct cvmx_pow_wq_int_cntx_s cn58xx;
606 struct cvmx_pow_wq_int_cntx_s cn58xxp1;
607};
608
609union cvmx_pow_wq_int_pc {
610 uint64_t u64;
611 struct cvmx_pow_wq_int_pc_s {
612 uint64_t reserved_60_63:4;
613 uint64_t pc:28;
614 uint64_t reserved_28_31:4;
615 uint64_t pc_thr:20;
616 uint64_t reserved_0_7:8;
617 } s;
618 struct cvmx_pow_wq_int_pc_s cn30xx;
619 struct cvmx_pow_wq_int_pc_s cn31xx;
620 struct cvmx_pow_wq_int_pc_s cn38xx;
621 struct cvmx_pow_wq_int_pc_s cn38xxp2;
622 struct cvmx_pow_wq_int_pc_s cn50xx;
623 struct cvmx_pow_wq_int_pc_s cn52xx;
624 struct cvmx_pow_wq_int_pc_s cn52xxp1;
625 struct cvmx_pow_wq_int_pc_s cn56xx;
626 struct cvmx_pow_wq_int_pc_s cn56xxp1;
627 struct cvmx_pow_wq_int_pc_s cn58xx;
628 struct cvmx_pow_wq_int_pc_s cn58xxp1;
629};
630
631union cvmx_pow_wq_int_thrx {
632 uint64_t u64;
633 struct cvmx_pow_wq_int_thrx_s {
634 uint64_t reserved_29_63:35;
635 uint64_t tc_en:1;
636 uint64_t tc_thr:4;
637 uint64_t reserved_23_23:1;
638 uint64_t ds_thr:11;
639 uint64_t reserved_11_11:1;
640 uint64_t iq_thr:11;
641 } s;
642 struct cvmx_pow_wq_int_thrx_cn30xx {
643 uint64_t reserved_29_63:35;
644 uint64_t tc_en:1;
645 uint64_t tc_thr:4;
646 uint64_t reserved_18_23:6;
647 uint64_t ds_thr:6;
648 uint64_t reserved_6_11:6;
649 uint64_t iq_thr:6;
650 } cn30xx;
651 struct cvmx_pow_wq_int_thrx_cn31xx {
652 uint64_t reserved_29_63:35;
653 uint64_t tc_en:1;
654 uint64_t tc_thr:4;
655 uint64_t reserved_20_23:4;
656 uint64_t ds_thr:8;
657 uint64_t reserved_8_11:4;
658 uint64_t iq_thr:8;
659 } cn31xx;
660 struct cvmx_pow_wq_int_thrx_s cn38xx;
661 struct cvmx_pow_wq_int_thrx_s cn38xxp2;
662 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
663 struct cvmx_pow_wq_int_thrx_cn52xx {
664 uint64_t reserved_29_63:35;
665 uint64_t tc_en:1;
666 uint64_t tc_thr:4;
667 uint64_t reserved_21_23:3;
668 uint64_t ds_thr:9;
669 uint64_t reserved_9_11:3;
670 uint64_t iq_thr:9;
671 } cn52xx;
672 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
673 struct cvmx_pow_wq_int_thrx_s cn56xx;
674 struct cvmx_pow_wq_int_thrx_s cn56xxp1;
675 struct cvmx_pow_wq_int_thrx_s cn58xx;
676 struct cvmx_pow_wq_int_thrx_s cn58xxp1;
677};
678
679union cvmx_pow_ws_pcx {
680 uint64_t u64;
681 struct cvmx_pow_ws_pcx_s {
682 uint64_t reserved_32_63:32;
683 uint64_t ws_pc:32;
684 } s;
685 struct cvmx_pow_ws_pcx_s cn30xx;
686 struct cvmx_pow_ws_pcx_s cn31xx;
687 struct cvmx_pow_ws_pcx_s cn38xx;
688 struct cvmx_pow_ws_pcx_s cn38xxp2;
689 struct cvmx_pow_ws_pcx_s cn50xx;
690 struct cvmx_pow_ws_pcx_s cn52xx;
691 struct cvmx_pow_ws_pcx_s cn52xxp1;
692 struct cvmx_pow_ws_pcx_s cn56xx;
693 struct cvmx_pow_ws_pcx_s cn56xxp1;
694 struct cvmx_pow_ws_pcx_s cn58xx;
695 struct cvmx_pow_ws_pcx_s cn58xxp1;
696};
697
698#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
new file mode 100644
index 000000000000..2fbf0871df11
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -0,0 +1,232 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Implementation of spinlocks for Octeon CVMX. Although similar in
30 * function to Linux kernel spinlocks, they are not compatible.
31 * Octeon CVMX spinlocks are only used to synchronize with the boot
32 * monitor and other non-Linux programs running in the system.
33 */
34
35#ifndef __CVMX_SPINLOCK_H__
36#define __CVMX_SPINLOCK_H__
37
38#include "cvmx-asm.h"
39
40/* Spinlocks for Octeon */
41
42/* define these to enable recursive spinlock debugging */
43/*#define CVMX_SPINLOCK_DEBUG */
44
45/**
46 * Spinlocks for Octeon CVMX
47 */
48typedef struct {
49 volatile uint32_t value;
50} cvmx_spinlock_t;
51
52/* note - macros not expanded in inline ASM, so values hardcoded */
53#define CVMX_SPINLOCK_UNLOCKED_VAL 0
54#define CVMX_SPINLOCK_LOCKED_VAL 1
55
56#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL}
57
58/**
59 * Initialize a spinlock
60 *
61 * @lock: Lock to initialize
62 */
63static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
64{
65 lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
66}
67
68/**
69 * Return non-zero if the spinlock is currently locked
70 *
71 * @lock: Lock to check
72 * Returns Non-zero if locked
73 */
74static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
75{
76 return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
77}
78
79/**
80 * Releases lock
81 *
82 * @lock: pointer to lock structure
83 */
84static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
85{
86 CVMX_SYNCWS;
87 lock->value = 0;
88 CVMX_SYNCWS;
89}
90
91/**
92 * Attempts to take the lock, but does not spin if lock is not available.
93 * May take some time to acquire the lock even if it is available
94 * due to the ll/sc not succeeding.
95 *
96 * @lock: pointer to lock structure
97 *
98 * Returns 0: lock successfully taken
99 * 1: lock not taken, held by someone else
100 * These return values match the Linux semantics.
101 */
102
103static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
104{
105 unsigned int tmp;
106
107 __asm__ __volatile__(".set noreorder \n"
108 "1: ll %[tmp], %[val] \n"
109 /* if lock held, fail immediately */
110 " bnez %[tmp], 2f \n"
111 " li %[tmp], 1 \n"
112 " sc %[tmp], %[val] \n"
113 " beqz %[tmp], 1b \n"
114 " li %[tmp], 0 \n"
115 "2: \n"
116 ".set reorder \n" :
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
118 : : "memory");
119
120 return tmp != 0; /* normalize to 0 or 1 */
121}
122
123/**
124 * Gets lock, spins until lock is taken
125 *
126 * @lock: pointer to lock structure
127 */
128static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
129{
130 unsigned int tmp;
131
132 __asm__ __volatile__(".set noreorder \n"
133 "1: ll %[tmp], %[val] \n"
134 " bnez %[tmp], 1b \n"
135 " li %[tmp], 1 \n"
136 " sc %[tmp], %[val] \n"
137 " beqz %[tmp], 1b \n"
138 " nop \n"
139 ".set reorder \n" :
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
141 : : "memory");
142
143}
144
145/** ********************************************************************
146 * Bit spinlocks
147 * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
148 * The rest of the bits in the word are left undisturbed. This enables more
149 * compact data structures as only 1 bit is consumed for the lock.
150 *
151 */
152
153/**
154 * Gets lock, spins until lock is taken
155 * Preserves the low 31 bits of the 32 bit
156 * word used for the lock.
157 *
158 *
159 * @word: word to lock bit 31 of
160 */
161static inline void cvmx_spinlock_bit_lock(uint32_t *word)
162{
163 unsigned int tmp;
164 unsigned int sav;
165
166 __asm__ __volatile__(".set noreorder \n"
167 ".set noat \n"
168 "1: ll %[tmp], %[val] \n"
169 " bbit1 %[tmp], 31, 1b \n"
170 " li $at, 1 \n"
171 " ins %[tmp], $at, 31, 1 \n"
172 " sc %[tmp], %[val] \n"
173 " beqz %[tmp], 1b \n"
174 " nop \n"
175 ".set at \n"
176 ".set reorder \n" :
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
178 : : "memory");
179
180}
181
182/**
183 * Attempts to get lock, returns immediately with success/failure
184 * Preserves the low 31 bits of the 32 bit
185 * word used for the lock.
186 *
187 *
188 * @word: word to lock bit 31 of
189 * Returns 0: lock successfully taken
190 * 1: lock not taken, held by someone else
191 * These return values match the Linux semantics.
192 */
193static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
194{
195 unsigned int tmp;
196
197 __asm__ __volatile__(".set noreorder\n\t"
198 ".set noat\n"
199 "1: ll %[tmp], %[val] \n"
200 /* if lock held, fail immediately */
201 " bbit1 %[tmp], 31, 2f \n"
202 " li $at, 1 \n"
203 " ins %[tmp], $at, 31, 1 \n"
204 " sc %[tmp], %[val] \n"
205 " beqz %[tmp], 1b \n"
206 " li %[tmp], 0 \n"
207 "2: \n"
208 ".set at \n"
209 ".set reorder \n" :
210 [val] "+m"(*word), [tmp] "=&r"(tmp)
211 : : "memory");
212
213 return tmp != 0; /* normalize to 0 or 1 */
214}
215
216/**
217 * Releases bit lock
218 *
219 * Unconditionally clears bit 31 of the lock word. Note that this is
220 * done non-atomically, as this implementation assumes that the rest
221 * of the bits in the word are protected by the lock.
222 *
223 * @word: word to unlock bit 31 in
224 */
225static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
226{
227 CVMX_SYNCWS;
228 *word &= ~(1UL << 31);
229 CVMX_SYNCWS;
230}
231
232#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
new file mode 100644
index 000000000000..61dd5741afe4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -0,0 +1,152 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board information obtained by the bootloader.
30 */
31
32#ifndef __CVMX_SYSINFO_H__
33#define __CVMX_SYSINFO_H__
34
35#define OCTEON_SERIAL_LEN 20
36/**
37 * Structure describing application specific information.
38 * __cvmx_app_init() populates this from the cvmx boot descriptor.
39 * This structure is private to simple executive applications, so
40 * no versioning is required.
41 *
42 * This structure must be provided with some fields set in order to
43 * use simple executive functions in other applications (Linux kernel,
44 * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is
45 * provided to set the required values in these cases.
46 */
47struct cvmx_sysinfo {
48 /* System wide variables */
49 /* installed DRAM in system, in bytes */
50 uint64_t system_dram_size;
51
52 /* ptr to memory descriptor block */
53 void *phy_mem_desc_ptr;
54
55
56 /* Application image specific variables */
57 /* stack top address (virtual) */
58 uint64_t stack_top;
59 /* heap base address (virtual) */
60 uint64_t heap_base;
61 /* stack size in bytes */
62 uint32_t stack_size;
63 /* heap size in bytes */
64 uint32_t heap_size;
65 /* coremask defining cores running application */
66 uint32_t core_mask;
67 /* Deprecated, use cvmx_coremask_first_core() to select init core */
68 uint32_t init_core;
69
70 /* exception base address, as set by bootloader */
71 uint64_t exception_base_addr;
72
73 /* cpu clock speed in hz */
74 uint32_t cpu_clock_hz;
75
76 /* dram data rate in hz (data rate = 2 * clock rate */
77 uint32_t dram_data_rate_hz;
78
79
80 uint16_t board_type;
81 uint8_t board_rev_major;
82 uint8_t board_rev_minor;
83 uint8_t mac_addr_base[6];
84 uint8_t mac_addr_count;
85 char board_serial_number[OCTEON_SERIAL_LEN];
86 /*
87 * Several boards support compact flash on the Octeon boot
88 * bus. The CF memory spaces may be mapped to different
89 * addresses on different boards. These values will be 0 if
90 * CF is not present. Note that these addresses are physical
91 * addresses, and it is up to the application to use the
92 * proper addressing mode (XKPHYS, KSEG0, etc.)
93 */
94 uint64_t compact_flash_common_base_addr;
95 uint64_t compact_flash_attribute_base_addr;
96 /*
97 * Base address of the LED display (as on EBT3000 board) This
98 * will be 0 if LED display not present. Note that this
99 * address is a physical address, and it is up to the
100 * application to use the proper addressing mode (XKPHYS,
101 * KSEG0, etc.)
102 */
103 uint64_t led_display_base_addr;
104 /* DFA reference clock in hz (if applicable)*/
105 uint32_t dfa_ref_clock_hz;
106 /* configuration flags from bootloader */
107 uint32_t bootloader_config_flags;
108
109 /* Uart number used for console */
110 uint8_t console_uart_num;
111};
112
113/**
114 * This function returns the system/board information as obtained
115 * by the bootloader.
116 *
117 *
118 * Returns Pointer to the boot information structure
119 *
120 */
121
122extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
123
124/**
125 * This function is used in non-simple executive environments (such as
126 * Linux kernel, u-boot, etc.) to configure the minimal fields that
127 * are required to use simple executive files directly.
128 *
129 * Locking (if required) must be handled outside of this
130 * function
131 *
132 * @phy_mem_desc_ptr: Pointer to global physical memory descriptor
133 * (bootmem descriptor) @board_type: Octeon board
134 * type enumeration
135 *
136 * @board_rev_major:
137 * Board major revision
138 * @board_rev_minor:
139 * Board minor revision
140 * @cpu_clock_hz:
141 * CPU clock freqency in hertz
142 *
143 * Returns 0: Failure
144 * 1: success
145 */
146extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
147 uint16_t board_type,
148 uint8_t board_rev_major,
149 uint8_t board_rev_minor,
150 uint32_t cpu_clock_hz);
151
152#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
new file mode 100644
index 000000000000..03fddfa3e928
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -0,0 +1,505 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34#include "cvmx-asm.h"
35#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h"
37
38#include "cvmx-ciu-defs.h"
39#include "cvmx-gpio-defs.h"
40#include "cvmx-iob-defs.h"
41#include "cvmx-ipd-defs.h"
42#include "cvmx-l2c-defs.h"
43#include "cvmx-l2d-defs.h"
44#include "cvmx-l2t-defs.h"
45#include "cvmx-led-defs.h"
46#include "cvmx-mio-defs.h"
47#include "cvmx-pow-defs.h"
48
49#include "cvmx-bootinfo.h"
50#include "cvmx-bootmem.h"
51#include "cvmx-l2c.h"
52
53#ifndef CVMX_ENABLE_DEBUG_PRINTS
54#define CVMX_ENABLE_DEBUG_PRINTS 1
55#endif
56
57#if CVMX_ENABLE_DEBUG_PRINTS
58#define cvmx_dprintf printk
59#else
60#define cvmx_dprintf(...) {}
61#endif
62
63#define CVMX_MAX_CORES (16)
64#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
65#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
66#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
67#define CAST64(v) ((long long)(long)(v))
68#define CASTPTR(type, v) ((type *)(long)(v))
69
70/*
71 * Returns processor ID, different Linux and simple exec versions
72 * provided in the cvmx-app-init*.c files.
73 */
74static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
75static inline uint32_t cvmx_get_proc_id(void)
76{
77 uint32_t id;
78 asm("mfc0 %0, $15,0" : "=r"(id));
79 return id;
80}
81
82/* turn the variable name into a string */
83#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
84#define CVMX_TMP_STR2(x) #x
85
86/**
87 * Builds a bit mask given the required size in bits.
88 *
89 * @bits: Number of bits in the mask
90 * Returns The mask
91 */ static inline uint64_t cvmx_build_mask(uint64_t bits)
92{
93 return ~((~0x0ull) << bits);
94}
95
96/**
97 * Builds a memory address for I/O based on the Major and Sub DID.
98 *
99 * @major_did: 5 bit major did
100 * @sub_did: 3 bit sub did
101 * Returns I/O base address
102 */
103static inline uint64_t cvmx_build_io_address(uint64_t major_did,
104 uint64_t sub_did)
105{
106 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
107}
108
109/**
110 * Perform mask and shift to place the supplied value into
111 * the supplied bit rage.
112 *
113 * Example: cvmx_build_bits(39,24,value)
114 * <pre>
115 * 6 5 4 3 3 2 1
116 * 3 5 7 9 1 3 5 7 0
117 * +-------+-------+-------+-------+-------+-------+-------+------+
118 * 000000000000000000000000___________value000000000000000000000000
119 * </pre>
120 *
121 * @high_bit: Highest bit value can occupy (inclusive) 0-63
122 * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
123 * @value: Value to use
124 * Returns Value masked and shifted
125 */
126static inline uint64_t cvmx_build_bits(uint64_t high_bit,
127 uint64_t low_bit, uint64_t value)
128{
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130}
131
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/**
154 * Convert a memory pointer (void*) into a hardware compatable
155 * memory address (uint64_t). Octeon hardware widgets don't
156 * understand logical addresses.
157 *
158 * @ptr: C style memory pointer
159 * Returns Hardware physical address
160 */
161static inline uint64_t cvmx_ptr_to_phys(void *ptr)
162{
163 if (sizeof(void *) == 8) {
164 /*
165 * We're running in 64 bit mode. Normally this means
166 * that we can use 40 bits of address space (the
167 * hardware limit). Unfortunately there is one case
168 * were we need to limit this to 30 bits, sign
169 * extended 32 bit. Although these are 64 bits wide,
170 * only 30 bits can be used.
171 */
172 if ((CAST64(ptr) >> 62) == 3)
173 return CAST64(ptr) & cvmx_build_mask(30);
174 else
175 return CAST64(ptr) & cvmx_build_mask(40);
176 } else {
177 return (long)(ptr) & 0x1fffffff;
178 }
179}
180
181/**
182 * Convert a hardware physical address (uint64_t) into a
183 * memory pointer (void *).
184 *
185 * @physical_address:
186 * Hardware physical address to memory
187 * Returns Pointer to memory
188 */
189static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
190{
191 if (sizeof(void *) == 8) {
192 /* Just set the top bit, avoiding any TLB uglyness */
193 return CASTPTR(void,
194 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
195 physical_address));
196 } else {
197 return CASTPTR(void,
198 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
199 physical_address));
200 }
201}
202
203/* The following #if controls the definition of the macro
204 CVMX_BUILD_WRITE64. This macro is used to build a store operation to
205 a full 64bit address. With a 64bit ABI, this can be done with a simple
206 pointer access. 32bit ABIs require more complicated assembly */
207
208/* We have a full 64bit ABI. Writing to a 64bit address can be done with
209 a simple volatile pointer */
210#define CVMX_BUILD_WRITE64(TYPE, ST) \
211static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
212{ \
213 *CASTPTR(volatile TYPE##_t, addr) = val; \
214}
215
216
217/* The following #if controls the definition of the macro
218 CVMX_BUILD_READ64. This macro is used to build a load operation from
219 a full 64bit address. With a 64bit ABI, this can be done with a simple
220 pointer access. 32bit ABIs require more complicated assembly */
221
222/* We have a full 64bit ABI. Writing to a 64bit address can be done with
223 a simple volatile pointer */
224#define CVMX_BUILD_READ64(TYPE, LT) \
225static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
226{ \
227 return *CASTPTR(volatile TYPE##_t, addr); \
228}
229
230
231/* The following defines 8 functions for writing to a 64bit address. Each
232 takes two arguments, the address and the value to write.
233 cvmx_write64_int64 cvmx_write64_uint64
234 cvmx_write64_int32 cvmx_write64_uint32
235 cvmx_write64_int16 cvmx_write64_uint16
236 cvmx_write64_int8 cvmx_write64_uint8 */
237CVMX_BUILD_WRITE64(int64, "sd");
238CVMX_BUILD_WRITE64(int32, "sw");
239CVMX_BUILD_WRITE64(int16, "sh");
240CVMX_BUILD_WRITE64(int8, "sb");
241CVMX_BUILD_WRITE64(uint64, "sd");
242CVMX_BUILD_WRITE64(uint32, "sw");
243CVMX_BUILD_WRITE64(uint16, "sh");
244CVMX_BUILD_WRITE64(uint8, "sb");
245#define cvmx_write64 cvmx_write64_uint64
246
247/* The following defines 8 functions for reading from a 64bit address. Each
248 takes the address as the only argument
249 cvmx_read64_int64 cvmx_read64_uint64
250 cvmx_read64_int32 cvmx_read64_uint32
251 cvmx_read64_int16 cvmx_read64_uint16
252 cvmx_read64_int8 cvmx_read64_uint8 */
253CVMX_BUILD_READ64(int64, "ld");
254CVMX_BUILD_READ64(int32, "lw");
255CVMX_BUILD_READ64(int16, "lh");
256CVMX_BUILD_READ64(int8, "lb");
257CVMX_BUILD_READ64(uint64, "ld");
258CVMX_BUILD_READ64(uint32, "lw");
259CVMX_BUILD_READ64(uint16, "lhu");
260CVMX_BUILD_READ64(uint8, "lbu");
261#define cvmx_read64 cvmx_read64_uint64
262
263
264static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
265{
266 cvmx_write64(csr_addr, val);
267
268 /*
269 * Perform an immediate read after every write to an RSL
270 * register to force the write to complete. It doesn't matter
271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
272 * because it is fast and harmless.
273 */
274 if ((csr_addr >> 40) == (0x800118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276}
277
278static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
279{
280 cvmx_write64(io_addr, val);
281
282}
283
284static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
285{
286 uint64_t val = cvmx_read64(csr_addr);
287 return val;
288}
289
290
291static inline void cvmx_send_single(uint64_t data)
292{
293 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
294 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
295}
296
297static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
298{
299 union {
300 uint64_t u64;
301 struct {
302 uint64_t scraddr:8;
303 uint64_t len:8;
304 uint64_t addr:48;
305 } s;
306 } addr;
307 addr.u64 = csr_addr;
308 addr.s.scraddr = scraddr >> 3;
309 addr.s.len = 1;
310 cvmx_send_single(addr.u64);
311}
312
313/* Return true if Octeon is CN38XX pass 1 */
314static inline int cvmx_octeon_is_pass1(void)
315{
316#if OCTEON_IS_COMMON_BINARY()
317 return 0; /* Pass 1 isn't supported for common binaries */
318#else
319/* Now that we know we're built for a specific model, only check CN38XX */
320#if OCTEON_IS_MODEL(OCTEON_CN38XX)
321 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
322#else
323 return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
324#endif
325#endif
326}
327
328static inline unsigned int cvmx_get_core_num(void)
329{
330 unsigned int core_num;
331 CVMX_RDHWRNV(core_num, 0);
332 return core_num;
333}
334
335/**
336 * Returns the number of bits set in the provided value.
337 * Simple wrapper for POP instruction.
338 *
339 * @val: 32 bit value to count set bits in
340 *
341 * Returns Number of bits set
342 */
343static inline uint32_t cvmx_pop(uint32_t val)
344{
345 uint32_t pop;
346 CVMX_POP(pop, val);
347 return pop;
348}
349
350/**
351 * Returns the number of bits set in the provided value.
352 * Simple wrapper for DPOP instruction.
353 *
354 * @val: 64 bit value to count set bits in
355 *
356 * Returns Number of bits set
357 */
358static inline int cvmx_dpop(uint64_t val)
359{
360 int pop;
361 CVMX_DPOP(pop, val);
362 return pop;
363}
364
365/**
366 * Provide current cycle counter as a return value
367 *
368 * Returns current cycle counter
369 */
370
371static inline uint64_t cvmx_get_cycle(void)
372{
373 uint64_t cycle;
374 CVMX_RDHWR(cycle, 31);
375 return cycle;
376}
377
378/**
379 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion
382 *
383 * Returns Global chip cycle count since chip reset.
384 */
385static inline uint64_t cvmx_get_cycle_global(void)
386{
387 if (cvmx_octeon_is_pass1())
388 return 0;
389 else
390 return cvmx_read64(CVMX_IPD_CLK_COUNT);
391}
392
393/**
394 * This macro spins on a field waiting for it to reach a value. It
395 * is common in code to need to wait for a specific field in a CSR
396 * to match a specific value. Conceptually this macro expands to:
397 *
398 * 1) read csr at "address" with a csr typedef of "type"
399 * 2) Check if ("type".s."field" "op" "value")
400 * 3) If #2 isn't true loop to #1 unless too much time has passed.
401 */
402#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
403 ( \
404{ \
405 int result; \
406 do { \
407 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
408 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
409 type c; \
410 while (1) { \
411 c.u64 = cvmx_read_csr(address); \
412 if ((c.s.field) op(value)) { \
413 result = 0; \
414 break; \
415 } else if (cvmx_get_cycle() > done) { \
416 result = -1; \
417 break; \
418 } else \
419 cvmx_wait(100); \
420 } \
421 } while (0); \
422 result; \
423})
424
425/***************************************************************************/
426
427static inline void cvmx_reset_octeon(void)
428{
429 union cvmx_ciu_soft_rst ciu_soft_rst;
430 ciu_soft_rst.u64 = 0;
431 ciu_soft_rst.s.soft_rst = 1;
432 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
433}
434
435/* Return the number of cores available in the chip */
436static inline uint32_t cvmx_octeon_num_cores(void)
437{
438 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
439 return cvmx_pop(ciu_fuse);
440}
441
442/**
443 * Read a byte of fuse data
444 * @byte_addr: address to read
445 *
446 * Returns fuse value: 0 or 1
447 */
448static uint8_t cvmx_fuse_read_byte(int byte_addr)
449{
450 union cvmx_mio_fus_rcmd read_cmd;
451
452 read_cmd.u64 = 0;
453 read_cmd.s.addr = byte_addr;
454 read_cmd.s.pend = 1;
455 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
456 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
457 && read_cmd.s.pend)
458 ;
459 return read_cmd.s.dat;
460}
461
462/**
463 * Read a single fuse bit
464 *
465 * @fuse: Fuse number (0-1024)
466 *
467 * Returns fuse value: 0 or 1
468 */
469static inline int cvmx_fuse_read(int fuse)
470{
471 return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
472}
473
474static inline int cvmx_octeon_model_CN36XX(void)
475{
476 return OCTEON_IS_MODEL(OCTEON_CN38XX)
477 && !cvmx_octeon_is_pass1()
478 && cvmx_fuse_read(264);
479}
480
481static inline int cvmx_octeon_zip_present(void)
482{
483 return octeon_has_feature(OCTEON_FEATURE_ZIP);
484}
485
486static inline int cvmx_octeon_dfa_present(void)
487{
488 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
489 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
490 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
491 return 0;
492 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
493 return 0;
494 else if (cvmx_octeon_is_pass1())
495 return 1;
496 else
497 return !cvmx_fuse_read(120);
498}
499
500static inline int cvmx_octeon_crypto_present(void)
501{
502 return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
503}
504
505#endif /* __CVMX_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
new file mode 100644
index 000000000000..04fac684069c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -0,0 +1,119 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining checks for different Octeon features.
30 */
31
32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__
34
35enum octeon_feature {
36 /*
37 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad).
39 */
40 OCTEON_FEATURE_SAAD,
41 /* Does this Octeon support the ZIP offload engine? */
42 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO,
45 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE,
47 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY,
50 /* Octeon has a LED controller for banks of external LEDs */
51 OCTEON_FEATURE_LED_CONTROLLER,
52 /* Octeon has a trace buffer */
53 OCTEON_FEATURE_TRA,
54 /* Octeon has a management port */
55 OCTEON_FEATURE_MGMT_PORT,
56 /* Octeon has a raid unit */
57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB,
60};
61
62static inline int cvmx_fuse_read(int fuse);
63
64/**
65 * Determine if the current Octeon supports a specific feature. These
66 * checks have been optimized to be fairly quick, but they should still
67 * be kept out of fast path code.
68 *
69 * @feature: Feature to check for. This should always be a constant so the
70 * compiler can remove the switch statement through optimization.
71 *
72 * Returns Non zero if the feature exists. Zero if the feature does not
73 * exist.
74 */
75static inline int octeon_has_feature(enum octeon_feature feature)
76{
77 switch (feature) {
78 case OCTEON_FEATURE_SAAD:
79 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
80
81 case OCTEON_FEATURE_ZIP:
82 if (OCTEON_IS_MODEL(OCTEON_CN30XX)
83 || OCTEON_IS_MODEL(OCTEON_CN50XX)
84 || OCTEON_IS_MODEL(OCTEON_CN52XX))
85 return 0;
86 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
87 return 1;
88 else
89 return !cvmx_fuse_read(121);
90
91 case OCTEON_FEATURE_CRYPTO:
92 return !cvmx_fuse_read(90);
93
94 case OCTEON_FEATURE_PCIE:
95 return OCTEON_IS_MODEL(OCTEON_CN56XX)
96 || OCTEON_IS_MODEL(OCTEON_CN52XX);
97
98 case OCTEON_FEATURE_KEY_MEMORY:
99 case OCTEON_FEATURE_LED_CONTROLLER:
100 return OCTEON_IS_MODEL(OCTEON_CN38XX)
101 || OCTEON_IS_MODEL(OCTEON_CN58XX)
102 || OCTEON_IS_MODEL(OCTEON_CN56XX);
103 case OCTEON_FEATURE_TRA:
104 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
105 || OCTEON_IS_MODEL(OCTEON_CN50XX));
106 case OCTEON_FEATURE_MGMT_PORT:
107 return OCTEON_IS_MODEL(OCTEON_CN56XX)
108 || OCTEON_IS_MODEL(OCTEON_CN52XX);
109 case OCTEON_FEATURE_RAID:
110 return OCTEON_IS_MODEL(OCTEON_CN56XX)
111 || OCTEON_IS_MODEL(OCTEON_CN52XX);
112 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX));
115 }
116 return 0;
117}
118
119#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
new file mode 100644
index 000000000000..cf50336eca2e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -0,0 +1,321 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__
37
38/* NOTE: These must match what is checked in common-config.mk */
39/* Defines to represent the different versions of Octeon. */
40
41/*
42 * IMPORTANT: When the default pass is updated for an Octeon Model,
43 * the corresponding change must also be made in the oct-sim script.
44 */
45
46/*
47 * The defines below should be used with the OCTEON_IS_MODEL() macro
48 * to determine what model of chip the software is running on. Models
49 * ending in 'XX' match multiple models (families), while specific
50 * models match only that model. If a pass (revision) is specified,
51 * then only that revision will be matched. Care should be taken when
52 * checking for both specific models and families that the specific
53 * models are checked for first. While these defines are similar to
54 * the processor ID, they are not intended to be used by anything
55 * other that the OCTEON_IS_MODEL framework, and the values are
56 * subject to change at anytime without notice.
57 *
58 * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
59 * macros should be used outside of this file. All other macros are
60 * for internal use only, and may change without notice.
61 */
62
63/* Flag bits in top byte */
64/* Ignores revision in model checks */
65#define OM_IGNORE_REVISION 0x01000000
66/* Check submodels */
67#define OM_CHECK_SUBMODEL 0x02000000
68/* Match all models previous than the one specified */
69#define OM_MATCH_PREVIOUS_MODELS 0x04000000
70/* Ignores the minor revison on newer parts */
71#define OM_IGNORE_MINOR_REVISION 0x08000000
72#define OM_FLAG_MASK 0xff000000
73
74/*
75 * CN5XXX models with new revision encoding
76 */
77#define OCTEON_CN58XX_PASS1_0 0x000d0300
78#define OCTEON_CN58XX_PASS1_1 0x000d0301
79#define OCTEON_CN58XX_PASS1_2 0x000d0303
80#define OCTEON_CN58XX_PASS2_0 0x000d0308
81#define OCTEON_CN58XX_PASS2_1 0x000d0309
82#define OCTEON_CN58XX_PASS2_2 0x000d030a
83#define OCTEON_CN58XX_PASS2_3 0x000d030b
84
85#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
86#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \
87 | OM_IGNORE_MINOR_REVISION)
88#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
89 | OM_IGNORE_MINOR_REVISION)
90#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
91#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
92
93#define OCTEON_CN56XX_PASS1_0 0x000d0400
94#define OCTEON_CN56XX_PASS1_1 0x000d0401
95#define OCTEON_CN56XX_PASS2_0 0x000d0408
96#define OCTEON_CN56XX_PASS2_1 0x000d0409
97
98#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
99#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \
100 | OM_IGNORE_MINOR_REVISION)
101#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
102 | OM_IGNORE_MINOR_REVISION)
103#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
104#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
105
106#define OCTEON_CN57XX OCTEON_CN56XX
107#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1
108#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2
109
110#define OCTEON_CN55XX OCTEON_CN56XX
111#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1
112#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2
113
114#define OCTEON_CN54XX OCTEON_CN56XX
115#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1
116#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2
117
118#define OCTEON_CN50XX_PASS1_0 0x000d0600
119
120#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
121#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \
122 | OM_IGNORE_MINOR_REVISION)
123#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
124
125/*
126 * NOTE: Octeon CN5000F model is not identifiable using the
127 * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
128 */
129
130#define OCTEON_CN52XX_PASS1_0 0x000d0700
131#define OCTEON_CN52XX_PASS2_0 0x000d0708
132
133#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
134#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \
135 | OM_IGNORE_MINOR_REVISION)
136#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
137 | OM_IGNORE_MINOR_REVISION)
138#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
139#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
140
141/*
142 * CN3XXX models with old revision enconding
143 */
144#define OCTEON_CN38XX_PASS1 0x000d0000
145#define OCTEON_CN38XX_PASS2 0x000d0001
146#define OCTEON_CN38XX_PASS3 0x000d0003
147#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
148
149#define OCTEON_CN36XX OCTEON_CN38XX
150#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2
151#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3
152
153/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
154#define OCTEON_CN31XX_PASS1 0x000d0100
155#define OCTEON_CN31XX_PASS1_1 0x000d0102
156#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
157
158/*
159 * This model is only used for internal checks, it is not a valid
160 * model for the OCTEON_MODEL environment variable. This matches the
161 * CN3010 and CN3005 but NOT the CN3020.
162 */
163#define OCTEON_CN30XX_PASS1 0x000d0200
164#define OCTEON_CN30XX_PASS1_1 0x000d0202
165#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
166
167#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
168#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
169#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
170#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
171 | OM_CHECK_SUBMODEL)
172
173#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
174#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
177 | OM_CHECK_SUBMODEL)
178
179#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
180#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
183 | OM_CHECK_SUBMODEL)
184
185
186
187/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
188#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
189 | OM_MATCH_PREVIOUS_MODELS \
190 | OM_IGNORE_REVISION)
191
192/* The revision byte (low byte) has two different encodings.
193 * CN3XXX:
194 *
195 * bits
196 * <7:5>: reserved (0)
197 * <4>: alternate package
198 * <3:0>: revision
199 *
200 * CN5XXX:
201 *
202 * bits
203 * <7>: reserved (0)
204 * <6>: alternate package
205 * <5:3>: major revision
206 * <2:0>: minor revision
207 *
208 */
209
210/* Masks used for the various types of model/family/revision matching */
211#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
212#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
213#define OCTEON_38XX_MODEL_MASK 0x00ffff10
214#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
215 | OCTEON_38XX_MODEL_MASK)
216
217/* CN5XXX and later use different layout of bits in the revision ID field */
218#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
219#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
220#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
221#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
222 | OCTEON_58XX_MODEL_MASK)
223#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
224 & 0x00fffff8)
225
226#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
227
228/* NOTE: This is for internal (to this file) use only. */
229static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
230 uint32_t chip_model)
231{
232 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
233
234 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
235 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
236 __OCTEON_MATCH_MASK__(chip_model, arg_model,
237 OCTEON_38XX_MODEL_MASK))
238 return 1;
239 if (((arg_model & OM_FLAG_MASK) == 0) &&
240 __OCTEON_MATCH_MASK__(chip_model, arg_model,
241 OCTEON_38XX_FAMILY_REV_MASK))
242 return 1;
243 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
244 __OCTEON_MATCH_MASK__(chip_model, arg_model,
245 OCTEON_38XX_FAMILY_MASK))
246 return 1;
247 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
248 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
249 OCTEON_38XX_MODEL_REV_MASK))
250 return 1;
251 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
252 ((chip_model & OCTEON_38XX_MODEL_MASK) <
253 (arg_model & OCTEON_38XX_MODEL_MASK)))
254 return 1;
255 } else {
256 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
257 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
258 OCTEON_58XX_MODEL_MASK))
259 return 1;
260 if (((arg_model & OM_FLAG_MASK) == 0) &&
261 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
262 OCTEON_58XX_FAMILY_REV_MASK))
263 return 1;
264 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
265 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
266 OCTEON_58XX_MODEL_MINOR_REV_MASK))
267 return 1;
268 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
269 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
270 OCTEON_58XX_FAMILY_MASK))
271 return 1;
272 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
273 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
274 OCTEON_58XX_MODEL_REV_MASK))
275 return 1;
276 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
277 ((chip_model & OCTEON_58XX_MODEL_MASK) <
278 (arg_model & OCTEON_58XX_MODEL_MASK)))
279 return 1;
280 }
281 return 0;
282}
283
284/* forward declarations */
285static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
286static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
287
288/* NOTE: This for internal use only!!!!! */
289static inline int __octeon_is_model_runtime__(uint32_t model)
290{
291 uint32_t cpuid = cvmx_get_proc_id();
292
293 /*
294 * Check for special case of mismarked 3005 samples. We only
295 * need to check if the sub model isn't being ignored.
296 */
297 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
298 if (cpuid == OCTEON_CN3010_PASS1 \
299 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
300 cpuid |= 0x10;
301 }
302 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
303}
304
305/*
306 * The OCTEON_IS_MODEL macro should be used for all Octeon model
307 * checking done in a program. This should be kept runtime if at all
308 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
309 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
310 * support is required.
311 */
312#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
313#define OCTEON_IS_COMMON_BINARY() 1
314#undef OCTEON_MODEL
315
316const char *octeon_model_get_string(uint32_t chip_id);
317const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
318
319#include "octeon-feature.h"
320
321#endif /* __OCTEON_MODEL_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
new file mode 100644
index 000000000000..edc676084cda
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -0,0 +1,248 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __ASM_OCTEON_OCTEON_H
9#define __ASM_OCTEON_OCTEON_H
10
11#include "cvmx.h"
12
13extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 uint64_t alignment,
15 uint64_t min_addr,
16 uint64_t max_addr,
17 int do_locking);
18extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
19 int do_locking);
20extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 uint64_t min_addr, uint64_t max_addr,
22 int do_locking);
23extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
24 char *name);
25extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 uint64_t max_addr, uint64_t align,
27 char *name);
28extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
29 char *name);
30extern int octeon_bootmem_free_named(char *name);
31extern void octeon_bootmem_lock(void);
32extern void octeon_bootmem_unlock(void);
33
34extern int octeon_is_simulation(void);
35extern int octeon_is_pci_host(void);
36extern int octeon_usb_is_ref_clk(void);
37extern uint64_t octeon_get_clock_rate(void);
38extern const char *octeon_board_type_string(void);
39extern const char *octeon_get_pci_interrupts(void);
40extern int octeon_get_southbridge_interrupt(void);
41extern int octeon_get_boot_coremask(void);
42extern int octeon_get_boot_num_arguments(void);
43extern const char *octeon_get_boot_argument(int arg);
44extern void octeon_hal_setup_reserved32(void);
45extern void octeon_user_io_init(void);
46struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags);
50
51extern void octeon_init_cvmcount(void);
52
53#define OCTEON_ARGV_MAX_ARGS 64
54#define OCTOEN_SERIAL_LEN 20
55
56struct octeon_boot_descriptor {
57 /* Start of block referenced by assembly code - do not change! */
58 uint32_t desc_version;
59 uint32_t desc_size;
60 uint64_t stack_top;
61 uint64_t heap_base;
62 uint64_t heap_end;
63 /* Only used by bootloader */
64 uint64_t entry_point;
65 uint64_t desc_vaddr;
66 /* End of This block referenced by assembly code - do not change! */
67 uint32_t exception_base_addr;
68 uint32_t stack_size;
69 uint32_t heap_size;
70 /* Argc count for application. */
71 uint32_t argc;
72 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
73
74#define BOOT_FLAG_INIT_CORE (1 << 0)
75#define OCTEON_BL_FLAG_DEBUG (1 << 1)
76#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
77 /* If set, use uart1 for console */
78#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
79 /* If set, use PCI console */
80#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
81 /* Call exit on break on serial port */
82#define OCTEON_BL_FLAG_BREAK (1 << 5)
83
84 uint32_t flags;
85 uint32_t core_mask;
86 /* DRAM size in megabyes. */
87 uint32_t dram_size;
88 /* physical address of free memory descriptor block. */
89 uint32_t phy_mem_desc_addr;
90 /* used to pass flags from app to debugger. */
91 uint32_t debugger_flags_base_addr;
92 /* CPU clock speed, in hz. */
93 uint32_t eclock_hz;
94 /* DRAM clock speed, in hz. */
95 uint32_t dclock_hz;
96 /* SPI4 clock in hz. */
97 uint32_t spi_clock_hz;
98 uint16_t board_type;
99 uint8_t board_rev_major;
100 uint8_t board_rev_minor;
101 uint16_t chip_type;
102 uint8_t chip_rev_major;
103 uint8_t chip_rev_minor;
104 char board_serial_number[OCTOEN_SERIAL_LEN];
105 uint8_t mac_addr_base[6];
106 uint8_t mac_addr_count;
107 uint64_t cvmx_desc_vaddr;
108};
109
110union octeon_cvmemctl {
111 uint64_t u64;
112 struct {
113 /* RO 1 = BIST fail, 0 = BIST pass */
114 uint64_t tlbbist:1;
115 /* RO 1 = BIST fail, 0 = BIST pass */
116 uint64_t l1cbist:1;
117 /* RO 1 = BIST fail, 0 = BIST pass */
118 uint64_t l1dbist:1;
119 /* RO 1 = BIST fail, 0 = BIST pass */
120 uint64_t dcmbist:1;
121 /* RO 1 = BIST fail, 0 = BIST pass */
122 uint64_t ptgbist:1;
123 /* RO 1 = BIST fail, 0 = BIST pass */
124 uint64_t wbfbist:1;
125 /* Reserved */
126 uint64_t reserved:22;
127 /* R/W If set, marked write-buffer entries time out
128 * the same as as other entries; if clear, marked
129 * write-buffer entries use the maximum timeout. */
130 uint64_t dismarkwblongto:1;
131 /* R/W If set, a merged store does not clear the
132 * write-buffer entry timeout state. */
133 uint64_t dismrgclrwbto:1;
134 /* R/W Two bits that are the MSBs of the resultant
135 * CVMSEG LM word location for an IOBDMA. The other 8
136 * bits come from the SCRADDR field of the IOBDMA. */
137 uint64_t iobdmascrmsb:2;
138 /* R/W If set, SYNCWS and SYNCS only order marked
139 * stores; if clear, SYNCWS and SYNCS only order
140 * unmarked stores. SYNCWSMARKED has no effect when
141 * DISSYNCWS is set. */
142 uint64_t syncwsmarked:1;
143 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
144 * SYNC. */
145 uint64_t dissyncws:1;
146 /* R/W If set, no stall happens on write buffer
147 * full. */
148 uint64_t diswbfst:1;
149 /* R/W If set (and SX set), supervisor-level
150 * loads/stores can use XKPHYS addresses with
151 * VA<48>==0 */
152 uint64_t xkmemenas:1;
153 /* R/W If set (and UX set), user-level loads/stores
154 * can use XKPHYS addresses with VA<48>==0 */
155 uint64_t xkmemenau:1;
156 /* R/W If set (and SX set), supervisor-level
157 * loads/stores can use XKPHYS addresses with
158 * VA<48>==1 */
159 uint64_t xkioenas:1;
160 /* R/W If set (and UX set), user-level loads/stores
161 * can use XKPHYS addresses with VA<48>==1 */
162 uint64_t xkioenau:1;
163 /* R/W If set, all stores act as SYNCW (NOMERGE must
164 * be set when this is set) RW, reset to 0. */
165 uint64_t allsyncw:1;
166 /* R/W If set, no stores merge, and all stores reach
167 * the coherent bus in order. */
168 uint64_t nomerge:1;
169 /* R/W Selects the bit in the counter used for DID
170 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
171 * 214. Actual time-out is between 1x and 2x this
172 * interval. For example, with DIDTTO=3, expiration
173 * interval is between 16K and 32K. */
174 uint64_t didtto:2;
175 /* R/W If set, the (mem) CSR clock never turns off. */
176 uint64_t csrckalwys:1;
177 /* R/W If set, mclk never turns off. */
178 uint64_t mclkalwys:1;
179 /* R/W Selects the bit in the counter used for write
180 * buffer flush time-outs (WBFLT+11) is the bit
181 * position in an internal counter used to determine
182 * expiration. The write buffer expires between 1x and
183 * 2x this interval. For example, with WBFLT = 0, a
184 * write buffer expires between 2K and 4K cycles after
185 * the write buffer entry is allocated. */
186 uint64_t wbfltime:3;
187 /* R/W If set, do not put Istream in the L2 cache. */
188 uint64_t istrnol2:1;
189 /* R/W The write buffer threshold. */
190 uint64_t wbthresh:4;
191 /* Reserved */
192 uint64_t reserved2:2;
193 /* R/W If set, CVMSEG is available for loads/stores in
194 * kernel/debug mode. */
195 uint64_t cvmsegenak:1;
196 /* R/W If set, CVMSEG is available for loads/stores in
197 * supervisor mode. */
198 uint64_t cvmsegenas:1;
199 /* R/W If set, CVMSEG is available for loads/stores in
200 * user mode. */
201 uint64_t cvmsegenau:1;
202 /* R/W Size of local memory in cache blocks, 54 (6912
203 * bytes) is max legal value. */
204 uint64_t lmemsz:6;
205 } s;
206};
207
208struct octeon_cf_data {
209 unsigned long base_region_bias;
210 unsigned int base_region; /* The chip select region used by CF */
211 int is16bit; /* 0 - 8bit, !0 - 16bit */
212 int dma_engine; /* -1 for no DMA */
213};
214
215extern void octeon_write_lcd(const char *s);
216extern void octeon_check_cpu_bist(void);
217extern int octeon_get_boot_debug_flag(void);
218extern int octeon_get_boot_uart(void);
219
220struct uart_port;
221extern unsigned int octeon_serial_in(struct uart_port *, int);
222extern void octeon_serial_out(struct uart_port *, int, int);
223
224/**
225 * Write a 32bit value to the Octeon NPI register space
226 *
227 * @address: Address to write to
228 * @val: Value to write
229 */
230static inline void octeon_npi_write32(uint64_t address, uint32_t val)
231{
232 cvmx_write64_uint32(address ^ 4, val);
233 cvmx_read64_uint32(address ^ 4);
234}
235
236
237/**
238 * Read a 32bit value from the Octeon NPI register space
239 *
240 * @address: Address to read
241 * Returns The result
242 */
243static inline uint32_t octeon_npi_read32(uint64_t address)
244{
245 return cvmx_read64_uint32(address ^ 4);
246}
247
248#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 18ee58e39445..0f926aa0cb47 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -118,6 +118,60 @@ union mips_watch_reg_state {
118 struct mips3264_watch_reg_state mips3264; 118 struct mips3264_watch_reg_state mips3264;
119}; 119};
120 120
121#ifdef CONFIG_CPU_CAVIUM_OCTEON
122
123struct octeon_cop2_state {
124 /* DMFC2 rt, 0x0201 */
125 unsigned long cop2_crc_iv;
126 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
127 unsigned long cop2_crc_length;
128 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
129 unsigned long cop2_crc_poly;
130 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
131 unsigned long cop2_llm_dat[2];
132 /* DMFC2 rt, 0x0084 */
133 unsigned long cop2_3des_iv;
134 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
135 unsigned long cop2_3des_key[3];
136 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
137 unsigned long cop2_3des_result;
138 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
139 unsigned long cop2_aes_inp0;
140 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
141 unsigned long cop2_aes_iv[2];
142 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
143 * rt, 0x0107 */
144 unsigned long cop2_aes_key[4];
145 /* DMFC2 rt, 0x0110 */
146 unsigned long cop2_aes_keylen;
147 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
148 unsigned long cop2_aes_result[2];
149 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
150 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
151 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
152 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
153 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
154 unsigned long cop2_hsh_datw[15];
155 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
156 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
157 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
158 unsigned long cop2_hsh_ivw[8];
159 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
160 unsigned long cop2_gfm_mult[2];
161 /* DMFC2 rt, 0x025E - Pass2 */
162 unsigned long cop2_gfm_poly;
163 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
164 unsigned long cop2_gfm_result[2];
165};
166#define INIT_OCTEON_COP2 {0,}
167
168struct octeon_cvmseg_state {
169 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
170 [cpu_dcache_line_size() / sizeof(unsigned long)];
171};
172
173#endif
174
121typedef struct { 175typedef struct {
122 unsigned long seg; 176 unsigned long seg;
123} mm_segment_t; 177} mm_segment_t;
@@ -160,6 +214,10 @@ struct thread_struct {
160 unsigned long trap_no; 214 unsigned long trap_no;
161 unsigned long irix_trampoline; /* Wheee... */ 215 unsigned long irix_trampoline; /* Wheee... */
162 unsigned long irix_oldctx; 216 unsigned long irix_oldctx;
217#ifdef CONFIG_CPU_CAVIUM_OCTEON
218 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
219 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
220#endif
163 struct mips_abi *abi; 221 struct mips_abi *abi;
164}; 222};
165 223
@@ -171,6 +229,13 @@ struct thread_struct {
171#define FPAFF_INIT 229#define FPAFF_INIT
172#endif /* CONFIG_MIPS_MT_FPAFF */ 230#endif /* CONFIG_MIPS_MT_FPAFF */
173 231
232#ifdef CONFIG_CPU_CAVIUM_OCTEON
233#define OCTEON_INIT \
234 .cp2 = INIT_OCTEON_COP2,
235#else
236#define OCTEON_INIT
237#endif /* CONFIG_CPU_CAVIUM_OCTEON */
238
174#define INIT_THREAD { \ 239#define INIT_THREAD { \
175 /* \ 240 /* \
176 * Saved main processor registers \ 241 * Saved main processor registers \
@@ -221,6 +286,10 @@ struct thread_struct {
221 .trap_no = 0, \ 286 .trap_no = 0, \
222 .irix_trampoline = 0, \ 287 .irix_trampoline = 0, \
223 .irix_oldctx = 0, \ 288 .irix_oldctx = 0, \
289 /* \
290 * Cavium Octeon specifics (null if not Octeon) \
291 */ \
292 OCTEON_INIT \
224} 293}
225 294
226struct task_struct; 295struct task_struct;
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index c2c8bac43307..1f30d16d4669 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -48,6 +48,10 @@ struct pt_regs {
48#ifdef CONFIG_MIPS_MT_SMTC 48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus; 49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */ 50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
54#endif
51} __attribute__ ((aligned (8))); 55} __attribute__ ((aligned (8)));
52 56
53/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 86557b5d1b3f..40e5ef1d4d26 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
37 37
38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
39#define SMP_CALL_FUNCTION 0x2 39#define SMP_CALL_FUNCTION 0x2
40/* Octeon - Tell another core to flush its icache */
41#define SMP_ICACHE_FLUSH 0x4
42
40 43
41extern void asmlinkage smp_bootstrap(void); 44extern void asmlinkage smp_bootstrap(void);
42 45
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4c37c4e5f72e..db0fa7b5aeaf 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -194,6 +194,19 @@
194 LONG_S $31, PT_R31(sp) 194 LONG_S $31, PT_R31(sp)
195 ori $28, sp, _THREAD_MASK 195 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 196 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON
198 .set mips64
199 pref 0, 0($28) /* Prefetch the current pointer */
200 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
201 /* The Octeon multiplier state is affected by general multiply
202 instructions. It must be saved before and kernel code might
203 corrupt it */
204 jal octeon_mult_save
205 LONG_L v1, 0($28) /* Load the current pointer */
206 /* Restore $31(ra) that was changed by the jal */
207 LONG_L ra, PT_R31(sp)
208 pref 0, 0(v1) /* Prefetch the current thread */
209#endif
197 .set pop 210 .set pop
198 .endm 211 .endm
199 212
@@ -324,6 +337,10 @@
324 DVPE 5 # dvpe a1 337 DVPE 5 # dvpe a1
325 jal mips_ihb 338 jal mips_ihb
326#endif /* CONFIG_MIPS_MT_SMTC */ 339#endif /* CONFIG_MIPS_MT_SMTC */
340#ifdef CONFIG_CPU_CAVIUM_OCTEON
341 /* Restore the Octeon multiplier state */
342 jal octeon_mult_restore
343#endif
327 mfc0 a0, CP0_STATUS 344 mfc0 a0, CP0_STATUS
328 ori a0, STATMASK 345 ori a0, STATMASK
329 xori a0, STATMASK 346 xori a0, STATMASK
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 9601ea950542..38a30d2ee959 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,27 +50,35 @@ extern int (*perf_irq)(void);
50/* 50/*
51 * Initialize the calling CPU's compare interrupt as clockevent device 51 * Initialize the calling CPU's compare interrupt as clockevent device
52 */ 52 */
53#ifdef CONFIG_CEVT_R4K 53#ifdef CONFIG_CEVT_R4K_LIB
54extern int mips_clockevent_init(void);
55extern unsigned int __weak get_c0_compare_int(void); 54extern unsigned int __weak get_c0_compare_int(void);
56#else 55extern int r4k_clockevent_init(void);
56#endif
57
57static inline int mips_clockevent_init(void) 58static inline int mips_clockevent_init(void)
58{ 59{
60#ifdef CONFIG_CEVT_R4K
61 return r4k_clockevent_init();
62#else
59 return -ENXIO; 63 return -ENXIO;
60}
61#endif 64#endif
65}
62 66
63/* 67/*
64 * Initialize the count register as a clocksource 68 * Initialize the count register as a clocksource
65 */ 69 */
66#ifdef CONFIG_CSRC_R4K 70#ifdef CONFIG_CSRC_R4K_LIB
67extern int init_mips_clocksource(void); 71extern int init_r4k_clocksource(void);
68#else 72#endif
73
69static inline int init_mips_clocksource(void) 74static inline int init_mips_clocksource(void)
70{ 75{
76#ifdef CONFIG_CSRC_R4K
77 return init_r4k_clocksource();
78#else
71 return 0; 79 return 0;
72}
73#endif 80#endif
81}
74 82
75extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); 83extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
76extern void clockevent_set_clock(struct clock_event_device *cd, 84extern void clockevent_set_clock(struct clock_event_device *cd,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 12:57:38 -0500