MIPS: Respect the ISA level in FCSR handling

Define the central place the default FCSR value is set from, initialised
in `cpu_probe'.  Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.

Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused.  For ptrace(2) it's just sanity.

[ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 13 insertions, 5 deletions

diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index c3f4f2d2e108..e7dc785a91ca 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -49,6 +49,8 @@ struct cpuinfo_mips {
         unsigned int            udelay_val;
         unsigned int            processor_id;
         unsigned int            fpu_id;
+        unsigned int            fpu_csr31;
+        unsigned int            fpu_msk31;
         unsigned int            msa_id;
         unsigned int            cputype;
         int                     isa_level;
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 535f196ffe02..612cf519bd88 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -11,6 +11,9 @@
 #include <linux/fs.h>
 #include <uapi/linux/elf.h>
 
+#include <asm/cpu-info.h>
+#include <asm/current.h>
+
 /* ELF header e_flags defines. */
 /* MIPS architecture level. */
 #define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
@@ -297,6 +300,8 @@ do {									\
         mips_set_personality_fp(state);                                 \
                                                                         \
         current->thread.abi = &mips_abi;                                \
+                                                                        \
+        current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
 } while (0)
 
 #endif /* CONFIG_32BIT */
@@ -356,6 +361,8 @@ do {									\
         else                                                            \
                 current->thread.abi = &mips_abi;                        \
                                                                         \
+        current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
+                                                                        \
         p = personality(current->personality);                          \
         if (p != PER_LINUX32 && p != PER_LINUX)                         \
                 set_personality(PER_LINUX);                             \
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index dd083e999b08..83d50d563a0f 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -30,7 +30,7 @@
 struct sigcontext;
 struct sigcontext32;
 
-extern void _init_fpu(void);
+extern void _init_fpu(unsigned int);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
 
@@ -182,6 +182,7 @@ static inline void lose_fpu(int save)
 
 static inline int init_fpu(void)
 {
+        unsigned int fcr31 = current->thread.fpu.fcr31;
         int ret = 0;
 
         if (cpu_has_fpu) {
@@ -192,7 +193,7 @@ static inline int init_fpu(void)
                         return ret;
 
                 if (!cpu_has_fre) {
-                        _init_fpu();
+                        _init_fpu(fcr31);
 
                         return 0;
                 }
@@ -206,7 +207,7 @@ static inline int init_fpu(void)
                 config5 = clear_c0_config5(MIPS_CONF5_FRE);
                 enable_fpu_hazard();
 
-                _init_fpu();
+                _init_fpu(fcr31);
 
                 /* Restore FRE */
                 write_c0_config5(config5);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index bfcc5c64b7b0..2f021cdfba4f 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -88,8 +88,6 @@ static inline void fpu_emulator_init_fpu(void)
         struct task_struct *t = current;
         int i;
 
-        t->thread.fpu.fcr31 = 0;
-
         for (i = 0; i < 32; i++)
                 set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
 }