MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

22 files changed, 939 insertions, 939 deletions

diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 2367b56dcdef..66814f8ba8e8 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -88,8 +88,8 @@
 
 #define SWIN_SIZE_BITS          24
 #define SWIN_SIZE               (UINT64_CAST 1 << 24)
-#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
-#define SWIN_WIDGET_MASK        0xF
+#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
+#define SWIN_WIDGET_MASK        0xF
 
 /*
  * Convert smallwindow address to xtalk address.
@@ -97,8 +97,8 @@
  * 'addr' can be physical or virtual address, but will be converted
  * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
  */
-#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
-#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
+#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
 /*
  * Verify if addr belongs to small window address on node with "nasid"
  *
@@ -108,7 +108,7 @@
  *
  *
  */
-#define NODE_SWIN_ADDR(nasid, addr)     \
+#define NODE_SWIN_ADDR(nasid, addr)     \
                 (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
                  ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
                  ))
@@ -150,7 +150,7 @@
 
 #endif
 
-#define HUB_REGISTER_WIDGET     1
+#define HUB_REGISTER_WIDGET     1
 #define IALIAS_BASE             NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
 #define IALIAS_SIZE             0x800000        /* 8 Megabytes */
 #define IS_IALIAS(_a)           (((_a) >= IALIAS_BASE) &&               \
@@ -174,16 +174,16 @@
  *   WARNING: They won't work in assembler.
  *
  *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
- *                  entry corresponding to a physical (Cac or Uncac) address.
+ *                  entry corresponding to a physical (Cac or Uncac) address.
  *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
  *   BDPRT_ENTRY    returns the address of the double-word protection entry
- *                  corresponding to the page containing the physical address.
+ *                  corresponding to the page containing the physical address.
  *   BDPRT_ENTRY_S  Stores the value into the protection entry.
  *   BDPRT_ENTRY_L  Load the value from the protection entry.
  *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
- *                  double-word at a specified physical address.
+ *                  double-word at a specified physical address.
  *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
- *                  quad-word at a specified physical address.
+ *                  quad-word at a specified physical address.
  */
 #define NODE_BDOOR_BASE(_n)     (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
 
@@ -226,11 +226,11 @@
 #define BDADDR_IS_DIR(_ba)      ((UINT64_CAST  (_ba) & 0x200) != 0)
 #define BDADDR_IS_PRT(_ba)      ((UINT64_CAST  (_ba) & 0x200) == 0)
 
-#define BDDIR_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK            | \
+#define BDDIR_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK            | \
                                  (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
                                  (UINT64_CAST(_ba) & 0x1f << 4) << 3)
 
-#define BDPRT_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
+#define BDPRT_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
                                  (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
 
 #define BDECC_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
@@ -251,23 +251,23 @@
 /*
  * WARNING:
  *      When certain Hub chip workaround are defined, it's not sufficient
- *      to dereference the *_HUB_ADDR() macros.  You should instead use
+ *      to dereference the *_HUB_ADDR() macros.  You should instead use
  *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
  *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *      They're always safe.
  */
 #define LOCAL_HUB_ADDR(_x)      (HUBREG_CAST (IALIAS_BASE + (_x)))
-#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
                                               0x800000 + (_x)))
 #ifdef CONFIG_SGI_IP27
-#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
                                               0x800000 + (_x)))
 #endif /* CONFIG_SGI_IP27 */
 
 #ifndef __ASSEMBLY__
 
 #define HUB_L(_a)                       *(_a)
-#define HUB_S(_a, _d)                   *(_a) = (_d)
+#define HUB_S(_a, _d)                   *(_a) = (_d)
 
 #define LOCAL_HUB_L(_r)                 HUB_L(LOCAL_HUB_ADDR(_r))
 #define LOCAL_HUB_S(_r, _d)             HUB_S(LOCAL_HUB_ADDR(_r), (_d))
@@ -330,14 +330,14 @@
 
 #define KLI_LAUNCH              0               /* Dir. entries */
 #define KLI_KLCONFIG            1
-#define KLI_NMI                 2
+#define KLI_NMI                 2
 #define KLI_GDA                 3
 #define KLI_FREEMEM             4
-#define KLI_SYMMON_STK          5
+#define KLI_SYMMON_STK          5
 #define KLI_PI_ERROR            6
 #define KLI_KERN_VARS           7
-#define KLI_KERN_XP             8
-#define KLI_KERN_PARTID         9
+#define KLI_KERN_XP             8
+#define KLI_KERN_PARTID         9
 
 #ifndef __ASSEMBLY__
 
@@ -350,8 +350,8 @@
 #define KLD_SYMMON_STK(nasid)   (KLD_BASE(nasid) + KLI_SYMMON_STK)
 #define KLD_FREEMEM(nasid)      (KLD_BASE(nasid) + KLI_FREEMEM)
 #define KLD_KERN_VARS(nasid)    (KLD_BASE(nasid) + KLI_KERN_VARS)
-#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
-#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
+#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
+#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
 
 #define LAUNCH_OFFSET(nasid, slice)                                     \
         (KLD_LAUNCH(nasid)->offset +                                    \
@@ -365,7 +365,7 @@
          KLD_NMI(nasid)->stride * (slice))
 #define NMI_ADDR(nasid, slice)                                          \
         TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice))
-#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
+#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
 
 #define KLCONFIG_OFFSET(nasid)  KLD_KLCONFIG(nasid)->offset
 #define KLCONFIG_ADDR(nasid)                                            \
@@ -390,8 +390,8 @@
 /* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
  * relocatable program
  */
-#define UNIX_DEBUG_LOADADDR     0x300000
-#define SYMMON_LOADADDR(nasid)                                          \
+#define UNIX_DEBUG_LOADADDR     0x300000
+#define SYMMON_LOADADDR(nasid)                                          \
         TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
 
 #define FREEMEM_OFFSET(nasid)   KLD_FREEMEM(nasid)->offset
@@ -420,8 +420,8 @@
 #define KERN_VARS_ADDR(nasid)   KLD_KERN_VARS(nasid)->pointer
 #define KERN_VARS_SIZE(nasid)   KLD_KERN_VARS(nasid)->size
 
-#define KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
-#define KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
+#define KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
+#define KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
 
 #define GPDA_ADDR(nasid)        TO_NODE_CAC(nasid, GPDA_OFFSET)
 
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index dc81114d4742..e33d09293019 100644
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -25,21 +25,21 @@
  */
 
 #if defined(CONFIG_SGI_IP27)
-#define HUB_NIC_ADDR(_cpuid)                                               \
-        REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
+#define HUB_NIC_ADDR(_cpuid)                                               \
+        REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
                 MD_MLAN_CTL)
 #endif
 
-#define SET_HUB_NIC(_my_cpuid, _val)                                       \
+#define SET_HUB_NIC(_my_cpuid, _val)                                       \
         (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
 
-#define SET_MY_HUB_NIC(_v)                                                 \
+#define SET_MY_HUB_NIC(_v)                                                 \
         SET_HUB_NIC(cpuid(), (_v))
 
-#define GET_HUB_NIC(_my_cpuid)                                             \
+#define GET_HUB_NIC(_my_cpuid)                                             \
         (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
 
-#define GET_MY_HUB_NIC()                                                   \
+#define GET_MY_HUB_NIC()                                                   \
         GET_HUB_NIC(cpuid())
 
 #endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
index bd75945e10ff..471e6870d876 100644
--- a/arch/mips/include/asm/sn/arch.h
+++ b/arch/mips/include/asm/sn/arch.h
@@ -28,14 +28,14 @@ typedef u64	hubreg_t;
 #define INVALID_CNODEID         (cnodeid_t)-1
 #define INVALID_PNODEID         (pnodeid_t)-1
 #define INVALID_MODULE          (moduleid_t)-1
-#define INVALID_PARTID          (partid_t)-1
+#define INVALID_PARTID          (partid_t)-1
 
 extern nasid_t get_nasid(void);
 extern cnodeid_t get_cpu_cnode(cpuid_t);
 extern int get_cpu_slice(cpuid_t);
 
 /*
- * NO ONE should access these arrays directly.  The only reason we refer to
+ * NO ONE should access these arrays directly.  The only reason we refer to
  * them here is to avoid the procedure call that would be required in the
  * macros below.  (Really want private data members here :-)
  */
@@ -44,12 +44,12 @@ extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
 
 /*
  * These macros are used by various parts of the kernel to convert
- * between the three different kinds of node numbering.   At least some
+ * between the three different kinds of node numbering.   At least some
  * of them may change to procedure calls in the future, but the macros
  * will continue to work.  Don't use the arrays above directly.
  */
 
-#define NASID_TO_REGION(nnode)          \
+#define NASID_TO_REGION(nnode)          \
     ((nnode) >> \
      (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
 
diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h
index b3e3606723b7..bbb83257c8e2 100644
--- a/arch/mips/include/asm/sn/fru.h
+++ b/arch/mips/include/asm/sn/fru.h
@@ -21,24 +21,24 @@ typedef struct kf_mem_s {
                                      * is this necessary ?
                                      */
         confidence_t km_dimm[MAX_DIMMS];
-                                    /* confidence level that dimm[i] is bad
+                                    /* confidence level that dimm[i] is bad
                                      *I think this is the right number
                                      */
 
 } kf_mem_t;
 
 typedef struct kf_cpu_s {
-        confidence_t    kc_confidence; /* confidence level that cpu is bad */
-        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
-        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
-        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
         confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
 } kf_cpu_t;
 
 typedef struct kf_pci_bus_s {
         confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
         confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
-                                        /* confidence level that the pci dev is bad */
+                                        /* confidence level that the pci dev is bad */
 } kf_pci_bus_t;
 
 #endif /* __ASM_SN_FRU_H */
diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h
index 9cb6ff770915..85fa1b5f639d 100644
--- a/arch/mips/include/asm/sn/gda.h
+++ b/arch/mips/include/asm/sn/gda.h
@@ -8,7 +8,7 @@
  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  *
  * gda.h -- Contains the data structure for the global data area,
- *      The GDA contains information communicated between the
+ *      The GDA contains information communicated between the
  *      PROM, SYMMON, and the kernel.
  */
 #ifndef _ASM_SN_GDA_H
@@ -23,8 +23,8 @@
  *
  * Version #    | Change
  * -------------+-------------------------------------------------------
- *      1       | Initial SN0 version
- *      2       | Prom sets g_partid field to the partition number. 0 IS
+ *      1       | Initial SN0 version
+ *      2       | Prom sets g_partid field to the partition number. 0 IS
  *              | a valid partition #.
  */
 
@@ -60,7 +60,7 @@ typedef struct gda {
                                 /* Pointer to a mask of nodes with copies
                                  * of the kernel. */
         char    g_padding[56];  /* pad out to 128 bytes */
-        nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
+        nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
                                                   * indexed by cnodeid.
                                                   */
 } gda_t;
@@ -74,7 +74,7 @@ typedef struct gda {
  *              revisions assume GDA is NOT set up, and read partition
  *              information from the board info.
  */
-#define PART_GDA_VERSION        2
+#define PART_GDA_VERSION        2
 
 /*
  * The following requests can be sent to the PROM during startup.
@@ -83,17 +83,17 @@ typedef struct gda {
 #define PROMOP_MAGIC            0x0ead0000
 #define PROMOP_MAGIC_MASK       0x0fff0000
 
-#define PROMOP_BIST_SHIFT       11
-#define PROMOP_BIST_MASK        (0x3 << 11)
+#define PROMOP_BIST_SHIFT       11
+#define PROMOP_BIST_MASK        (0x3 << 11)
 
 #define PROMOP_REG              PI_ERR_STACK_ADDR_A
 
 #define PROMOP_INVALID          (PROMOP_MAGIC | 0x00)
-#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
-#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
-#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
-#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
-#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
 
 #define PROMOP_CMD_MASK         0x00f0
 #define PROMOP_OPTIONS_MASK     0xfff0
diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
index 6718b644b970..fc1348193957 100644
--- a/arch/mips/include/asm/sn/intr.h
+++ b/arch/mips/include/asm/sn/intr.h
@@ -14,8 +14,8 @@
 #define INT_PEND0_BASELVL       0
 #define INT_PEND1_BASELVL       64
 
-#define N_INTPENDJUNK_BITS      8
-#define INTPENDJUNK_CLRBIT      0x80
+#define N_INTPENDJUNK_BITS      8
+#define INTPENDJUNK_CLRBIT      0x80
 
 /*
  * Macros to manipulate the interrupt register on the calling hub chip.
@@ -32,7 +32,7 @@
  * We do an uncached load of the int_pend0 register to ensure this.
  */
 
-#define LOCAL_HUB_CLR_INTR(level)                               \
+#define LOCAL_HUB_CLR_INTR(level)                               \
 do {                                                            \
         LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
         LOCAL_HUB_L(PI_INT_PEND0);                              \
@@ -40,7 +40,7 @@ do {								\
 
 #define REMOTE_HUB_CLR_INTR(hub, level)                         \
 do {                                                            \
-        nasid_t  __hub = (hub);                                 \
+        nasid_t  __hub = (hub);                                 \
                                                                 \
         REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
         REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
@@ -102,8 +102,8 @@ do {								\
 #define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
 #define LLP_PFAIL_INTR_B        42
 
-#define TLB_INTR_A              43      /* used for tlb flush random */
-#define TLB_INTR_B              44
+#define TLB_INTR_A              43      /* used for tlb flush random */
+#define TLB_INTR_B              44
 
 #define IP27_INTR_0             45      /* Reserved for PROM use */
 #define IP27_INTR_1             46      /* do not use in Kernel */
@@ -116,8 +116,8 @@ do {								\
 
 #define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
                                         /* Bridge Errors */
-#define DEBUG_INTR_A            54
-#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define DEBUG_INTR_A            54
+#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
 #define IO_ERROR_INTR           57      /* Setup by PROM */
 #define CLK_ERR_INTR            58
 #define COR_ERR_INTR_A          59
diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
index 24c6775fbb0f..d5174d04538c 100644
--- a/arch/mips/include/asm/sn/io.h
+++ b/arch/mips/include/asm/sn/io.h
@@ -31,7 +31,7 @@
 #define HUB_PIO_MAP_TO_MEM      0
 #define HUB_PIO_MAP_TO_IO       1
 
-#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
+#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
 
 #define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
         REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
@@ -52,7 +52,7 @@
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
-#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
                         (_x) : \
                         (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
index 099677774d71..e33f0363235b 100644
--- a/arch/mips/include/asm/sn/ioc3.h
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -62,8 +62,8 @@ struct ioc3_sioregs {
 
         volatile u8             fill3[0x170 - 0x169 - 1];
 
-        struct ioc3_uartregs    uartb;  /* 0x20170  */
-        struct ioc3_uartregs    uarta;  /* 0x20178  */
+        struct ioc3_uartregs    uartb;  /* 0x20170  */
+        struct ioc3_uartregs    uarta;  /* 0x20178  */
 };
 
 /* Register layout of IOC3 in configuration space.  */
@@ -106,7 +106,7 @@ struct ioc3 {
         volatile u32    ppbr_l_b;       /* 0x00094  */
         volatile u32    ppcr_b;         /* 0x00098  */
 
-        /* Keyboard and Mouse Registers  */
+        /* Keyboard and Mouse Registers  */
         volatile u32    km_csr;         /* 0x0009c  */
         volatile u32    k_rd;           /* 0x000a0  */
         volatile u32    m_rd;           /* 0x000a4  */
@@ -208,7 +208,7 @@ struct ioc3_erxbuf {
 /*
  * Ethernet TX Descriptor
  */
-#define ETXD_DATALEN    104
+#define ETXD_DATALEN    104
 struct ioc3_etxd {
         u32     cmd;                            /* command field */
         u32     bufcnt;                         /* buffer counts field */
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index fe02900b930d..467c313d5767 100644
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 1999, 2000 by Ralf Baechle
  */
-#ifndef _ASM_SN_KLCONFIG_H
-#define _ASM_SN_KLCONFIG_H
+#ifndef _ASM_SN_KLCONFIG_H
+#define _ASM_SN_KLCONFIG_H
 
 /*
  * The KLCONFIG structures store info about the various BOARDs found
@@ -20,11 +20,11 @@
 /*
  * WARNING:
  *      Certain assembly language routines (notably xxxxx.s) in the IP27PROM
- *      will depend on the format of the data structures in this file.  In
- *      most cases, rearranging the fields can seriously break things.
- *      Adding fields in the beginning or middle can also break things.
- *      Add fields if necessary, to the end of a struct in such a way
- *      that offsets of existing fields do not change.
+ *      will depend on the format of the data structures in this file.  In
+ *      most cases, rearranging the fields can seriously break things.
+ *      Adding fields in the beginning or middle can also break things.
+ *      Add fields if necessary, to the end of a struct in such a way
+ *      that offsets of existing fields do not change.
  */
 
 #include <linux/types.h>
@@ -35,7 +35,7 @@
 #include <asm/sn/sn0/addrs.h>
 //#include <sys/SN/router.h>
 // XXX Stolen from <sys/SN/router.h>:
-#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
 #include <asm/sn/fru.h>
 //#include <sys/graph.h>
 //#include <sys/xtalk/xbow.h>
@@ -63,14 +63,14 @@
 
 typedef u64  nic_t;
 
-#define KLCFGINFO_MAGIC 0xbeedbabe
+#define KLCFGINFO_MAGIC 0xbeedbabe
 
 typedef s32 klconf_off_t;
 
 /*
  * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
  */
-#define MAX_MODULE_ID           255
+#define MAX_MODULE_ID           255
 #define SIZE_PAD                4096 /* 4k padding for structures */
 /*
  * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
@@ -86,25 +86,25 @@ typedef s32 klconf_off_t;
 /* All bits in this field are currently used. Try the pad fields if
    you need more flag bits */
 
-#define ENABLE_BOARD            0x01
-#define FAILED_BOARD            0x02
-#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
+#define ENABLE_BOARD            0x01
+#define FAILED_BOARD            0x02
+#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
                                            are discovered twice. Use one of them */
 #define VISITED_BOARD           0x08    /* Used for compact hub numbering. */
-#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
+#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
 #define GLOBAL_MASTER_IO6       0x20
-#define THIRD_NIC_PRESENT       0x40    /* for future use */
-#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
+#define THIRD_NIC_PRESENT       0x40    /* for future use */
+#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
 
 /* klinfo->flags fields */
 
-#define KLINFO_ENABLE           0x01    /* This component is enabled */
-#define KLINFO_FAILED           0x02    /* This component failed */
-#define KLINFO_DEVICE           0x04    /* This component is a device */
-#define KLINFO_VISITED          0x08    /* This component has been visited */
-#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
-#define KLINFO_INSTALL          0x20    /* Install a driver */
-#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
+#define KLINFO_ENABLE           0x01    /* This component is enabled */
+#define KLINFO_FAILED           0x02    /* This component failed */
+#define KLINFO_DEVICE           0x04    /* This component is a device */
+#define KLINFO_VISITED          0x08    /* This component has been visited */
+#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
+#define KLINFO_INSTALL          0x20    /* Install a driver */
+#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
 #define IS_CONSOLE_IOC3(i)      ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
 
 #define GB2             0x80000000
@@ -116,30 +116,30 @@ typedef s32 klconf_off_t;
    is used in the code to allocate various areas.
 */
 
-#define BOARD_STRUCT            0
-#define COMPONENT_STRUCT        1
-#define ERRINFO_STRUCT          2
-#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
-#define DEVICE_STRUCT           3
+#define BOARD_STRUCT            0
+#define COMPONENT_STRUCT        1
+#define ERRINFO_STRUCT          2
+#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT           3
 
 
 typedef struct console_s {
-        unsigned long   uart_base;
-        unsigned long   config_base;
-        unsigned long   memory_base;
+        unsigned long   uart_base;
+        unsigned long   config_base;
+        unsigned long   memory_base;
         short           baud;
         short           flag;
         int             type;
         nasid_t         nasid;
         char            wid;
-        char            npci;
+        char            npci;
         nic_t           baseio_nic;
 } console_t;
 
 typedef struct klc_malloc_hdr {
-        klconf_off_t km_base;
-        klconf_off_t km_limit;
-        klconf_off_t km_current;
+        klconf_off_t km_base;
+        klconf_off_t km_limit;
+        klconf_off_t km_current;
 } klc_malloc_hdr_t;
 
 /* Functions/macros needed to use this structure */
@@ -148,7 +148,7 @@ typedef struct kl_config_hdr {
         u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
         u32             ch_version;    /* structure version number */
         klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
-        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
+        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
         klconf_off_t    ch_board_info;  /* the link list of boards */
         console_t       ch_cons_info;   /* address info of the console */
         klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
@@ -157,27 +157,27 @@ typedef struct kl_config_hdr {
 } kl_config_hdr_t;
 
 
-#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
 #define KL_CONFIG_INFO_OFFSET(_nasid)                                   \
-        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+        (KL_CONFIG_HDR(_nasid)->ch_board_info)
 #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                         \
-        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
 
-#define KL_CONFIG_INFO(_nasid)                                          \
-        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
+#define KL_CONFIG_INFO(_nasid)                                          \
+        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
          NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
          0)
 #define KL_CONFIG_MAGIC(_nasid)         (KL_CONFIG_HDR(_nasid)->ch_magic)
 
 #define KL_CONFIG_CHECK_MAGIC(_nasid)                                   \
-        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
 
 #define KL_CONFIG_HDR_INIT_MAGIC(_nasid)        \
-                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
 
 /* --- New Macros for the changed kl_config_hdr_t structure --- */
 
-#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
                         ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
 
 #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
@@ -190,29 +190,29 @@ typedef struct kl_config_hdr {
 /* ------------------------------------------------------------- */
 
 #define KL_CONFIG_INFO_START(_nasid)    \
-        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
 
 #define KL_CONFIG_BOARD_NASID(_brd)     ((_brd)->brd_nasid)
 #define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)    ((_brd)->brd_next = (_off))
 
-#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
+#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
 
-#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
-#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
 
-#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
-#define XBOW_PORT_NASID(_xbowp, _link)  \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link)  \
+               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
 
-#define XBOW_PORT_IO     0x1
-#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_IO     0x1
+#define XBOW_PORT_HUB    0x2
 #define XBOW_PORT_ENABLE 0x4
 
-#define SN0_PORT_FENCE_SHFT     0
-#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
+#define SN0_PORT_FENCE_SHFT     0
+#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
 
 /*
  * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
@@ -242,28 +242,28 @@ typedef struct kl_config_hdr {
  *
  KLCONFIG
 
- +------------+      +------------+      +------------+      +------------+
- |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
- +------------+      +------------+      +------------+      +------------+
+ +------------+      +------------+      +------------+      +------------+
+ |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+  |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+      +------------+      +------------+      +------------+
 
 
  +------------+
  | board info |
- +------------+       +--------------------------------+
+ +------------+       +--------------------------------+
  | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
- +------------+       +--------------------------------+
+ +------------+       +--------------------------------+
  | compt 2    |--+
- +------------+  |    +--------------------------------+
- |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
- +------------+       +--------------------------------+
+ +------------+  |    +--------------------------------+
+ |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+       +--------------------------------+
  | errinfo    |--+
- +------------+  |    +--------------------------------+
-                 +--->|r/l brd errinfo,compt err flags |
-                      +--------------------------------+
+ +------------+  |    +--------------------------------+
+                 +--->|r/l brd errinfo,compt err flags |
+                      +--------------------------------+
 
  *
  * Each BOARD consists of COMPONENTs and the BOARD structure has
@@ -311,7 +311,7 @@ typedef struct kl_config_hdr {
  */
 #define KL_CPU_R4000            0x1     /* Standard R4000 */
 #define KL_CPU_TFP              0x2     /* TFP processor */
-#define KL_CPU_R10000           0x3     /* R10000 (T5) */
+#define KL_CPU_R10000           0x3     /* R10000 (T5) */
 #define KL_CPU_NONE             (-1)    /* no cpu present in slot */
 
 /*
@@ -320,13 +320,13 @@ typedef struct kl_config_hdr {
 
 #define KLCLASS_MASK    0xf0
 #define KLCLASS_NONE    0x00
-#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
 #define KLCLASS_CPU     KLCLASS_NODE
-#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
+#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
                                             and the non-graphics widget boards */
-#define KLCLASS_ROUTER  0x30             /* Router board */
-#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
-                                            so that we can record error info */
+#define KLCLASS_ROUTER  0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
+                                            so that we can record error info */
 #define KLCLASS_GFX     0x50            /* graphics boards */
 
 #define KLCLASS_PSEUDO_GFX      0x60    /* HDTV type cards that use a gfx
@@ -336,7 +336,7 @@ typedef struct kl_config_hdr {
 #define KLCLASS_MAX     7               /* Bump this if a new CLASS is added */
 #define KLTYPE_MAX      10              /* Bump this if a new CLASS is added */
 
-#define KLCLASS_UNKNOWN 0xf0
+#define KLCLASS_UNKNOWN 0xf0
 
 #define KLCLASS(_x) ((_x) & KLCLASS_MASK)
 
@@ -353,36 +353,36 @@ typedef struct kl_config_hdr {
 
 #define KLTYPE_WEIRDIO  (KLCLASS_IO  | 0x0)
 #define KLTYPE_BASEIO   (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
-#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
 #define KLTYPE_4CHSCSI  (KLCLASS_IO  | 0x2)
-#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
-#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
-#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
-#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
+#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
 #define KLTYPE_UNUSED   (KLCLASS_IO  | 0x5) /* XXX UNUSED */
-#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
 #define KLTYPE_PCI      KLTYPE_HAROLD
-#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
-#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
-#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
-#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
-#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
-#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
-#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
+#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
 
 #define KLTYPE_GFX      (KLCLASS_GFX | 0x0) /* unknown graphics type */
 #define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
 #define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
 
 #define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
-#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
+#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
 #define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
 #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
 
 #define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
 #define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
-#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
 #define KLTYPE_PBRICK_XBOW      (KLCLASS_MIDPLANE | 0x2)
 
 #define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
@@ -398,11 +398,11 @@ typedef struct kl_config_hdr {
  * When bringup started nic names had not standardized and so we
  * had to hard code. (For people interested in history.)
  */
-#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
+#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
 
 #define KLTYPE_UNKNOWN  (KLCLASS_UNKNOWN | 0xf)
 
-#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
+#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
 #define IS_MIO_PRESENT(l)       ((l->brd_type == KLTYPE_BASEIO) && \
                                  (l->brd_flags & SECOND_NIC_PRESENT))
 #define IS_MIO_IOC3(l, n)       (IS_MIO_PRESENT(l) && (n > 2))
@@ -416,33 +416,33 @@ typedef struct kl_config_hdr {
 #define LOCAL_BOARD 1
 #define REMOTE_BOARD 2
 
-#define LBOARD_STRUCT_VERSION   2
+#define LBOARD_STRUCT_VERSION   2
 
 typedef struct lboard_s {
-        klconf_off_t    brd_next;         /* Next BOARD */
-        unsigned char   struct_type;      /* type of structure, local or remote */
-        unsigned char   brd_type;         /* type+class */
-        unsigned char   brd_sversion;     /* version of this structure */
-        unsigned char   brd_brevision;    /* board revision */
-        unsigned char   brd_promver;      /* board prom version, if any */
-        unsigned char   brd_flags;        /* Enabled, Disabled etc */
-        unsigned char   brd_slot;         /* slot number */
-        unsigned short  brd_debugsw;      /* Debug switches */
-        moduleid_t      brd_module;       /* module to which it belongs */
-        partid_t        brd_partition;    /* Partition number */
-        unsigned short  brd_diagval;      /* diagnostic value */
-        unsigned short  brd_diagparm;     /* diagnostic parameter */
-        unsigned char   brd_inventory;    /* inventory history */
-        unsigned char   brd_numcompts;    /* Number of components */
-        nic_t           brd_nic;          /* Number in CAN */
-        nasid_t         brd_nasid;        /* passed parameter */
-        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
-        klconf_off_t    brd_errinfo;      /* Board's error information */
+        klconf_off_t    brd_next;         /* Next BOARD */
+        unsigned char   struct_type;      /* type of structure, local or remote */
+        unsigned char   brd_type;         /* type+class */
+        unsigned char   brd_sversion;     /* version of this structure */
+        unsigned char   brd_brevision;    /* board revision */
+        unsigned char   brd_promver;      /* board prom version, if any */
+        unsigned char   brd_flags;        /* Enabled, Disabled etc */
+        unsigned char   brd_slot;         /* slot number */
+        unsigned short  brd_debugsw;      /* Debug switches */
+        moduleid_t      brd_module;       /* module to which it belongs */
+        partid_t        brd_partition;    /* Partition number */
+        unsigned short  brd_diagval;      /* diagnostic value */
+        unsigned short  brd_diagparm;     /* diagnostic parameter */
+        unsigned char   brd_inventory;    /* inventory history */
+        unsigned char   brd_numcompts;    /* Number of components */
+        nic_t           brd_nic;          /* Number in CAN */
+        nasid_t         brd_nasid;        /* passed parameter */
+        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+        klconf_off_t    brd_errinfo;      /* Board's error information */
         struct lboard_s *brd_parent;      /* Logical parent for this brd */
-        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
+        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
         confidence_t    brd_confidence;   /* confidence that the board is bad */
-        nasid_t         brd_owner;        /* who owns this board */
-        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+        nasid_t         brd_owner;        /* who owns this board */
+        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
         char            brd_name[32];
 } lboard_t;
 
@@ -456,23 +456,23 @@ typedef struct lboard_s {
 
 #define KLCF_CLASS(_brd)        KLCLASS((_brd)->brd_type)
 #define KLCF_TYPE(_brd)         KLTYPE((_brd)->brd_type)
-#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
 #define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
 #define KLCF_MODULE_ID(_brd)    ((_brd)->brd_module)
 
-#define KLCF_NEXT(_brd)         \
-        ((_brd)->brd_next ?     \
+#define KLCF_NEXT(_brd)         \
+        ((_brd)->brd_next ?     \
          (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
          NULL)
-#define KLCF_COMP(_brd, _ndx)   \
-                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
+#define KLCF_COMP(_brd, _ndx)   \
+                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
                                                (_brd)->brd_compts[(_ndx)]))
 
 #define KLCF_COMP_ERROR(_brd, _comp)    \
-               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
 
 #define KLCF_COMP_TYPE(_comp)   ((_comp)->struct_type)
-#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
+#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
 
 
 
@@ -481,73 +481,73 @@ typedef struct lboard_s {
  * component.
  */
 
-typedef struct klinfo_s {                  /* Generic info */
-        unsigned char   struct_type;       /* type of this structure */
-        unsigned char   struct_version;    /* version of this structure */
-        unsigned char   flags;            /* Enabled, disabled etc */
-        unsigned char   revision;         /* component revision */
-        unsigned short  diagval;          /* result of diagnostics */
-        unsigned short  diagparm;         /* diagnostic parameter */
-        unsigned char   inventory;        /* previous inventory status */
-        nic_t           nic;              /* MUst be aligned properly */
-        unsigned char   physid;           /* physical id of component */
-        unsigned int    virtid;           /* virtual id as seen by system */
-        unsigned char   widid;            /* Widget id - if applicable */
-        nasid_t         nasid;            /* node number - from parent */
+typedef struct klinfo_s {                  /* Generic info */
+        unsigned char   struct_type;       /* type of this structure */
+        unsigned char   struct_version;    /* version of this structure */
+        unsigned char   flags;            /* Enabled, disabled etc */
+        unsigned char   revision;         /* component revision */
+        unsigned short  diagval;          /* result of diagnostics */
+        unsigned short  diagparm;         /* diagnostic parameter */
+        unsigned char   inventory;        /* previous inventory status */
+        nic_t           nic;              /* MUst be aligned properly */
+        unsigned char   physid;           /* physical id of component */
+        unsigned int    virtid;           /* virtual id as seen by system */
+        unsigned char   widid;            /* Widget id - if applicable */
+        nasid_t         nasid;            /* node number - from parent */
         char            pad1;             /* pad out structure. */
         char            pad2;             /* pad out structure. */
-        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
-        klconf_off_t    errinfo;          /* component specific errors */
-        unsigned short  pad3;             /* pci fields have moved over to */
-        unsigned short  pad4;             /* klbri_t */
+        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
+        klconf_off_t    errinfo;          /* component specific errors */
+        unsigned short  pad3;             /* pci fields have moved over to */
+        unsigned short  pad4;             /* klbri_t */
 } klinfo_t ;
 
 #define KLCONFIG_INFO_ENABLED(_i)       ((_i)->flags & KLINFO_ENABLE)
 /*
  * Component structures.
  * Following are the currently identified components:
- *      CPU, HUB, MEM_BANK,
- *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
- *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
- *      ROUTER
- *      GRAPHICS
+ *      CPU, HUB, MEM_BANK,
+ *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
+ *      ROUTER
+ *      GRAPHICS
  */
 #define KLSTRUCT_UNKNOWN        0
-#define KLSTRUCT_CPU            1
-#define KLSTRUCT_HUB            2
-#define KLSTRUCT_MEMBNK         3
-#define KLSTRUCT_XBOW           4
-#define KLSTRUCT_BRI            5
-#define KLSTRUCT_IOC3           6
-#define KLSTRUCT_PCI            7
-#define KLSTRUCT_VME            8
+#define KLSTRUCT_CPU            1
+#define KLSTRUCT_HUB            2
+#define KLSTRUCT_MEMBNK         3
+#define KLSTRUCT_XBOW           4
+#define KLSTRUCT_BRI            5
+#define KLSTRUCT_IOC3           6
+#define KLSTRUCT_PCI            7
+#define KLSTRUCT_VME            8
 #define KLSTRUCT_ROU            9
-#define KLSTRUCT_GFX            10
-#define KLSTRUCT_SCSI           11
-#define KLSTRUCT_FDDI           12
-#define KLSTRUCT_MIO            13
-#define KLSTRUCT_DISK           14
-#define KLSTRUCT_TAPE           15
-#define KLSTRUCT_CDROM          16
-#define KLSTRUCT_HUB_UART       17
-#define KLSTRUCT_IOC3ENET       18
-#define KLSTRUCT_IOC3UART       19
+#define KLSTRUCT_GFX            10
+#define KLSTRUCT_SCSI           11
+#define KLSTRUCT_FDDI           12
+#define KLSTRUCT_MIO            13
+#define KLSTRUCT_DISK           14
+#define KLSTRUCT_TAPE           15
+#define KLSTRUCT_CDROM          16
+#define KLSTRUCT_HUB_UART       17
+#define KLSTRUCT_IOC3ENET       18
+#define KLSTRUCT_IOC3UART       19
 #define KLSTRUCT_UNUSED         20 /* XXX UNUSED */
-#define KLSTRUCT_IOC3PCKM       21
-#define KLSTRUCT_RAD            22
-#define KLSTRUCT_HUB_TTY        23
-#define KLSTRUCT_IOC3_TTY       24
+#define KLSTRUCT_IOC3PCKM       21
+#define KLSTRUCT_RAD            22
+#define KLSTRUCT_HUB_TTY        23
+#define KLSTRUCT_IOC3_TTY       24
 
 /* Early Access IO proms are compatible
    only with KLSTRUCT values up to 24. */
 
-#define KLSTRUCT_FIBERCHANNEL   25
+#define KLSTRUCT_FIBERCHANNEL   25
 #define KLSTRUCT_MOD_SERIAL_NUM 26
-#define KLSTRUCT_IOC3MS         27
-#define KLSTRUCT_TPU            28
-#define KLSTRUCT_GSN_A          29
-#define KLSTRUCT_GSN_B          30
-#define KLSTRUCT_XTHD           31
+#define KLSTRUCT_IOC3MS         27
+#define KLSTRUCT_TPU            28
+#define KLSTRUCT_GSN_A          29
+#define KLSTRUCT_GSN_B          30
+#define KLSTRUCT_XTHD           31
 
 /*
  * These are the indices of various components within a lboard structure.
@@ -583,7 +583,7 @@ typedef u64 *router_t;
  * The port info in ip27_cfg area translates to a lboart_t in the
  * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
  * is stored in terms of a nasid and a offset from start of KLCONFIG
- * area  on that nasid.
+ * area  on that nasid.
  */
 typedef struct klport_s {
         nasid_t         port_nasid;
@@ -591,20 +591,20 @@ typedef struct klport_s {
         klconf_off_t    port_offset;
 } klport_t;
 
-typedef struct klcpu_s {                          /* CPU */
-        klinfo_t        cpu_info;
-        unsigned short  cpu_prid;       /* Processor PRID value */
-        unsigned short  cpu_fpirr;      /* FPU IRR value */
-        unsigned short  cpu_speed;      /* Speed in MHZ */
-        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
-        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
+typedef struct klcpu_s {                          /* CPU */
+        klinfo_t        cpu_info;
+        unsigned short  cpu_prid;       /* Processor PRID value */
+        unsigned short  cpu_fpirr;      /* FPU IRR value */
+        unsigned short  cpu_speed;      /* Speed in MHZ */
+        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
+        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
 } klcpu_t ;
 
 #define CPU_STRUCT_VERSION   2
 
 typedef struct klhub_s {                        /* HUB */
-        klinfo_t        hub_info;
-        unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
+        klinfo_t        hub_info;
+        unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
         klport_t        hub_port;               /* hub is connected to this */
         nic_t           hub_box_nic;            /* nic of containing box */
         klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
@@ -612,36 +612,36 @@ typedef struct klhub_s {			/* HUB */
 } klhub_t ;
 
 typedef struct klhub_uart_s {                   /* HUB */
-        klinfo_t        hubuart_info;
-        unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
+        klinfo_t        hubuart_info;
+        unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
         nic_t           hubuart_box_nic;        /* nic of containing box */
 } klhub_uart_t ;
 
-#define MEMORY_STRUCT_VERSION   2
+#define MEMORY_STRUCT_VERSION   2
 
 typedef struct klmembnk_s {                     /* MEMORY BANK */
-        klinfo_t        membnk_info;
-        short           membnk_memsz;           /* Total memory in megabytes */
+        klinfo_t        membnk_info;
+        short           membnk_memsz;           /* Total memory in megabytes */
         short           membnk_dimm_select; /* bank to physical addr mapping*/
         short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
         short           membnk_attr;
 } klmembnk_t ;
 
 #define KLCONFIG_MEMBNK_SIZE(_info, _bank)      \
-                            ((_info)->membnk_bnksz[(_bank)])
+                            ((_info)->membnk_bnksz[(_bank)])
 
 
 #define MEMBNK_PREMIUM 1
 #define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)   \
-                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
 
 #define MAX_SERIAL_NUM_SIZE 10
 
 typedef struct klmod_serial_num_s {
-      klinfo_t        snum_info;
+      klinfo_t        snum_info;
       union {
-              char snum_str[MAX_SERIAL_NUM_SIZE];
-              unsigned long long       snum_int;
+              char snum_str[MAX_SERIAL_NUM_SIZE];
+              unsigned long long       snum_int;
       } snum;
 } klmod_serial_num_t;
 
@@ -650,43 +650,43 @@ typedef struct klmod_serial_num_s {
    serial number struct as a component without losing compatibility
    between prom versions. */
 
-#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
+#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
                                 KLCF_COMP(_l, _l->brd_numcompts))
 
 #define MAX_XBOW_LINKS 16
 
-typedef struct klxbow_s {                          /* XBOW */
-        klinfo_t        xbow_info ;
+typedef struct klxbow_s {                          /* XBOW */
+        klinfo_t        xbow_info ;
         klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
-        int             xbow_master_hub_link;
-        /* type of brd connected+component struct ptr+flags */
+        int             xbow_master_hub_link;
+        /* type of brd connected+component struct ptr+flags */
 } klxbow_t ;
 
 #define MAX_PCI_SLOTS 8
 
 typedef struct klpci_device_s {
         s32     pci_device_id;  /* 32 bits of vendor/device ID. */
-        s32     pci_device_pad; /* 32 bits of padding. */
+        s32     pci_device_pad; /* 32 bits of padding. */
 } klpci_device_t;
 
 #define BRIDGE_STRUCT_VERSION   2
 
-typedef struct klbri_s {                          /* BRIDGE */
-        klinfo_t        bri_info ;
-        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
-        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
-        pci_t           pci_specific  ;    /* PCI Board config info */
+typedef struct klbri_s {                          /* BRIDGE */
+        klinfo_t        bri_info ;
+        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
+        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+        pci_t           pci_specific  ;    /* PCI Board config info */
         klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
         klconf_off_t    bri_mfg_nic ;
 } klbri_t ;
 
 #define MAX_IOC3_TTY    2
 
-typedef struct klioc3_s {                          /* IOC3 */
-        klinfo_t        ioc3_info ;
-        unsigned char   ioc3_ssram ;        /* Info about ssram */
-        unsigned char   ioc3_nvram ;        /* Info about nvram */
-        klinfo_t        ioc3_superio ;      /* Info about superio */
+typedef struct klioc3_s {                          /* IOC3 */
+        klinfo_t        ioc3_info ;
+        unsigned char   ioc3_ssram ;        /* Info about ssram */
+        unsigned char   ioc3_nvram ;        /* Info about nvram */
+        klinfo_t        ioc3_superio ;      /* Info about superio */
         klconf_off_t    ioc3_tty_off ;
         klinfo_t        ioc3_enet ;
         klconf_off_t    ioc3_enet_off ;
@@ -695,27 +695,27 @@ typedef struct klioc3_s {                          /* IOC3 */
 
 #define MAX_VME_SLOTS 8
 
-typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
-        klinfo_t        vmeb_info ;
+typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
+        klinfo_t        vmeb_info ;
         vmeb_t          vmeb_specific ;
-        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
 } klvmeb_t ;
 
-typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
         klinfo_t        vmed_info ;
         vmed_t          vmed_specific ;
-        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
 } klvmed_t ;
 
 #define ROUTER_VECTOR_VERS      2
 
 /* XXX - Don't we need the number of ports here?!? */
-typedef struct klrou_s {                          /* ROUTER */
-        klinfo_t        rou_info ;
-        unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
-        nic_t           rou_box_nic ;         /* nic of the containing module */
-        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
-        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
+typedef struct klrou_s {                          /* ROUTER */
+        klinfo_t        rou_info ;
+        unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
+        nic_t           rou_box_nic ;         /* nic of the containing module */
+        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
         u64     rou_vector;       /* vector from master node */
 } klrou_t ;
 
@@ -732,30 +732,30 @@ typedef struct klrou_s {                          /* ROUTER */
 #define KLGFX_COOKIE    0x0c0de000
 
 typedef struct klgfx_s {                /* GRAPHICS Device */
-        klinfo_t        gfx_info;
-        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
-        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
+        klinfo_t        gfx_info;
+        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
+        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
         unsigned int            cookie;         /* for compatibility with older proms */
         unsigned int            moduleslot;
         struct klgfx_s  *gfx_next_pipe;
         graphics_t      gfx_specific;
-        klconf_off_t    pad0;           /* for compatibility with older proms */
-        klconf_off_t    gfx_mfg_nic;
+        klconf_off_t    pad0;           /* for compatibility with older proms */
+        klconf_off_t    gfx_mfg_nic;
 } klgfx_t;
 
 typedef struct klxthd_s {
-        klinfo_t        xthd_info ;
-        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
+        klinfo_t        xthd_info ;
+        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
 } klxthd_t ;
 
-typedef struct kltpu_s {                     /* TPU board */
-        klinfo_t        tpu_info ;
-        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
+typedef struct kltpu_s {                     /* TPU board */
+        klinfo_t        tpu_info ;
+        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
 } kltpu_t ;
 
-typedef struct klgsn_s {                     /* GSN board */
-        klinfo_t        gsn_info ;
-        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
+typedef struct klgsn_s {                     /* GSN board */
+        klinfo_t        gsn_info ;
+        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
 } klgsn_t ;
 
 #define MAX_SCSI_DEVS 16
@@ -767,57 +767,57 @@ typedef struct klgsn_s {                     /* GSN board */
  * that as the size to be klmalloced.
  */
 
-typedef struct klscsi_s {                          /* SCSI Controller */
-        klinfo_t        scsi_info ;
-        scsi_t          scsi_specific   ;
-        unsigned char   scsi_numdevs ;
+typedef struct klscsi_s {                          /* SCSI Controller */
+        klinfo_t        scsi_info ;
+        scsi_t          scsi_specific   ;
+        unsigned char   scsi_numdevs ;
         klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
 } klscsi_t ;
 
-typedef struct klscdev_s {                          /* SCSI device */
-        klinfo_t        scdev_info ;
+typedef struct klscdev_s {                          /* SCSI device */
+        klinfo_t        scdev_info ;
         struct scsidisk_data *scdev_cfg ; /* driver fills up this */
 } klscdev_t ;
 
-typedef struct klttydev_s {                          /* TTY device */
-        klinfo_t        ttydev_info ;
+typedef struct klttydev_s {                          /* TTY device */
+        klinfo_t        ttydev_info ;
         struct terminal_data *ttydev_cfg ; /* driver fills up this */
 } klttydev_t ;
 
-typedef struct klenetdev_s {                          /* ENET device */
-        klinfo_t        enetdev_info ;
+typedef struct klenetdev_s {                          /* ENET device */
+        klinfo_t        enetdev_info ;
         struct net_data *enetdev_cfg ; /* driver fills up this */
 } klenetdev_t ;
 
-typedef struct klkbddev_s {                          /* KBD device */
-        klinfo_t        kbddev_info ;
+typedef struct klkbddev_s {                          /* KBD device */
+        klinfo_t        kbddev_info ;
         struct keyboard_data *kbddev_cfg ; /* driver fills up this */
 } klkbddev_t ;
 
-typedef struct klmsdev_s {                          /* mouse device */
-        klinfo_t        msdev_info ;
-        void            *msdev_cfg ;
+typedef struct klmsdev_s {                          /* mouse device */
+        klinfo_t        msdev_info ;
+        void            *msdev_cfg ;
 } klmsdev_t ;
 
 #define MAX_FDDI_DEVS 10 /* XXX Is this true */
 
-typedef struct klfddi_s {                          /* FDDI */
-        klinfo_t        fddi_info ;
-        fddi_t          fddi_specific ;
+typedef struct klfddi_s {                          /* FDDI */
+        klinfo_t        fddi_info ;
+        fddi_t          fddi_specific ;
         klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
 } klfddi_t ;
 
-typedef struct klmio_s {                          /* MIO */
-        klinfo_t        mio_info ;
-        mio_t           mio_specific   ;
+typedef struct klmio_s {                          /* MIO */
+        klinfo_t        mio_info ;
+        mio_t           mio_specific   ;
 } klmio_t ;
 
 
 typedef union klcomp_s {
         klcpu_t         kc_cpu;
         klhub_t         kc_hub;
-        klmembnk_t      kc_mem;
-        klxbow_t        kc_xbow;
+        klmembnk_t      kc_mem;
+        klxbow_t        kc_xbow;
         klbri_t         kc_bri;
         klioc3_t        kc_ioc3;
         klvmeb_t        kc_vmeb;
@@ -831,11 +831,11 @@ typedef union klcomp_s {
         klmod_serial_num_t kc_snum ;
 } klcomp_t;
 
-typedef union kldev_s {      /* for device structure allocation */
+typedef union kldev_s {      /* for device structure allocation */
         klscdev_t       kc_scsi_dev ;
         klttydev_t      kc_tty_dev ;
         klenetdev_t     kc_enet_dev ;
-        klkbddev_t      kc_kbd_dev ;
+        klkbddev_t      kc_kbd_dev ;
 } kldev_t ;
 
 /* Data structure interface routines. TBD */
diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
index 1327e12e9645..bfb3aec94539 100644
--- a/arch/mips/include/asm/sn/kldir.h
+++ b/arch/mips/include/asm/sn/kldir.h
@@ -16,8 +16,8 @@
  * The kldir memory area resides at a fixed place in each node's memory and
  * provides pointers to most other IP27 memory areas.  This allows us to
  * resize and/or relocate memory areas at a later time without breaking all
- * firmware and kernels that use them.  Indices in the array are
- * permanently dedicated to areas listed below.  Some memory areas (marked
+ * firmware and kernels that use them.  Indices in the array are
+ * permanently dedicated to areas listed below.  Some memory areas (marked
  * below) reside at a permanently fixed location, but are included in the
  * directory for completeness.
  */
@@ -28,98 +28,98 @@
  * The upper portion of the memory map applies during boot
  * only and is overwritten by IRIX/SYMMON.
  *
- *                                    MEMORY MAP PER NODE
+ *                                    MEMORY MAP PER NODE
  *
- * 0x2000000 (32M)         +-----------------------------------------+
- *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
- * 0x1F80000 (31.5M)       +-----------------------------------------+
- *                         |      IO6 TEXT/DATA/BSS/stack            |
- * 0x1C00000 (30M)         +-----------------------------------------+
- *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
- * 0x0800000 (28M)         +-----------------------------------------+
- *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
- * 0x1B00000 (27M)         +-----------------------------------------+
- *                         |      IP27 CFG                           |
- * 0x1A00000 (26M)         +-----------------------------------------+
- *                         |      Graphics PROM                      |
- * 0x1800000 (24M)         +-----------------------------------------+
- *                         |      3rd Party PROM drivers             |
- * 0x1600000 (22M)         +-----------------------------------------+
- *                         |                                         |
- *                         |      Free                               |
- *                         |                                         |
- *                         +-----------------------------------------+
- *                         |      UNIX DEBUG Version                 |
- * 0x190000 (2M--)         +-----------------------------------------+
- *                         |      SYMMON                             |
- *                         |      (For UNIX Debug only)              |
- * 0x34000 (208K)          +-----------------------------------------+
- *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
- *                         |      (For UNIX Debug only)              |
- * 0x25000 (148K)          +-----------------------------------------+
- *                         |      KLCONFIG - II (temp)               |
- *                         |                                         |
- *                         |    ----------------------------         |
- *                         |                                         |
- *                         |      UNIX NON-DEBUG Version             |
- * 0x19000 (100K)          +-----------------------------------------+
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)         +-----------------------------------------+
+ *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)         +-----------------------------------------+
+ *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)         +-----------------------------------------+
+ *                         |      IP27 CFG                           |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Graphics PROM                      |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)         +-----------------------------------------+
+ *                         |      SYMMON                             |
+ *                         |      (For UNIX Debug only)              |
+ * 0x34000 (208K)          +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x25000 (148K)          +-----------------------------------------+
+ *                         |      KLCONFIG - II (temp)               |
+ *                         |                                         |
+ *                         |    ----------------------------         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)          +-----------------------------------------+
  *
  *
  * The lower portion of the memory map contains information that is
  * permanent and is used by the IP27PROM, IO6PROM and IRIX.
  *
- * 0x19000 (100K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      PI Error Spools (32K)              |
- *                         |                                         |
- * 0x12000 (72K)           +-----------------------------------------+
- *                         |      Unused                             |
- * 0x11c00 (71K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Eframe area              |
- * 0x11a00 (70.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Eframe area              |
- * 0x11800 (70K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Register save area       |
- * 0x11600 (69.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Register save area       |
- * 0x11400 (69K)           +-----------------------------------------+
- *                         |      GDA (1k)                           |
- * 0x11000 (68K)           +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                         |      kernel/io6prom nmi registers       |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (32K)              |
+ *                         |                                         |
+ * 0x12000 (72K)           +-----------------------------------------+
+ *                         |      Unused                             |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Eframe area              |
+ * 0x11a00 (70.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Eframe area              |
+ * 0x11800 (70K)           +-----------------------------------------+
+ *                         |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)         +-----------------------------------------+
+ *                         |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x11000 (68K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
  * 0x10800  (66k)          +-----------------------------------------+
- *                         |      cache error eframe                 |
- * 0x10400 (65K)           +-----------------------------------------+
- *                         |      Exception Handlers (UALIAS copy)   |
- * 0x10000 (64K)           +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      KLCONFIG - I (permanent) (48K)     |
- *                         |                                         |
- *                         |                                         |
- *                         |                                         |
- * 0x4000 (16K)            +-----------------------------------------+
- *                         |      NMI Handler (Protected Page)       |
- * 0x3000 (12K)            +-----------------------------------------+
- *                         |      ARCS PVECTORS (master node only)   |
- * 0x2c00 (11K)            +-----------------------------------------+
- *                         |      ARCS TVECTORS (master node only)   |
- * 0x2800 (10K)            +-----------------------------------------+
- *                         |      LAUNCH [NUM_CPU]                   |
- * 0x2400 (9K)             +-----------------------------------------+
- *                         |      Low memory directory (KLDIR)       |
- * 0x2000 (8K)             +-----------------------------------------+
- *                         |      ARCS SPB (1K)                      |
- * 0x1000 (4K)             +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                         |      kernel/io6prom nmi registers       |
- * 0x800  (2k)             +-----------------------------------------+
- *                         |      cache error eframe                 |
- * 0x400 (1K)              +-----------------------------------------+
- *                         |      Exception Handlers                 |
- * 0x0   (0K)              +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      KLCONFIG - I (permanent) (48K)     |
+ *                         |                                         |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x4000 (16K)            +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)            +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)            +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)            +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)             +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)             +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)             +-----------------------------------------+
+ *                         |      Early cache Exception stack        |
+ *                         |             and/or                      |
+ *                         |      kernel/io6prom nmi registers       |
+ * 0x800  (2k)             +-----------------------------------------+
+ *                         |      cache error eframe                 |
+ * 0x400 (1K)              +-----------------------------------------+
+ *                         |      Exception Handlers                 |
+ * 0x0   (0K)              +-----------------------------------------+
  */
 
 #ifdef __ASSEMBLY__
@@ -202,13 +202,13 @@
 
 #ifndef __ASSEMBLY__
 typedef struct kldir_ent_s {
-        u64             magic;          /* Indicates validity of entry      */
+        u64             magic;          /* Indicates validity of entry      */
         off_t           offset;         /* Offset from start of node space  */
         unsigned long   pointer;        /* Pointer to area in some cases    */
-        size_t          size;           /* Size in bytes                    */
+        size_t          size;           /* Size in bytes                    */
         u64             count;          /* Repeat count if array, 1 if not  */
-        size_t          stride;         /* Stride if array, 0 if not        */
-        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
+        size_t          stride;         /* Stride if array, 0 if not        */
+        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
         /* NOTE: These 16 bytes are used in the Partition KLDIR
            entry to store partition info. Refer to klpart.h for this. */
 } kldir_ent_t;
diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h
index b7c2226312c6..04226d8d30c4 100644
--- a/arch/mips/include/asm/sn/launch.h
+++ b/arch/mips/include/asm/sn/launch.h
@@ -19,7 +19,7 @@
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends
- * an interrupt to the slave processor.  The slave calls the desired
+ * an interrupt to the slave processor.  The slave calls the desired
  * function, then returns to the slave loop.  The master may poll or wait
  * for the slaves to finish.
  *
@@ -33,7 +33,7 @@
 #define LAUNCH_PADSZ            0xa0
 #endif
 
-#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
+#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
 #define LAUNCH_OFF_BUSY         0x08
 #define LAUNCH_OFF_CALL         0x10
 #define LAUNCH_OFF_CALLC        0x18
@@ -44,7 +44,7 @@
 #define LAUNCH_OFF_BEVNORMAL    0x40
 #define LAUNCH_OFF_BEVECC       0x48
 
-#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
+#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
 #define LAUNCH_STATE_SENT       1
 #define LAUNCH_STATE_RECD       2
 
@@ -65,16 +65,16 @@ typedef int launch_state_t;
 typedef void (*launch_proc_t)(u64 call_parm);
 
 typedef struct launch_s {
-        volatile u64            magic;  /* Magic number                     */
-        volatile u64            busy;   /* Slave currently active           */
+        volatile u64            magic;  /* Magic number                     */
+        volatile u64            busy;   /* Slave currently active           */
         volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
         volatile u64            call_addr_c;    /* 1's complement of call_addr*/
         volatile u64            call_parm;      /* Single parm passed to call*/
         volatile void *stack_addr;      /* Stack pointer for slave function */
         volatile void *gp_addr;         /* Global pointer for slave func.   */
-        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
-        volatile char           *bevnormal;/*Address of bev normal ex handler */
-        volatile char           *bevecc;/* Address of bev cache err handler */
+        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
+        volatile char           *bevnormal;/*Address of bev normal ex handler */
+        volatile char           *bevecc;/* Address of bev cache err handler */
         volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
 } launch_t;
 
diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
index 721496a0bb92..401f3b0eee17 100644
--- a/arch/mips/include/asm/sn/mapped_kernel.h
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
@@ -48,7 +48,7 @@
 
 #endif /* CONFIG_MAPPED_KERNEL */
 
-#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
-#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
+#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
+#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
 
 #endif /* __ASM_SN_MAPPED_KERNEL_H  */
diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
index 1af49897d4e1..12ac210f12a1 100644
--- a/arch/mips/include/asm/sn/nmi.h
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -19,7 +19,7 @@
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends
- * an interrupt to the slave processor.  The slave calls the desired
+ * an interrupt to the slave processor.  The slave calls the desired
  * function, followed by an optional rendezvous function, then returns to
  * the slave loop.  The master does not wait for the slaves before
  * returning.
@@ -31,7 +31,7 @@
 #define NMI_MAGIC               0x48414d4d455201
 #define NMI_SIZEOF              0x40
 
-#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
+#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
 #define NMI_OFF_FLAGS           0x08
 #define NMI_OFF_CALL            0x10
 #define NMI_OFF_CALLC           0x18
@@ -53,8 +53,8 @@
 typedef struct nmi_s {
         volatile unsigned long   magic;         /* Magic number */
         volatile unsigned long   flags;         /* Combination of flags above */
-        volatile void *call_addr;       /* Routine for slave to call        */
-        volatile void *call_addr_c;     /* 1's complement of address        */
+        volatile void *call_addr;       /* Routine for slave to call        */
+        volatile void *call_addr_c;     /* 1's complement of address        */
         volatile void *call_parm;       /* Single parm passed to call       */
         volatile unsigned long   gmaster;       /* Flag true only on global master*/
 } nmi_t;
diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
index b06190093bbc..6b53070f400f 100644
--- a/arch/mips/include/asm/sn/sn0/addrs.h
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -29,7 +29,7 @@
  * chapter of the Hub specification.
  *
  * NOTE: This header file is included both by C and by assembler source
- *       files.  Please bracket any language-dependent definitions
+ *       files.  Please bracket any language-dependent definitions
  *       appropriately.
  */
 
@@ -102,14 +102,14 @@
 
 #define BWIN_INDEX_BITS         3
 #define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
-#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
-#define BWIN_WIDGET_MASK        0x7
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
 #define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
-#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
                         (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
 
-#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
-#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
 /*
  * Verify if addr belongs to large window address of node with "nasid"
  *
@@ -120,7 +120,7 @@
  *
  */
 
-#define NODE_BWIN_ADDR(nasid, addr)     \
+#define NODE_BWIN_ADDR(nasid, addr)     \
                 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
                  ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
                                 BWIN_SIZE)))
@@ -129,7 +129,7 @@
  * The following define the major position-independent aliases used
  * in SN0.
  *      CALIAS -- Varies in size, points to the first n bytes of memory
- *                      on the reader's node.
+ *                      on the reader's node.
  */
 
 #define CALIAS_BASE             CAC_BASE
@@ -146,7 +146,7 @@
 
 #ifndef __ASSEMBLY__
 #define KERN_NMI_ADDR(nasid, slice)                                     \
-                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
                                   (IP27_NMI_KREGS_CPU_SIZE * (slice)))
 #endif /* !__ASSEMBLY__ */
 
@@ -203,7 +203,7 @@
 
 #define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
 #define IO6PROM_SIZE            0x400000
-#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
 #define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
 #define IO6DPROM_SIZE           0x200000
 
diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
index f734f2007f24..425a67e6a947 100644
--- a/arch/mips/include/asm/sn/sn0/arch.h
+++ b/arch/mips/include/asm/sn/sn0/arch.h
@@ -12,23 +12,23 @@
 #define _ASM_SN_SN0_ARCH_H
 
 
-#ifndef SN0XXL  /* 128 cpu SMP max */
+#ifndef SN0XXL  /* 128 cpu SMP max */
 /*
  * This is the maximum number of nodes that can be part of a kernel.
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  */
-#define MAX_COMPACT_NODES       64
+#define MAX_COMPACT_NODES       64
 
 /*
  * MAXCPUS refers to the maximum number of CPUs in a single kernel.
  * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
  */
-#define MAXCPUS                 128
+#define MAXCPUS                 128
 
 #else /* SN0XXL system */
 
-#define MAX_COMPACT_NODES       128
-#define MAXCPUS                 256
+#define MAX_COMPACT_NODES       128
+#define MAXCPUS                 256
 
 #endif /* SN0XXL */
 
@@ -41,9 +41,9 @@
 /*
  * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
  */
-#define MAX_REGIONS             64
-#define MAX_NONPREMIUM_REGIONS  16
-#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+#define MAX_REGIONS             64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
 
 /*
  * MAX_PARITIONS refers to the maximum number of logically defined
@@ -57,12 +57,12 @@
  * Slot constants for SN0
  */
 #ifdef CONFIG_SGI_SN_N_MODE
-#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#define MAX_MEM_SLOTS   16                      /* max slots per node */
 #else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
-#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#define MAX_MEM_SLOTS   32                      /* max slots per node */
 #endif /* CONFIG_SGI_SN_M_MODE */
 
-#define SLOT_SHIFT              (27)
+#define SLOT_SHIFT              (27)
 #define SLOT_MIN_MEM_SIZE       (32*1024*1024)
 
 #define CPUS_PER_NODE           2       /* CPUs on a single hub */
diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
index 3e228f8e7969..d78dd76d5dcf 100644
--- a/arch/mips/include/asm/sn/sn0/hub.h
+++ b/arch/mips/include/asm/sn/sn0/hub.h
@@ -19,8 +19,8 @@
 #define HUB_REV_2_0             2
 #define HUB_REV_2_1             3
 #define HUB_REV_2_2             4
-#define HUB_REV_2_3             5
-#define HUB_REV_2_4             6
+#define HUB_REV_2_3             5
+#define HUB_REV_2_4             6
 
 #define MAX_HUB_PATH            80
 
@@ -32,9 +32,9 @@
 //#include <asm/sn/sn0/hubcore.h>
 
 /* Translation of uncached attributes */
-#define UATTR_HSPEC     0
-#define UATTR_IO        1
-#define UATTR_MSPEC     2
-#define UATTR_UNCAC     3
+#define UATTR_HSPEC     0
+#define UATTR_IO        1
+#define UATTR_MSPEC     2
+#define UATTR_UNCAC     3
 
 #endif /* _ASM_SN_SN0_HUB_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 46286d8302a7..5998b13e9764 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SGI_SN_SN0_HUBIO_H
-#define _ASM_SGI_SN_SN0_HUBIO_H
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H
 
 /*
  * Hub I/O interface registers
@@ -22,7 +22,7 @@
  * Slightly friendlier names for some common registers.
  * The hardware definitions follow.
  */
-#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
 #define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
 #define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
 #define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
@@ -37,21 +37,21 @@
 #define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
 #define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
 #define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
-#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
 
 #define IIO_LLP_CSR_IS_UP               0x00002000
-#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
-#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
 
 /* key to IIO_PROTECT_OVRRD */
 #define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
 
 /* BTE register names */
 #define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
 #define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
 #define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
 #define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
 #define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
 #define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
@@ -83,11 +83,11 @@
 #define IIO_WSTAT       0x400008        /* Widget status */
 #define IIO_WCR         0x400020        /* Widget control */
 
-#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
-#define IIO_WSTAT_TXRETRY_SHFT  (16)
-#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
                                           IIO_WSTAT_TXRETRY_MASK)
 
 #define IIO_ILAPR       0x400100        /* Local Access Protection */
@@ -130,12 +130,12 @@
 #define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
         (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
         (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
-        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
-        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
 
 /* Scratch registers (not all bits available) */
 #define IIO_SCRATCH_REG0        0x400150
-#define IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_REG1        0x400158
 #define IIO_SCRATCH_MASK        0x0000000f00f11fff
 
 #define IIO_SCRATCH_BIT0_0      0x0000000800000000
@@ -174,43 +174,43 @@
 typedef union hubii_wid_u {
         u64     wid_reg_value;
         struct {
-                u64     wid_rsvd:       32,     /* unused */
+                u64     wid_rsvd:       32,     /* unused */
                         wid_rev_num:     4,     /* revision number */
                         wid_part_num:   16,     /* the widget type: hub=c101 */
                         wid_mfg_num:    11,     /* Manufacturer id (IBM) */
                         wid_rsvd1:       1;     /* Reserved */
-        } wid_fields_s;
+        } wid_fields_s;
 } hubii_wid_t;
 
 
 typedef union hubii_wcr_u {
         u64     wcr_reg_value;
         struct {
-                u64     wcr_rsvd:       41,     /* unused */
+                u64     wcr_rsvd:       41,     /* unused */
                         wcr_e_thresh:    5,     /* elasticity threshold */
                         wcr_dir_con:     1,     /* widget direct connect */
                         wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
                         wcr_xbar_crd:    3,     /* LLP crossbar credit */
                         wcr_rsvd1:       8,     /* Reserved */
-                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_tag_mode:    1,     /* Tag mode */
                         wcr_widget_id:   4;     /* LLP crossbar credit */
-        } wcr_fields_s;
+        } wcr_fields_s;
 } hubii_wcr_t;
 
-#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
 
 typedef union hubii_wstat_u {
-        u64      reg_value;
+        u64      reg_value;
         struct {
                 u64     rsvd1:          31,
                         crazy:           1,     /* Crazy bit            */
                         rsvd2:           8,
-                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
                         rsvd3:           6,
                         tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
                         rsvd4:           2,
                         xt_tail_to:      1,     /* Xtalk Tail Timeout   */
-                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
                         pending:         4;     /* Pending Requests     */
         } wstat_fields_s;
 } hubii_wstat_t;
@@ -219,50 +219,50 @@ typedef union hubii_wstat_u {
 typedef union hubii_ilcsr_u {
         u64     icsr_reg_value;
         struct {
-                u64     icsr_rsvd:      22,     /* unused */
-                        icsr_max_burst: 10,     /* max burst */
-                        icsr_rsvd4:      6,     /* reserved */
-                        icsr_max_retry: 10,     /* max retry */
-                        icsr_rsvd3:      2,     /* reserved */
-                        icsr_lnk_stat:   2,     /* link status */
-                        icsr_bm8:        1,     /* Bit mode 8 */
-                        icsr_llp_en:     1,     /* LLP enable bit */
-                        icsr_rsvd2:      1,     /* reserver */
-                        icsr_wrm_reset:  1,     /* Warm reset bit */
+                u64     icsr_rsvd:      22,     /* unused */
+                        icsr_max_burst: 10,     /* max burst */
+                        icsr_rsvd4:      6,     /* reserved */
+                        icsr_max_retry: 10,     /* max retry */
+                        icsr_rsvd3:      2,     /* reserved */
+                        icsr_lnk_stat:   2,     /* link status */
+                        icsr_bm8:        1,     /* Bit mode 8 */
+                        icsr_llp_en:     1,     /* LLP enable bit */
+                        icsr_rsvd2:      1,     /* reserver */
+                        icsr_wrm_reset:  1,     /* Warm reset bit */
                         icsr_rsvd1:      2,     /* Data ready offset */
-                        icsr_null_to:    6;     /* Null timeout   */
+                        icsr_null_to:    6;     /* Null timeout   */
 
-        } icsr_fields_s;
+        } icsr_fields_s;
 } hubii_ilcsr_t;
 
 
 typedef union hubii_iowa_u {
         u64     iowa_reg_value;
         struct {
-                u64     iowa_rsvd:      48,     /* unused */
+                u64     iowa_rsvd:      48,     /* unused */
                         iowa_wxoac:      8,     /* xtalk widget access bits */
                         iowa_rsvd1:      7,     /* xtalk widget access bits */
                         iowa_w0oac:      1;     /* xtalk widget access bits */
-        } iowa_fields_s;
+        } iowa_fields_s;
 } hubii_iowa_t;
 
 typedef union hubii_iiwa_u {
         u64     iiwa_reg_value;
         struct {
-                u64     iiwa_rsvd:      48,     /* unused */
+                u64     iiwa_rsvd:      48,     /* unused */
                         iiwa_wxiac:      8,     /* hub wid access bits */
                         iiwa_rsvd1:      7,     /* reserved */
                         iiwa_w0iac:      1;     /* hub wid0 access */
-        } iiwa_fields_s;
+        } iiwa_fields_s;
 } hubii_iiwa_t;
 
 typedef union   hubii_illr_u {
         u64     illr_reg_value;
         struct {
-                u64     illr_rsvd:      32,     /* unused */
+                u64     illr_rsvd:      32,     /* unused */
                         illr_cb_cnt:    16,     /* checkbit error count */
                         illr_sn_cnt:    16;     /* sequence number count */
-        } illr_fields_s;
+        } illr_fields_s;
 } hubii_illr_t;
 
 /* The structures below are defined to extract and modify the ii
@@ -273,7 +273,7 @@ performance registers */
 typedef union io_perf_sel {
         u64 perf_sel_reg;
         struct {
-                u64     perf_rsvd  : 48,
+                u64     perf_rsvd  : 48,
                         perf_icct  :  8,
                         perf_ippr1 :  4,
                         perf_ippr0 :  4;
@@ -301,7 +301,7 @@ typedef union io_perf_cnt {
 #define IIO_LLP_SN_MAX  0xffff
 
 /* IO PRB Entries */
-#define IIO_NUM_IPRBS   (9)
+#define IIO_NUM_IPRBS   (9)
 #define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
 #define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
 #define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
@@ -318,21 +318,21 @@ typedef union io_perf_cnt {
 #define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
 #define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
 #define IIO_IECLR       0x4001f8        /* IO error clear */
-#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+#define IIO_IBCN        0x400200        /* IO BTE CRB count */
 
 /*
  * IIO_IMEM Register fields.
  */
-#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
 
 /* PIO Read address Table Entries */
 #define IIO_IPCA        0x400300        /* PRB Counter adjust */
 #define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
 #define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
 #define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
-#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
 #define IIO_IPDR        0x400388        /* PIO table entry deallocation */
 #define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
 #define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
@@ -369,35 +369,35 @@ typedef union io_perf_cnt {
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  */
-#define IIO_IPDR_PND    (1 << 4)
+#define IIO_IPDR_PND    (1 << 4)
 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */
-#define IIO_ICDR_PND    (1 << 4)
+#define IIO_ICDR_PND    (1 << 4)
 
 /*
  * IIO CRB control register Fields: IIO_ICCR
  */
-#define IIO_ICCR_PENDING        (0x10000)
-#define IIO_ICCR_CMD_MASK       (0xFF)
-#define IIO_ICCR_CMD_SHFT       (7)
-#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
-#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
-#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
-#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
                                          * via a WB
                                          */
-#define IIO_ICCR_CMD_FLUSH      (0x800)
+#define IIO_ICCR_CMD_FLUSH      (0x800)
 
 /*
  * CRB manipulation macros
  *      The CRB macros are slightly complicated, since there are up to
- *      four registers associated with each CRB entry.
+ *      four registers associated with each CRB entry.
  */
 #define IIO_NUM_CRBS            15      /* Number of CRBs */
-#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
-#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
 #define IIO_ICRB_OFFSET         8
 #define IIO_ICRB_0              0x400400
 /* XXX - This is now tuneable:
@@ -405,9 +405,9 @@ typedef union io_perf_cnt {
  */
 
 #define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
-#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
 #define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
-#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
 
 /* XXX - IBUE register coming for Hub 2 */
 
@@ -444,16 +444,16 @@ typedef union io_perf_cnt {
 typedef union icrba_u {
         u64     reg_value;
         struct {
-                u64     resvd:  6,
+                u64     resvd:  6,
                         stall_bte0: 1,  /* Stall BTE 0 */
                         stall_bte1: 1,  /* Stall BTE 1 */
                         error:  1,      /* CRB has an error     */
-                        ecode:  3,      /* Error Code           */
+                        ecode:  3,      /* Error Code           */
                         lnetuce: 1,     /* SN0net Uncorrectable error */
-                        mark:   1,      /* CRB Has been marked  */
+                        mark:   1,      /* CRB Has been marked  */
                         xerr:   1,      /* Error bit set in xtalk header */
                         sidn:   4,      /* SIDN field from xtalk        */
-                        tnum:   5,      /* TNUM field in xtalk          */
+                        tnum:   5,      /* TNUM field in xtalk          */
                         addr:   38,     /* Address of request   */
                         valid:  1,      /* Valid status         */
                         iow:    1;      /* IO Write operation   */
@@ -467,15 +467,15 @@ typedef union h1_icrba_u {
         u64     reg_value;
 
         struct {
-                u64     resvd:  6,
-                        unused: 1,      /* Unused but RW!!      */
+                u64     resvd:  6,
+                        unused: 1,      /* Unused but RW!!      */
                         error:  1,      /* CRB has an error     */
-                        ecode:  4,      /* Error Code           */
+                        ecode:  4,      /* Error Code           */
                         lnetuce: 1,     /* SN0net Uncorrectable error */
-                        mark:   1,      /* CRB Has been marked  */
+                        mark:   1,      /* CRB Has been marked  */
                         xerr:   1,      /* Error bit set in xtalk header */
                         sidn:   4,      /* SIDN field from xtalk        */
-                        tnum:   5,      /* TNUM field in xtalk          */
+                        tnum:   5,      /* TNUM field in xtalk          */
                         addr:   38,     /* Address of request   */
                         valid:  1,      /* Valid status         */
                         iow:    1;      /* IO Write operation   */
@@ -488,21 +488,21 @@ typedef union h1_icrba_u {
 
 #endif /* !__ASSEMBLY__ */
 
-#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
 
 /*
  * values for "ecode" field
  */
-#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
                                          * e.g. WINV to a Read only line.
                                          */
-#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
 
 
 
@@ -513,10 +513,10 @@ typedef union h1_icrba_u {
 typedef union icrbb_u {
         u64     reg_value;
         struct {
-            u64 rsvd1:  5,
-                btenum: 1,      /* BTE to which entry belongs to */
-                cohtrans: 1,    /* Coherent transaction */
-                xtsize: 2,      /* Xtalk operation size
+            u64 rsvd1:  5,
+                btenum: 1,      /* BTE to which entry belongs to */
+                cohtrans: 1,    /* Coherent transaction */
+                xtsize: 2,      /* Xtalk operation size
                                  * 0: Double Word
                                  * 1: 32 Bytes.
                                  * 2: 128 Bytes,
@@ -526,11 +526,11 @@ typedef union icrbb_u {
                 srcinit: 2,     /* Source Initiator:
                                  * See below for field values.
                                  */
-                useold: 1,      /* Use OLD command for processing */
+                useold: 1,      /* Use OLD command for processing */
                 imsgtype: 2,    /* Incoming message type
                                  * see below for field values
                                  */
-                imsg:   8,      /* Incoming message     */
+                imsg:   8,      /* Incoming message     */
                 initator: 3,    /* Initiator of original request
                                  * See below for field values.
                                  */
@@ -538,12 +538,12 @@ typedef union icrbb_u {
                                  * See below for field values.
                                  */
                 rsvd2:  7,
-                ackcnt: 11,     /* Invalidate ack count */
+                ackcnt: 11,     /* Invalidate ack count */
                 resp:   1,      /* data response  given to processor */
-                ack:    1,      /* indicates data ack received  */
+                ack:    1,      /* indicates data ack received  */
                 hold:   1,      /* entry is gathering inval acks */
                 wb_pend:1,      /* waiting for writeback to complete */
-                intvn:  1,      /* Intervention */
+                intvn:  1,      /* Intervention */
                 stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
                 stall_intr: 1;  /* Stall internal interrupts */
         } icrbb_field_s;
@@ -556,9 +556,9 @@ typedef union h1_icrbb_u {
         u64     reg_value;
         struct {
                 u64     rsvd1:  5,
-                        btenum: 1,      /* BTE to which entry belongs to */
-                        cohtrans: 1,    /* Coherent transaction */
-                        xtsize: 2,      /* Xtalk operation size
+                        btenum: 1,      /* BTE to which entry belongs to */
+                        cohtrans: 1,    /* Coherent transaction */
+                        xtsize: 2,      /* Xtalk operation size
                                          * 0: Double Word
                                          * 1: 32 Bytes.
                                          * 2: 128 Bytes,
@@ -568,99 +568,99 @@ typedef union h1_icrbb_u {
                         srcinit: 2,     /* Source Initiator:
                                          * See below for field values.
                                          */
-                        useold: 1,      /* Use OLD command for processing */
+                        useold: 1,      /* Use OLD command for processing */
                         imsgtype: 2,    /* Incoming message type
                                          * see below for field values
                                          */
-                        imsg:   8,      /* Incoming message     */
+                        imsg:   8,      /* Incoming message     */
                         initator: 3,    /* Initiator of original request
                                          * See below for field values.
                                          */
-                        rsvd2:  1,
+                        rsvd2:  1,
                         pcache: 1,      /* entry belongs to partial cache */
                         reqtype: 5,     /* Identifies type of request
                                          * See below for field values.
                                          */
-                        stl_ib: 1,      /* stall Ibus coming from xtalk */
+                        stl_ib: 1,      /* stall Ibus coming from xtalk */
                         stl_intr: 1,    /* Stall internal interrupts */
-                        stl_bte0: 1,    /* Stall BTE 0  */
+                        stl_bte0: 1,    /* Stall BTE 0  */
                         stl_bte1: 1,    /* Stall BTE 1  */
-                        intrvn: 1,      /* Req was target of intervention */
-                        ackcnt: 11,     /* Invalidate ack count */
+                        intrvn: 1,      /* Req was target of intervention */
+                        ackcnt: 11,     /* Invalidate ack count */
                         resp:   1,      /* data response  given to processor */
-                        ack:    1,      /* indicates data ack received  */
+                        ack:    1,      /* indicates data ack received  */
                         hold:   1,      /* entry is gathering inval acks */
                         wb_pend:1,      /* waiting for writeback to complete */
-                        sleep:  1,      /* xtalk req sleeping till IO-sync */
+                        sleep:  1,      /* xtalk req sleeping till IO-sync */
                         pnd_reply: 1,   /* replies not issed due to IOQ full */
                         pnd_req: 1;     /* reqs not issued due to IOQ full */
         } h1_icrbb_field_s;
 } h1_icrbb_t;
 
 
-#define b_imsgtype      icrbb_field_s.imsgtype
-#define b_btenum        icrbb_field_s.btenum
-#define b_cohtrans      icrbb_field_s.cohtrans
-#define b_xtsize        icrbb_field_s.xtsize
-#define b_srcnode       icrbb_field_s.srcnode
-#define b_srcinit       icrbb_field_s.srcinit
-#define b_imsgtype      icrbb_field_s.imsgtype
-#define b_imsg          icrbb_field_s.imsg
-#define b_initiator     icrbb_field_s.initiator
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_btenum        icrbb_field_s.btenum
+#define b_cohtrans      icrbb_field_s.cohtrans
+#define b_xtsize        icrbb_field_s.xtsize
+#define b_srcnode       icrbb_field_s.srcnode
+#define b_srcinit       icrbb_field_s.srcinit
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_imsg          icrbb_field_s.imsg
+#define b_initiator     icrbb_field_s.initiator
 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * values for field xtsize
  */
-#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
-#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
-#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
 
 /*
  * values for field srcinit
  */
-#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
-#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
-#define IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
-#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
+#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
 
 /*
  * Values for field imsgtype
  */
-#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
-#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
 
 /*
  * values for field initiator.
  */
-#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
-#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
 
 /*
  * Values for field reqtype.
  */
 /* XXX - Need to fix this for Hub 2 */
-#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
-#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
-#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
-#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
-#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
-#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
-#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
-#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
-#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
-#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
-#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
-#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
-#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
-#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
-#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
 
 /*
  * Fields in CRB Register C
@@ -674,8 +674,8 @@ typedef union icrbc_s {
                 u64     rsvd:   6,
                         sleep:  1,
                         pricnt: 4,      /* Priority count sent with Read req */
-                        pripsc: 4,      /* Priority Pre scalar  */
-                        bteop:  1,      /* BTE Operation        */
+                        pripsc: 4,      /* Priority Pre scalar  */
+                        bteop:  1,      /* BTE Operation        */
                         push_be: 34,    /* Push address Byte enable
                                          * Holds push addr, if CRB is for BTE
                                          * If CRB belongs to Partial cache,
@@ -684,20 +684,20 @@ typedef union icrbc_s {
                                          */
                         suppl:  11,     /* Supplemental field   */
                         barrop: 1,      /* Barrier Op bit set in xtalk req */
-                        doresp: 1,      /* Xtalk req needs a response   */
-                        gbr:    1;      /* GBR bit set in xtalk packet  */
+                        doresp: 1,      /* Xtalk req needs a response   */
+                        gbr:    1;      /* GBR bit set in xtalk packet  */
         } icrbc_field_s;
 } icrbc_t;
 
-#define c_pricnt        icrbc_field_s.pricnt
-#define c_pripsc        icrbc_field_s.pripsc
-#define c_bteop         icrbc_field_s.bteop
-#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
-#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
-#define c_suppl         icrbc_field_s.suppl
-#define c_barrop        icrbc_field_s.barrop
-#define c_doresp        icrbc_field_s.doresp
-#define c_gbr   icrbc_field_s.gbr
+#define c_pricnt        icrbc_field_s.pricnt
+#define c_pripsc        icrbc_field_s.pripsc
+#define c_bteop         icrbc_field_s.bteop
+#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl         icrbc_field_s.suppl
+#define c_barrop        icrbc_field_s.barrop
+#define c_doresp        icrbc_field_s.doresp
+#define c_gbr   icrbc_field_s.gbr
 #endif /* !__ASSEMBLY__ */
 
 /*
@@ -708,31 +708,31 @@ typedef union icrbc_s {
 typedef union icrbd_s {
         u64     reg_value;
         struct {
-            u64 rsvd:   38,
+            u64 rsvd:   38,
                 toutvld: 1,     /* Timeout in progress for this CRB */
-                ctxtvld: 1,     /* Context field below is valid */
+                ctxtvld: 1,     /* Context field below is valid */
                 rsvd2:  1,
-                context: 15,    /* Bit vector:
+                context: 15,    /* Bit vector:
                                  * Has a bit set for each CRB entry
                                  * which needs to be deallocated
                                  * before this CRB entry is processed.
                                  * Set only for barrier operations.
                                  */
-                timeout: 8;     /* Timeout Upper 8 bits */
+                timeout: 8;     /* Timeout Upper 8 bits */
         } icrbd_field_s;
 } icrbd_t;
 
-#define icrbd_toutvld   icrbd_field_s.toutvld
-#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
-#define icrbd_context   icrbd_field_s.context
+#define icrbd_toutvld   icrbd_field_s.toutvld
+#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
+#define icrbd_context   icrbd_field_s.context
 
 
 typedef union hubii_ifdr_u {
         u64     hi_ifdr_value;
         struct {
                 u64     ifdr_rsvd:      49,
-                        ifdr_maxrp:      7,
-                        ifdr_rsvd1:      1,
+                        ifdr_maxrp:      7,
+                        ifdr_rsvd1:      1,
                         ifdr_maxrq:      7;
         } hi_ifdr_fields;
 } hubii_ifdr_t;
@@ -789,26 +789,26 @@ typedef union hubii_ifdr_u {
 typedef union iprte_a {
         u64     entry;
         struct {
-            u64 rsvd1     : 7,  /* Reserved field               */
-                valid     : 1,  /* Maps to a timeout entry      */
-                rsvd2     : 1,
-                srcnode   : 9,  /* Node which did this PIO      */
-                initiator : 2,  /* If T5A or T5B or IO          */
-                rsvd3     : 3,
-                addr      : 38, /* Physical address of PIO      */
-                rsvd4     : 3;
+            u64 rsvd1     : 7,  /* Reserved field               */
+                valid     : 1,  /* Maps to a timeout entry      */
+                rsvd2     : 1,
+                srcnode   : 9,  /* Node which did this PIO      */
+                initiator : 2,  /* If T5A or T5B or IO          */
+                rsvd3     : 3,
+                addr      : 38, /* Physical address of PIO      */
+                rsvd4     : 3;
         } iprte_fields;
 } iprte_a_t;
 
-#define iprte_valid     iprte_fields.valid
-#define iprte_timeout   iprte_fields.timeout
-#define iprte_srcnode   iprte_fields.srcnode
-#define iprte_init      iprte_fields.initiator
-#define iprte_addr      iprte_fields.addr
+#define iprte_valid     iprte_fields.valid
+#define iprte_timeout   iprte_fields.timeout
+#define iprte_srcnode   iprte_fields.srcnode
+#define iprte_init      iprte_fields.initiator
+#define iprte_addr      iprte_fields.addr
 
 #endif /* !__ASSEMBLY__ */
 
-#define IPRTE_ADDRSHFT  3
+#define IPRTE_ADDRSHFT  3
 
 /*
  * Hub IIO PRB Register format.
@@ -823,14 +823,14 @@ typedef union iprte_a {
 typedef union iprb_u {
         u64     reg_value;
         struct {
-            u64 rsvd1:  15,
+            u64 rsvd1:  15,
                 error:  1,      /* Widget rcvd wr resp pkt w/ error */
-                ovflow: 5,      /* Overflow count. perf measurement */
+                ovflow: 5,      /* Overflow count. perf measurement */
                 fire_and_forget: 1, /* Launch Write without response */
                 mode:   2,      /* Widget operation Mode        */
                 rsvd2:  2,
                 bnakctr: 14,
-                rsvd3:  2,
+                rsvd3:  2,
                 anakctr: 14,
                 xtalkctr: 8;
         } iprb_fields_s;
@@ -838,13 +838,13 @@ typedef union iprb_u {
 
 #define iprb_regval     reg_value
 
-#define iprb_error      iprb_fields_s.error
-#define iprb_ovflow     iprb_fields_s.ovflow
-#define iprb_ff         iprb_fields_s.fire_and_forget
-#define iprb_mode       iprb_fields_s.mode
-#define iprb_bnakctr    iprb_fields_s.bnakctr
-#define iprb_anakctr    iprb_fields_s.anakctr
-#define iprb_xtalkctr   iprb_fields_s.xtalkctr
+#define iprb_error      iprb_fields_s.error
+#define iprb_ovflow     iprb_fields_s.ovflow
+#define iprb_ff         iprb_fields_s.fire_and_forget
+#define iprb_mode       iprb_fields_s.mode
+#define iprb_bnakctr    iprb_fields_s.bnakctr
+#define iprb_anakctr    iprb_fields_s.anakctr
+#define iprb_xtalkctr   iprb_fields_s.xtalkctr
 
 #endif /* !__ASSEMBLY__ */
 
@@ -853,10 +853,10 @@ typedef union iprb_u {
  * For details of the meanings of NAK and Accept, refer the PIO flow
  * document
  */
-#define IPRB_MODE_NORMAL        (0)
-#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
-#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
-#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+#define IPRB_MODE_NORMAL        (0)
+#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
 
 /*
  * IO CRB entry C_A to E_A : Partial (cache) CRBS
@@ -865,31 +865,31 @@ typedef union iprb_u {
 typedef union icrbp_a {
         u64   ip_reg;       /* the entire register value        */
         struct {
-             u64 error: 1,  /*    63, error occurred            */
-                ln_uce: 1,  /*    62: uncorrectable memory      */
-                ln_ae:  1,  /*    61: protection violation      */
-                ln_werr:1,  /*    60: write access error        */
-                ln_aerr:1,  /*    59: sn0net: Address error     */
-                ln_perr:1,  /*    58: sn0net: poison error      */
-                timeout:1,  /*    57: CRB timed out             */
-                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
-                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
-                c_err:  1,  /*    54: incoming xtalk req, err set*/
+             u64 error: 1,  /*    63, error occurred            */
+                ln_uce: 1,  /*    62: uncorrectable memory      */
+                ln_ae:  1,  /*    61: protection violation      */
+                ln_werr:1,  /*    60: write access error        */
+                ln_aerr:1,  /*    59: sn0net: Address error     */
+                ln_perr:1,  /*    58: sn0net: poison error      */
+                timeout:1,  /*    57: CRB timed out             */
+                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+                c_err:  1,  /*    54: incoming xtalk req, err set*/
                 rsvd1: 12,  /* 53-42: reserved                  */
-                valid:  1,  /*    41: Valid status              */
+                valid:  1,  /*    41: Valid status              */
                 sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
                 tnum:   5,  /* 36-32: TNUM of xtalk request     */
-                bo:     1,  /*    31: barrier op set in xtalk rqst*/
-                resprqd:1,  /*    30: xtalk rqst requires response*/
-                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+                bo:     1,  /*    31: barrier op set in xtalk rqst*/
+                resprqd:1,  /*    30: xtalk rqst requires response*/
+                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
                 size:   2,  /* 28-27: size of xtalk request     */
                 excl:   4,  /* 26-23: exclusive bit(s)          */
                 stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
-                intvn:  1,  /*    19: rqst target of intervention*/
-                resp:   1,  /*    18: Data response given to t5 */
-                ack:    1,  /*    17: Data ack received.        */
-                hold:   1,  /*    16: crb gathering invalidate acks*/
-                wb:     1,  /*    15: writeback pending.        */
+                intvn:  1,  /*    19: rqst target of intervention*/
+                resp:   1,  /*    18: Data response given to t5 */
+                ack:    1,  /*    17: Data ack received.        */
+                hold:   1,  /*    16: crb gathering invalidate acks*/
+                wb:     1,  /*    15: writeback pending.        */
                 ack_cnt:11, /* 14-04: counter of invalidate acks*/
                 tscaler:4;  /* 03-00: Timeout prescaler         */
         } ip_fmt;
@@ -908,13 +908,13 @@ typedef union hubii_idsr {
         u64 iin_reg;
         struct {
                 u64 rsvd1 : 35,
-                    isent : 1,
-                    rsvd2 : 3,
-                    ienable: 1,
-                    rsvd  : 7,
-                    node  : 9,
-                    rsvd4 : 1,
-                    level : 7;
+                    isent : 1,
+                    rsvd2 : 3,
+                    ienable: 1,
+                    rsvd  : 7,
+                    node  : 9,
+                    rsvd4 : 1,
+                    level : 7;
         } iin_fmt;
 } hubii_idsr_t;
 #endif /* !__ASSEMBLY__ */
@@ -966,7 +966,7 @@ typedef union hubii_idsr {
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */
-#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_CREDIT       3
 #define       HUBII_XBOW_REV2_CREDIT  4
 
 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
index 14c225d80664..305d002be182 100644
--- a/arch/mips/include/asm/sn/sn0/hubmd.h
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
@@ -8,16 +8,16 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_SN0_HUBMD_H
-#define _ASM_SN_SN0_HUBMD_H
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H
 
 
 /*
  * Hub Memory/Directory interface registers
  */
-#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
+#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
 
-#define MAX_REGIONS             64
+#define MAX_REGIONS             64
 
 /* Hardware page size and shift */
 
@@ -34,62 +34,62 @@
 #define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
 #define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
 #define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
-#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
-#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
-#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
-#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
-#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
-#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
-#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
-#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
-#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
+#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
 #define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
-#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
-#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
-#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
+#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
 #define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
 #define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
-#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
-#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
+#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
 #define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
 
-#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
-#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
-#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
-#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
-#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
-#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
-#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
-
-#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
-#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
-#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
-#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
-#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
-#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
-#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
-#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
 
 #define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
-#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
-#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
-
-#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
-#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
-#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
-#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
-#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
-#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
-#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
-#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
-#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
-#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
-#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
-#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
-#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
-#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
-#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
-#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
+#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
 
 #ifdef CONFIG_SGI_SN_N_MODE
 #define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
@@ -106,14 +106,14 @@
  *   Bits not used by the MD are used by software.
  */
 
-#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
 #define MD_SIZE_8MB             1
 #define MD_SIZE_16MB            2
 #define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
-#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
 #define MD_SIZE_256MB           6
-#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
 #define MD_SIZE_1GB             8
 #define MD_SIZE_2GB             9
 #define MD_SIZE_4GB             10
@@ -207,16 +207,16 @@
 
 /* MD_SLOTID_USTAT bit definitions */
 
-#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
 #define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
 #define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
-#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
+#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
 #define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
 #define MSU_CORECLK             (UINT64_CAST 1 << 6)
-#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
+#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
 #define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
 #define MSU_NETSYNC             (UINT64_CAST 1 << 5)
-#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
 #define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
 #define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
 #define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
@@ -228,8 +228,8 @@
 #define MSU_SN00_SLOTID_SHFT    7
 #define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
 
-#define MSU_PIMM_PSC_SHFT       4
-#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+#define MSU_PIMM_PSC_SHFT       4
+#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
 
 /* MD_MIG_DIFF_THRESH bit definitions */
 
@@ -260,7 +260,7 @@
 
 /* Other MD definitions */
 
-#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
+#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
 #define MD_BANK_MASK            (UINT64_CAST 7 << 29)
 #define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
 #define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
@@ -300,32 +300,32 @@
  * Format C:  STATE != shared (FINE must be 0)
  */
 
-#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
 #define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
 #define MD_PDIR_ECC_MASK        0x7f
-#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
+#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
 #define MD_PDIR_PRIO_MASK       (0xf << 8)
-#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
+#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
 #define MD_PDIR_AX_MASK         (1 << 7)
 #define MD_PDIR_AX              (1 << 7)
-#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
+#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
 #define MD_PDIR_FINE_MASK       (1 << 12)
 #define MD_PDIR_FINE            (1 << 12)
-#define MD_PDIR_OCT_SHFT        13                      /* A low            */
+#define MD_PDIR_OCT_SHFT        13                      /* A low            */
 #define MD_PDIR_OCT_MASK        (7 << 13)
-#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
+#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
 #define MD_PDIR_STATE_MASK      (7 << 13)
-#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
+#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
 #define MD_PDIR_ONECNT_MASK     (0x3f << 16)
-#define MD_PDIR_PTR_SHFT        22                      /* C low            */
+#define MD_PDIR_PTR_SHFT        22                      /* C low            */
 #define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
-#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
+#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
 #define MD_PDIR_VECMSB_BITMASK  0x3ffffff
 #define MD_PDIR_VECMSB_BITSHFT  27
 #define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
-#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
+#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
 #define MD_PDIR_CWOFF_MASK      (7 << 7)
-#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
+#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
 #define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
 #define MD_PDIR_VECLSB_BITSHFT  0
 #define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
@@ -349,25 +349,25 @@
  * Format C:  STATE != shared
  */
 
-#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
+#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
 #define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
 #define MD_SDIR_ECC_MASK        0x1f
-#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
+#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
 #define MD_SDIR_PRIO_MASK       (1 << 6)
-#define MD_SDIR_AX_SHFT         5                       /* AC low           */
+#define MD_SDIR_AX_SHFT         5                       /* AC low           */
 #define MD_SDIR_AX_MASK         (1 << 5)
 #define MD_SDIR_AX              (1 << 5)
-#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
+#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
 #define MD_SDIR_STATE_MASK      (7 << 7)
-#define MD_SDIR_PTR_SHFT        10                      /* C low            */
+#define MD_SDIR_PTR_SHFT        10                      /* C low            */
 #define MD_SDIR_PTR_MASK        (0x3f << 10)
-#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
+#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
 #define MD_SDIR_CWOFF_MASK      (7 << 5)
-#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
+#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
 #define MD_SDIR_VECMSB_BITMASK  0x1f
 #define MD_SDIR_VECMSB_BITSHFT  7
 #define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
-#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
+#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
 #define MD_SDIR_VECLSB_BITMASK  0x7ff
 #define MD_SDIR_VECLSB_BITSHFT  0
 #define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
@@ -390,7 +390,7 @@
 
 /* Premium SIMM protection entry shifts and masks. */
 
-#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
 #define MD_PPROT_MASK           7
 #define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
 #define MD_PPROT_MIGMD_MASK     (3 << 3)
@@ -403,7 +403,7 @@
 
 /* Standard SIMM protection entry shifts and masks. */
 
-#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
 #define MD_SPROT_MASK           7
 #define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
 #define MD_SPROT_MIGMD_MASK     (3 << 3)
@@ -431,13 +431,13 @@
 
 #define CPU_LED_ADDR(_nasid, _slice)                                       \
         (private.p_sn00 ?                                                  \
-         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
          REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
 
 #define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
         (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
 
-#define SET_MY_LEDS(_v)                                                    \
+#define SET_MY_LEDS(_v)                                                    \
         SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
 
 /*
@@ -541,7 +541,7 @@
  */
 
 struct dir_error_reg {
-        u64     uce_vld:   1,   /*    63: valid directory uce   */
+        u64     uce_vld:   1,   /*    63: valid directory uce   */
                 ae_vld:    1,   /*    62: valid dir prot ecc error */
                 ce_vld:    1,   /*    61: valid correctable ECC err*/
                 rsvd1:    19,   /* 60-42: reserved              */
@@ -555,13 +555,13 @@ struct dir_error_reg {
 };
 
 typedef union md_dir_error {
-        u64     derr_reg;       /* the entire register          */
+        u64     derr_reg;       /* the entire register          */
         struct dir_error_reg derr_fmt;  /* the register format          */
 } md_dir_error_t;
 
 
 struct mem_error_reg {
-        u64     uce_vld:   1,   /*    63: valid memory uce      */
+        u64     uce_vld:   1,   /*    63: valid memory uce      */
                 ce_vld:    1,   /*    62: valid correctable ECC err*/
                 rsvd1:    22,   /* 61-40: reserved              */
                 bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
@@ -573,8 +573,8 @@ struct mem_error_reg {
 
 
 typedef union md_mem_error {
-        u64     merr_reg;       /* the entire register          */
-        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+        u64     merr_reg;       /* the entire register          */
+        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
 } md_mem_error_t;
 
 
@@ -594,7 +594,7 @@ struct proto_error_reg {
 };
 
 typedef union md_proto_error {
-        u64     perr_reg;       /* the entire register          */
+        u64     perr_reg;       /* the entire register          */
         struct proto_error_reg  perr_fmt; /* format of the register     */
 } md_proto_error_t;
 
@@ -695,33 +695,33 @@ typedef union md_pdir_loent {
  *   represent directory memory information.
  */
 
-typedef union   md_dir_high     {
-        md_sdir_high_t  md_sdir_high;
-        md_pdir_high_t  md_pdir_high;
+typedef union   md_dir_high     {
+        md_sdir_high_t  md_sdir_high;
+        md_pdir_high_t  md_pdir_high;
 } md_dir_high_t;
 
-typedef union   md_dir_low      {
-        md_sdir_low_t   md_sdir_low;
-        md_pdir_low_t   md_pdir_low;
+typedef union   md_dir_low      {
+        md_sdir_low_t   md_sdir_low;
+        md_pdir_low_t   md_pdir_low;
 } md_dir_low_t;
 
-typedef struct  bddir_entry     {
-        md_dir_low_t    md_dir_low;
-        md_dir_high_t   md_dir_high;
+typedef struct  bddir_entry     {
+        md_dir_low_t    md_dir_low;
+        md_dir_high_t   md_dir_high;
 } bddir_entry_t;
 
 typedef struct  dir_mem_entry   {
-        u64             prcpf[MAX_REGIONS];
-        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+        u64             prcpf[MAX_REGIONS];
+        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
 } dir_mem_entry_t;
 
 
 
 typedef union md_perf_sel {
-        u64     perf_sel_reg;
+        u64     perf_sel_reg;
         struct  {
                 u64     perf_rsvd : 60,
-                        perf_en   :  1,
+                        perf_en   :  1,
                         perf_sel  :  3;
         } perf_sel_bits;
 } md_perf_sel_t;
@@ -730,7 +730,7 @@ typedef union md_perf_cnt {
         u64     perf_cnt;
         struct  {
                 u64     perf_rsvd : 44,
-                        perf_cnt  : 20;
+                        perf_cnt  : 20;
         } perf_cnt_bits;
 } md_perf_cnt_t;
 
diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
index b40d3ef97a12..b73c4bee65f2 100644
--- a/arch/mips/include/asm/sn/sn0/hubni.h
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
@@ -25,38 +25,38 @@
 #define NI_BASE_TABLES          0x630000
 
 #define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
-#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
+#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
 #define NI_PROTECTION           0x600010 /* NI register access permissions  */
-#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
+#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
 #define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
 #define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
 #define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
 
 #define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
-#define NI_VECTOR               0x600208 /* Vector PIO route                */
-#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
-#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
-#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
-#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
+#define NI_VECTOR               0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
 #define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
 
-#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
-#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
-
-#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
-#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
-#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
-#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
-#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
-#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
-#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
-#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
+#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
 #define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
 #define NI_AGE_REG_MAX          NI_AGE_IO_PIO
 
-#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
-#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
-#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
+#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
 
 #define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
 #define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
@@ -76,13 +76,13 @@
 #define NSRI_LINKUP_SHFT        29
 #define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
 #define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
-#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
 #define NSRI_MORENODES_SHFT     18
 #define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
 #define  MORE_MEMORY            0
 #define  MORE_NODES             1
 #define NSRI_REGIONSIZE_SHFT    17
-#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
+#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
 #define  REGIONSIZE_FINE        1
 #define  REGIONSIZE_COARSE      0
 #define NSRI_NODEID_SHFT        8
@@ -90,14 +90,14 @@
 #define NSRI_REV_SHFT           4
 #define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
 #define NSRI_CHIPID_SHFT        0
-#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
+#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
 
 /*
- * In fine mode, each node is a region.  In coarse mode, there are
+ * In fine mode, each node is a region.  In coarse mode, there are
  * eight nodes per region.
  */
 #define NASID_TO_FINEREG_SHFT   0
-#define NASID_TO_COARSEREG_SHFT 3
+#define NASID_TO_COARSEREG_SHFT 3
 
 /* NI_PORT_RESET mask definitions */
 
@@ -111,21 +111,21 @@
 
 /* NI_GLOBAL_PARMS mask and shift definitions */
 
-#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
+#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
 #define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
-#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
 #define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
 
-#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
 #define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
-#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
 #define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
 
 /* NI_DIAG_PARMS mask and shift definitions */
 
 #define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
 #define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
-#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
 #define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
 
 /*
@@ -137,7 +137,7 @@
 #define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
 #define NVP_WRITEID_SHFT        32
 #define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
-#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
 #define NVP_TYPE_SHFT           0
 #define NVP_TYPE_MASK           (UINT64_CAST 0x3)
 
@@ -151,7 +151,7 @@
 #define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
 #define NVS_WRITEID_SHFT        32
 #define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
-#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
 #define NVS_TYPE_SHFT           0
 #define NVS_TYPE_MASK           (UINT64_CAST 0x7)
 #define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
@@ -161,10 +161,10 @@
 #define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
-#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
-#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
-#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
-#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
 
 /* NI_AGE_XXX mask and shift definitions */
 
@@ -215,7 +215,7 @@
 
 #define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
                                  NPE_BADMESSAGE | NPE_BADDEST |         \
-                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
                                  NPE_TAILTO_MASK)
 
 /* NI_META_TABLE mask and shift definitions */
@@ -231,7 +231,7 @@
 typedef union   hubni_port_error_u {
         u64     nipe_reg_value;
         struct {
-            u64 nipe_rsvd:      26,     /* unused */
+            u64 nipe_rsvd:      26,     /* unused */
                 nipe_lnk_reset:  1,     /* link reset */
                 nipe_intl_err:   1,     /* internal error */
                 nipe_bad_msg:    1,     /* bad message */
diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
index e39f5f9da040..7b83655913c5 100644
--- a/arch/mips/include/asm/sn/sn0/hubpi.h
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_SN0_HUBPI_H
-#define _ASM_SN_SN0_HUBPI_H
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H
 
 #include <linux/types.h>
 
@@ -25,13 +25,13 @@
 
 /* General protection and control registers */
 
-#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
-#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
-#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
 #define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
-#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
-#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
-#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
+#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
 #define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
 
 /* CALIAS values */
@@ -54,28 +54,28 @@
 
 /* Processor control and status checking */
 
-#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
-#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
-#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
-#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
-#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
+#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
 #define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
-#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
-#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
+#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
 #define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
-#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
+#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
 
-/* Regular Interrupt register checking.  */
+/* Regular Interrupt register checking.  */
 
 #define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
-#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
-#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
-#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
-#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
-#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
-#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
+#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
 
-#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
+#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
 
 /* Crosscall interrupts */
 
@@ -83,49 +83,49 @@
 #define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
 #define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
 #define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
-#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
+#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
 
-#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
+#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
 
 /* Realtime Counter and Profiler control registers */
 
-#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
-#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
-#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
+#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
 #define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
-#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
-#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
+#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
 #define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
 #define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
-#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
-#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
-#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
-#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
-#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
+#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
 #define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
 
 #define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
 
 /* Built-In Self Test support */
 
-#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
-#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
-#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
-#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
-#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
-#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
-#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
+#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
 
 /* Graphics control registers */
 
-#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
-#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
-#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
+#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
 #define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
 #define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
-#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
-#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
-#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
+#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
 #define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
 #define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
 
@@ -138,24 +138,24 @@
 #define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
 #define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
 #define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
-#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
-#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
+#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
 #define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
-#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
 #define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
-#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
 #define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
-#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
 #define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
-#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
-#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
-#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
-#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
+#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
 #define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
-#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
-#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
-#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
-#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
+#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
 #define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
 #define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
 #define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
@@ -168,7 +168,7 @@
 #define PI_ERR_SPUR_MSG_A       0x00000008
 #define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
 #define PI_ERR_WRB_TERR_A       0x00000020
-#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
 #define PI_ERR_WRB_WERR_A       0x00000080
 #define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
 #define PI_ERR_SYSSTATE_A       0x00000200
@@ -196,32 +196,32 @@
  * The following three macros define all possible error int pends.
  */
 
-#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
-                                 PI_ERR_BAD_SPOOL_A     | \
-                                 PI_ERR_SYSCMD_ADDR_A   | \
-                                 PI_ERR_SYSCMD_DATA_A   | \
-                                 PI_ERR_SYSAD_ADDR_A    | \
+#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
+                                 PI_ERR_BAD_SPOOL_A     | \
+                                 PI_ERR_SYSCMD_ADDR_A   | \
+                                 PI_ERR_SYSCMD_DATA_A   | \
+                                 PI_ERR_SYSAD_ADDR_A    | \
                                  PI_ERR_SYSAD_DATA_A    | \
                                  PI_ERR_SYSSTATE_A)
 
-#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
-                                 PI_ERR_WRB_WERR_A      | \
-                                 PI_ERR_WRB_TERR_A      | \
-                                 PI_ERR_SPUR_MSG_A      | \
+#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
+                                 PI_ERR_WRB_WERR_A      | \
+                                 PI_ERR_WRB_TERR_A      | \
+                                 PI_ERR_SPUR_MSG_A      | \
                                  PI_ERR_SPOOL_CMP_A)
 
-#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
-                                 PI_ERR_BAD_SPOOL_B     | \
-                                 PI_ERR_SYSCMD_ADDR_B   | \
-                                 PI_ERR_SYSCMD_DATA_B   | \
-                                 PI_ERR_SYSAD_ADDR_B    | \
+#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
+                                 PI_ERR_BAD_SPOOL_B     | \
+                                 PI_ERR_SYSCMD_ADDR_B   | \
+                                 PI_ERR_SYSCMD_DATA_B   | \
+                                 PI_ERR_SYSAD_ADDR_B    | \
                                  PI_ERR_SYSAD_DATA_B    | \
                                  PI_ERR_SYSSTATE_B)
 
-#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
-                                 PI_ERR_WRB_WERR_B      | \
-                                 PI_ERR_WRB_TERR_B      | \
-                                 PI_ERR_SPUR_MSG_B      | \
+#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
+                                 PI_ERR_WRB_WERR_B      | \
+                                 PI_ERR_WRB_TERR_B      | \
+                                 PI_ERR_SPUR_MSG_B      | \
                                  PI_ERR_SPOOL_CMP_B)
 
 #define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
@@ -242,24 +242,24 @@
 #define PI_ERR_ST0_CMD_SHFT     17
 #define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
 #define PI_ERR_ST0_ADDR_SHFT    25
-#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
-#define PI_ERR_ST0_OVERRUN_SHFT 62
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62
 #define PI_ERR_ST0_VALID_MASK   0x8000000000000000
 #define PI_ERR_ST0_VALID_SHFT   63
 
 /* Fields in PI_ERR_STATUS1_[AB] */
 #define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
 #define PI_ERR_ST1_SPOOL_SHFT   0
-#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
-#define PI_ERR_ST1_TOUTCNT_SHFT 21
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21
 #define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
 #define PI_ERR_ST1_INVCNT_SHFT  29
 #define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
 #define PI_ERR_ST1_CRBNUM_SHFT  39
 #define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
 #define PI_ERR_ST1_WRBRRB_SHFT  42
-#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
-#define PI_ERR_ST1_CRBSTAT_SHFT 43
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43
 #define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
 #define PI_ERR_ST1_MSGSRC_SHFT  53
 
@@ -274,8 +274,8 @@
 #define PI_ERR_STK_CRBNUM_SHFT  9
 #define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
 #define PI_ERR_STK_WRBRRB_SHFT  12
-#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
-#define PI_ERR_STK_CRBSTAT_SHFT 13
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13
 #define PI_ERR_STK_CMD_MASK     0x000000007f800000
 #define PI_ERR_STK_CMD_SHFT     23
 #define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
@@ -364,11 +364,11 @@ typedef u64	rtc_time_t;
 
 /* Bits in PI_SYSAD_ERRCHK_EN */
 #define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
-#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
-#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
 #define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
 #define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
-#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
 #define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
 
 /* Interrupt pending bits on R10000 */
diff --git a/arch/mips/include/asm/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h
index 3c97e0855c8d..3b5efeefcc3f 100644
--- a/arch/mips/include/asm/sn/sn0/ip27.h
+++ b/arch/mips/include/asm/sn/sn0/ip27.h
@@ -21,14 +21,14 @@
 
 #ifndef __ASSEMBLY__
 
-#define CAUSE_BERRINTR          IE_IRQ5
+#define CAUSE_BERRINTR          IE_IRQ5
 
-#define ECCF_CACHE_ERR  0
-#define ECCF_TAGLO      1
-#define ECCF_ECC        2
-#define ECCF_ERROREPC   3
-#define ECCF_PADDR      4
-#define ECCF_SIZE       (5 * sizeof(long))
+#define ECCF_CACHE_ERR  0
+#define ECCF_TAGLO      1
+#define ECCF_ECC        2
+#define ECCF_ERROREPC   3
+#define ECCF_PADDR      4
+#define ECCF_SIZE       (5 * sizeof(long))
 
 #endif /* !__ASSEMBLY__ */
 
@@ -39,8 +39,8 @@
  * the processor number of the calling processor.  The proc parameters
  * must be a register.
  */
-#define KL_GET_CPUNUM(proc)                             \
-        dli     proc, LOCAL_HUB(0);                     \
+#define KL_GET_CPUNUM(proc)                             \
+        dli     proc, LOCAL_HUB(0);                     \
         ld      proc, PI_CPU_NUM(proc)
 
 #endif /* __ASSEMBLY__ */
@@ -71,15 +71,15 @@
 
 #define NUM_CAUSE_INTRS         8
 
-#define SCACHE_LINESIZE 128
-#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
+#define SCACHE_LINESIZE 128
+#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
 
 #include <asm/sn/addrs.h>
 
-#define LED_CYCLE_MASK  0x0f
-#define LED_CYCLE_SHFT  4
+#define LED_CYCLE_MASK  0x0f
+#define LED_CYCLE_SHFT  4
 
 #define SEND_NMI(_nasid, _slice)        \
-          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
 
 #endif /* _ASM_SN_SN0_IP27_H */
diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
index 74d0bb260b86..c4813d67aec3 100644
--- a/arch/mips/include/asm/sn/types.h
+++ b/arch/mips/include/asm/sn/types.h
@@ -11,7 +11,7 @@
 
 #include <linux/types.h>
 
-typedef unsigned long   cpuid_t;
+typedef unsigned long   cpuid_t;
 typedef unsigned long   cnodemask_t;
 typedef signed short    nasid_t;        /* node id in numa-as-id space */
 typedef signed short    cnodeid_t;      /* node id in compact-id space */
@@ -19,7 +19,7 @@ typedef signed char	partid_t;	/* partition ID type */
 typedef signed short    moduleid_t;     /* user-visible module number type */
 typedef signed short    cmoduleid_t;    /* kernel compact module id type */
 typedef unsigned char   clusterid_t;    /* Clusterid of the cell */
-typedef unsigned long   pfn_t;
+typedef unsigned long   pfn_t;
 
 typedef dev_t           vertex_hdl_t;   /* hardware graph vertex handle */