diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2008-09-16 13:48:51 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 11:18:52 -0400 |
| commit | 384740dc49ea651ba350704d13ff6be9976e37fe (patch) | |
| tree | a6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/sibyte | |
| parent | e8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff) | |
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/sibyte')
24 files changed, 8721 insertions, 0 deletions
diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h new file mode 100644 index 000000000000..6109557c14e9 --- /dev/null +++ b/arch/mips/include/asm/sibyte/bcm1480_int.h | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Interrupt Mapper definitions File: bcm1480_int.h | ||
| 5 | * | ||
| 6 | * This module contains constants for manipulating the | ||
| 7 | * BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and | ||
| 8 | * definitions for the interrupt sources. | ||
| 9 | * | ||
| 10 | * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) | ||
| 11 | * | ||
| 12 | ********************************************************************* | ||
| 13 | * | ||
| 14 | * Copyright 2000,2001,2002,2003 | ||
| 15 | * Broadcom Corporation. All rights reserved. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or | ||
| 18 | * modify it under the terms of the GNU General Public License as | ||
| 19 | * published by the Free Software Foundation; either version 2 of | ||
| 20 | * the License, or (at your option) any later version. | ||
| 21 | * | ||
| 22 | * This program is distributed in the hope that it will be useful, | ||
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 25 | * GNU General Public License for more details. | ||
| 26 | * | ||
| 27 | * You should have received a copy of the GNU General Public License | ||
| 28 | * along with this program; if not, write to the Free Software | ||
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 30 | * MA 02111-1307 USA | ||
| 31 | ********************************************************************* */ | ||
| 32 | |||
| 33 | |||
| 34 | #ifndef _BCM1480_INT_H | ||
| 35 | #define _BCM1480_INT_H | ||
| 36 | |||
| 37 | #include "sb1250_defs.h" | ||
| 38 | |||
| 39 | /* ********************************************************************* | ||
| 40 | * Interrupt Mapper Constants | ||
| 41 | ********************************************************************* */ | ||
| 42 | |||
| 43 | /* | ||
| 44 | * The interrupt mapper deals with 128-bit logical registers that are | ||
| 45 | * implemented as pairs of 64-bit registers, with the "low" 64 bits in | ||
| 46 | * a register that has an address 0x1000 higher(!) than the | ||
| 47 | * corresponding "high" register. | ||
| 48 | * | ||
| 49 | * For appropriate registers, bit 0 of the "high" register is a | ||
| 50 | * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low" | ||
| 51 | * register. | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * This entire file uses _BCM1480_ in all the symbols because it is | ||
| 56 | * entirely BCM1480 specific. | ||
| 57 | */ | ||
| 58 | |||
| 59 | /* | ||
| 60 | * Interrupt sources (Table 22) | ||
| 61 | */ | ||
| 62 | |||
| 63 | #define K_BCM1480_INT_SOURCES 128 | ||
| 64 | |||
| 65 | #define _BCM1480_INT_HIGH(k) (k) | ||
| 66 | #define _BCM1480_INT_LOW(k) ((k)+64) | ||
| 67 | |||
| 68 | #define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1) | ||
| 69 | #define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4) | ||
| 70 | #define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5) | ||
| 71 | #define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6) | ||
| 72 | #define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7) | ||
| 73 | #define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8) | ||
| 74 | #define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9) | ||
| 75 | #define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10) | ||
| 76 | #define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11) | ||
| 77 | #define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12) | ||
| 78 | #define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13) | ||
| 79 | #define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14) | ||
| 80 | #define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15) | ||
| 81 | #define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20) | ||
| 82 | #define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21) | ||
| 83 | #define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22) | ||
| 84 | #define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23) | ||
| 85 | #define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28) | ||
| 86 | #define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29) | ||
| 87 | #define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30) | ||
| 88 | #define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31) | ||
| 89 | #define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36) | ||
| 90 | #define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37) | ||
| 91 | #define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38) | ||
| 92 | #define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39) | ||
| 93 | #define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40) | ||
| 94 | #define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41) | ||
| 95 | #define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42) | ||
| 96 | #define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43) | ||
| 97 | #define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52) | ||
| 98 | #define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53) | ||
| 99 | #define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54) | ||
| 100 | #define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55) | ||
| 101 | #define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56) | ||
| 102 | #define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57) | ||
| 103 | #define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58) | ||
| 104 | #define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59) | ||
| 105 | #define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60) | ||
| 106 | #define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61) | ||
| 107 | #define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62) | ||
| 108 | #define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63) | ||
| 109 | |||
| 110 | #define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1) | ||
| 111 | #define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2) | ||
| 112 | #define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3) | ||
| 113 | #define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4) | ||
| 114 | #define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5) | ||
| 115 | #define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6) | ||
| 116 | #define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7) | ||
| 117 | #define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8) | ||
| 118 | #define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9) | ||
| 119 | #define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10) | ||
| 120 | #define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11) | ||
| 121 | #define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16) | ||
| 122 | #define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17) | ||
| 123 | #define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18) | ||
| 124 | #define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19) | ||
| 125 | #define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20) | ||
| 126 | #define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21) | ||
| 127 | #define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22) | ||
| 128 | #define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23) | ||
| 129 | #define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24) | ||
| 130 | #define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25) | ||
| 131 | #define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32) | ||
| 132 | #define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33) | ||
| 133 | #define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34) | ||
| 134 | #define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35) | ||
| 135 | #define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36) | ||
| 136 | #define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40) | ||
| 137 | #define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41) | ||
| 138 | #define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42) | ||
| 139 | #define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44) | ||
| 140 | #define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45) | ||
| 141 | #define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46) | ||
| 142 | #define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47) | ||
| 143 | #define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52) | ||
| 144 | #define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53) | ||
| 145 | #define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54) | ||
| 146 | #define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55) | ||
| 147 | #define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56) | ||
| 148 | #define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57) | ||
| 149 | #define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58) | ||
| 150 | #define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59) | ||
| 151 | #define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60) | ||
| 152 | #define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61) | ||
| 153 | #define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62) | ||
| 154 | #define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63) | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Mask values for each interrupt | ||
| 158 | */ | ||
| 159 | |||
| 160 | #define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F)) | ||
| 161 | #define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F)) | ||
| 162 | #define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6) | ||
| 163 | |||
| 164 | #define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0)) | ||
| 165 | |||
| 166 | #define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP) | ||
| 167 | #define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0) | ||
| 168 | #define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1) | ||
| 169 | #define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2) | ||
| 170 | #define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3) | ||
| 171 | #define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA) | ||
| 172 | #define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB) | ||
| 173 | #define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC) | ||
| 174 | #define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD) | ||
| 175 | #define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0) | ||
| 176 | #define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1) | ||
| 177 | #define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2) | ||
| 178 | #define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3) | ||
| 179 | #define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0) | ||
| 180 | #define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1) | ||
| 181 | #define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2) | ||
| 182 | #define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3) | ||
| 183 | #define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0) | ||
| 184 | #define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1) | ||
| 185 | #define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2) | ||
| 186 | #define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3) | ||
| 187 | #define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0) | ||
| 188 | #define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1) | ||
| 189 | #define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1) | ||
| 190 | #define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1) | ||
| 191 | #define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2) | ||
| 192 | #define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1) | ||
| 193 | #define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3) | ||
| 194 | #define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1) | ||
| 195 | #define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW) | ||
| 196 | #define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH) | ||
| 197 | #define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW) | ||
| 198 | #define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH) | ||
| 199 | #define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0) | ||
| 200 | #define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0) | ||
| 201 | #define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1) | ||
| 202 | #define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2) | ||
| 203 | #define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3) | ||
| 204 | #define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0) | ||
| 205 | #define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1) | ||
| 206 | #define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2) | ||
| 207 | #define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3) | ||
| 208 | #define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC) | ||
| 209 | #define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC) | ||
| 210 | #define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS) | ||
| 211 | #define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT) | ||
| 212 | #define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT) | ||
| 213 | #define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE) | ||
| 214 | #define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE) | ||
| 215 | #define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0) | ||
| 216 | #define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1) | ||
| 217 | #define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2) | ||
| 218 | #define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3) | ||
| 219 | #define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR) | ||
| 220 | #define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET) | ||
| 221 | #define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER) | ||
| 222 | #define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE) | ||
| 223 | #define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL) | ||
| 224 | #define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL) | ||
| 225 | #define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL) | ||
| 226 | #define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL) | ||
| 227 | #define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL) | ||
| 228 | #define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL) | ||
| 229 | #define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI) | ||
| 230 | #define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI) | ||
| 231 | #define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT) | ||
| 232 | #define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP) | ||
| 233 | #define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT) | ||
| 234 | #define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0) | ||
| 235 | #define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1) | ||
| 236 | #define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA) | ||
| 237 | #define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0) | ||
| 238 | #define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1) | ||
| 239 | #define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2) | ||
| 240 | #define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3) | ||
| 241 | #define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4) | ||
| 242 | #define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5) | ||
| 243 | #define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6) | ||
| 244 | #define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7) | ||
| 245 | #define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8) | ||
| 246 | #define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9) | ||
| 247 | #define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10) | ||
| 248 | #define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11) | ||
| 249 | #define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12) | ||
| 250 | #define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13) | ||
| 251 | #define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14) | ||
| 252 | #define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15) | ||
| 253 | |||
| 254 | /* | ||
| 255 | * Interrupt mappings (Table 18) | ||
| 256 | */ | ||
| 257 | |||
| 258 | #define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */ | ||
| 259 | #define K_BCM1480_INT_MAP_I1 1 | ||
| 260 | #define K_BCM1480_INT_MAP_I2 2 | ||
| 261 | #define K_BCM1480_INT_MAP_I3 3 | ||
| 262 | #define K_BCM1480_INT_MAP_I4 4 | ||
| 263 | #define K_BCM1480_INT_MAP_I5 5 | ||
| 264 | #define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */ | ||
| 265 | #define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */ | ||
| 266 | |||
| 267 | /* | ||
| 268 | * Interrupt LDT Set Register (Table 19) | ||
| 269 | */ | ||
| 270 | |||
| 271 | #define S_BCM1480_INT_HT_INTMSG 0 | ||
| 272 | #define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG) | ||
| 273 | #define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG) | ||
| 274 | #define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG) | ||
| 275 | |||
| 276 | #define K_BCM1480_INT_HT_INTMSG_FIXED 0 | ||
| 277 | #define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1 | ||
| 278 | #define K_BCM1480_INT_HT_INTMSG_SMI 2 | ||
| 279 | #define K_BCM1480_INT_HT_INTMSG_NMI 3 | ||
| 280 | #define K_BCM1480_INT_HT_INTMSG_INIT 4 | ||
| 281 | #define K_BCM1480_INT_HT_INTMSG_STARTUP 5 | ||
| 282 | #define K_BCM1480_INT_HT_INTMSG_EXTINT 6 | ||
| 283 | #define K_BCM1480_INT_HT_INTMSG_RESERVED 7 | ||
| 284 | |||
| 285 | #define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3) | ||
| 286 | #define V_BCM1480_INT_HT_EDGETRIGGER 0 | ||
| 287 | #define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE | ||
| 288 | |||
| 289 | #define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4) | ||
| 290 | #define V_BCM1480_INT_HT_PHYSICALDEST 0 | ||
| 291 | #define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE | ||
| 292 | |||
| 293 | #define S_BCM1480_INT_HT_INTDEST 5 | ||
| 294 | #define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST) | ||
| 295 | #define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST) | ||
| 296 | #define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST) | ||
| 297 | |||
| 298 | #define S_BCM1480_INT_HT_VECTOR 13 | ||
| 299 | #define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR) | ||
| 300 | #define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR) | ||
| 301 | #define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR) | ||
| 302 | |||
| 303 | /* | ||
| 304 | * Vector prefix (Table 4-7) | ||
| 305 | */ | ||
| 306 | |||
| 307 | #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00 | ||
| 308 | #define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40 | ||
| 309 | #define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80 | ||
| 310 | #define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0 | ||
| 311 | |||
| 312 | #endif /* _BCM1480_INT_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h new file mode 100644 index 000000000000..fd75817f7ac4 --- /dev/null +++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h | |||
| @@ -0,0 +1,176 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * L2 Cache constants and macros File: bcm1480_l2c.h | ||
| 5 | * | ||
| 6 | * This module contains constants useful for manipulating the | ||
| 7 | * level 2 cache. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1280-UM100-D2 (11/14/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _BCM1480_L2C_H | ||
| 34 | #define _BCM1480_L2C_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Format of level 2 cache management address (Table 55) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_BCM1480_L2C_MGMT_INDEX 5 | ||
| 43 | #define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX) | ||
| 44 | #define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX) | ||
| 45 | #define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX) | ||
| 46 | |||
| 47 | #define S_BCM1480_L2C_MGMT_WAY 17 | ||
| 48 | #define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY) | ||
| 49 | #define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY) | ||
| 50 | #define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY) | ||
| 51 | |||
| 52 | #define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20) | ||
| 53 | #define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21) | ||
| 54 | |||
| 55 | #define S_BCM1480_L2C_MGMT_ECC_DIAG 22 | ||
| 56 | #define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 57 | #define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 58 | #define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG) | ||
| 59 | |||
| 60 | #define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000 | ||
| 61 | |||
| 62 | #define BCM1480_L2C_ENTRIES_PER_WAY 4096 | ||
| 63 | #define BCM1480_L2C_NUM_WAYS 8 | ||
| 64 | |||
| 65 | |||
| 66 | /* | ||
| 67 | * Level 2 Cache Tag register (Table 59) | ||
| 68 | */ | ||
| 69 | |||
| 70 | #define S_BCM1480_L2C_TAG_MBZ 0 | ||
| 71 | #define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ) | ||
| 72 | |||
| 73 | #define S_BCM1480_L2C_TAG_INDEX 5 | ||
| 74 | #define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX) | ||
| 75 | #define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX) | ||
| 76 | #define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX) | ||
| 77 | |||
| 78 | /* Note that index bit 16 is also tag bit 40 */ | ||
| 79 | #define S_BCM1480_L2C_TAG_TAG 17 | ||
| 80 | #define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG) | ||
| 81 | #define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG) | ||
| 82 | #define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG) | ||
| 83 | |||
| 84 | #define S_BCM1480_L2C_TAG_ECC 40 | ||
| 85 | #define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC) | ||
| 86 | #define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC) | ||
| 87 | #define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC) | ||
| 88 | |||
| 89 | #define S_BCM1480_L2C_TAG_WAY 46 | ||
| 90 | #define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY) | ||
| 91 | #define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY) | ||
| 92 | #define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY) | ||
| 93 | |||
| 94 | #define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49) | ||
| 95 | #define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50) | ||
| 96 | |||
| 97 | #define S_BCM1480_L2C_DATA_ECC 51 | ||
| 98 | #define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC) | ||
| 99 | #define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC) | ||
| 100 | #define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * L2 Misc0 Value Register (Table 60) | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define S_BCM1480_L2C_MISC0_WAY_REMOTE 0 | ||
| 108 | #define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE) | ||
| 109 | #define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE) | ||
| 110 | |||
| 111 | #define S_BCM1480_L2C_MISC0_WAY_LOCAL 8 | ||
| 112 | #define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL) | ||
| 113 | #define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL) | ||
| 114 | |||
| 115 | #define S_BCM1480_L2C_MISC0_WAY_ENABLE 16 | ||
| 116 | #define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE) | ||
| 117 | #define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE) | ||
| 118 | |||
| 119 | #define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24 | ||
| 120 | #define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE) | ||
| 121 | #define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE) | ||
| 122 | |||
| 123 | #define S_BCM1480_L2C_MISC0_CACHE_QUAD 26 | ||
| 124 | #define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD) | ||
| 125 | #define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD) | ||
| 126 | |||
| 127 | #define S_BCM1480_L2C_MISC0_MC_PRIORITY 30 | ||
| 128 | #define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY) | ||
| 129 | |||
| 130 | #define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31 | ||
| 131 | #define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP) | ||
| 132 | |||
| 133 | |||
| 134 | /* | ||
| 135 | * L2 Misc1 Value Register (Table 60) | ||
| 136 | */ | ||
| 137 | |||
| 138 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0 | ||
| 139 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0) | ||
| 140 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0) | ||
| 141 | |||
| 142 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8 | ||
| 143 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1) | ||
| 144 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1) | ||
| 145 | |||
| 146 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16 | ||
| 147 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2) | ||
| 148 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2) | ||
| 149 | |||
| 150 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24 | ||
| 151 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3) | ||
| 152 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3) | ||
| 153 | |||
| 154 | #define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32 | ||
| 155 | #define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4) | ||
| 156 | #define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4) | ||
| 157 | |||
| 158 | |||
| 159 | /* | ||
| 160 | * L2 Misc2 Value Register (Table 60) | ||
| 161 | */ | ||
| 162 | |||
| 163 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0 | ||
| 164 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8) | ||
| 165 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8) | ||
| 166 | |||
| 167 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8 | ||
| 168 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9) | ||
| 169 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9) | ||
| 170 | |||
| 171 | #define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16 | ||
| 172 | #define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A) | ||
| 173 | #define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A) | ||
| 174 | |||
| 175 | |||
| 176 | #endif /* _BCM1480_L2C_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h new file mode 100644 index 000000000000..f26a41a82b59 --- /dev/null +++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h | |||
| @@ -0,0 +1,984 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Memory Controller constants File: bcm1480_mc.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * programming the memory controller. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _BCM1480_MC_H | ||
| 34 | #define _BCM1480_MC_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Memory Channel Configuration Register (Table 81) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_BCM1480_MC_INTLV0 0 | ||
| 43 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) | ||
| 44 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) | ||
| 45 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) | ||
| 46 | #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) | ||
| 47 | |||
| 48 | #define S_BCM1480_MC_INTLV1 8 | ||
| 49 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) | ||
| 50 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) | ||
| 51 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) | ||
| 52 | #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) | ||
| 53 | |||
| 54 | #define S_BCM1480_MC_INTLV2 16 | ||
| 55 | #define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) | ||
| 56 | #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) | ||
| 57 | #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) | ||
| 58 | #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) | ||
| 59 | |||
| 60 | #define S_BCM1480_MC_CS_MODE 32 | ||
| 61 | #define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) | ||
| 62 | #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) | ||
| 63 | #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) | ||
| 64 | #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) | ||
| 65 | |||
| 66 | #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ | ||
| 67 | V_BCM1480_MC_INTLV1_DEFAULT | \ | ||
| 68 | V_BCM1480_MC_INTLV2_DEFAULT | \ | ||
| 69 | V_BCM1480_MC_CS_MODE_DEFAULT) | ||
| 70 | |||
| 71 | #define K_BCM1480_MC_CS01_MODE 0x03 | ||
| 72 | #define K_BCM1480_MC_CS02_MODE 0x05 | ||
| 73 | #define K_BCM1480_MC_CS0123_MODE 0x0F | ||
| 74 | #define K_BCM1480_MC_CS0246_MODE 0x55 | ||
| 75 | #define K_BCM1480_MC_CS0145_MODE 0x33 | ||
| 76 | #define K_BCM1480_MC_CS0167_MODE 0xC3 | ||
| 77 | #define K_BCM1480_MC_CSFULL_MODE 0xFF | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Chip Select Start Address Register (Table 82) | ||
| 81 | */ | ||
| 82 | |||
| 83 | #define S_BCM1480_MC_CS0_START 0 | ||
| 84 | #define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) | ||
| 85 | #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) | ||
| 86 | #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) | ||
| 87 | |||
| 88 | #define S_BCM1480_MC_CS1_START 16 | ||
| 89 | #define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) | ||
| 90 | #define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) | ||
| 91 | #define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) | ||
| 92 | |||
| 93 | #define S_BCM1480_MC_CS2_START 32 | ||
| 94 | #define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) | ||
| 95 | #define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) | ||
| 96 | #define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) | ||
| 97 | |||
| 98 | #define S_BCM1480_MC_CS3_START 48 | ||
| 99 | #define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) | ||
| 100 | #define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) | ||
| 101 | #define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Chip Select End Address Register (Table 83) | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define S_BCM1480_MC_CS0_END 0 | ||
| 108 | #define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) | ||
| 109 | #define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) | ||
| 110 | #define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) | ||
| 111 | |||
| 112 | #define S_BCM1480_MC_CS1_END 16 | ||
| 113 | #define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) | ||
| 114 | #define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) | ||
| 115 | #define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) | ||
| 116 | |||
| 117 | #define S_BCM1480_MC_CS2_END 32 | ||
| 118 | #define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) | ||
| 119 | #define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) | ||
| 120 | #define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) | ||
| 121 | |||
| 122 | #define S_BCM1480_MC_CS3_END 48 | ||
| 123 | #define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) | ||
| 124 | #define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) | ||
| 125 | #define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) | ||
| 126 | |||
| 127 | /* | ||
| 128 | * Row Address Bit Select Register 0 (Table 84) | ||
| 129 | */ | ||
| 130 | |||
| 131 | #define S_BCM1480_MC_ROW00 0 | ||
| 132 | #define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) | ||
| 133 | #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) | ||
| 134 | #define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) | ||
| 135 | |||
| 136 | #define S_BCM1480_MC_ROW01 8 | ||
| 137 | #define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) | ||
| 138 | #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) | ||
| 139 | #define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) | ||
| 140 | |||
| 141 | #define S_BCM1480_MC_ROW02 16 | ||
| 142 | #define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) | ||
| 143 | #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) | ||
| 144 | #define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) | ||
| 145 | |||
| 146 | #define S_BCM1480_MC_ROW03 24 | ||
| 147 | #define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) | ||
| 148 | #define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) | ||
| 149 | #define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) | ||
| 150 | |||
| 151 | #define S_BCM1480_MC_ROW04 32 | ||
| 152 | #define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) | ||
| 153 | #define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) | ||
| 154 | #define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) | ||
| 155 | |||
| 156 | #define S_BCM1480_MC_ROW05 40 | ||
| 157 | #define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) | ||
| 158 | #define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) | ||
| 159 | #define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) | ||
| 160 | |||
| 161 | #define S_BCM1480_MC_ROW06 48 | ||
| 162 | #define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) | ||
| 163 | #define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) | ||
| 164 | #define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) | ||
| 165 | |||
| 166 | #define S_BCM1480_MC_ROW07 56 | ||
| 167 | #define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) | ||
| 168 | #define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) | ||
| 169 | #define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Row Address Bit Select Register 1 (Table 85) | ||
| 173 | */ | ||
| 174 | |||
| 175 | #define S_BCM1480_MC_ROW08 0 | ||
| 176 | #define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) | ||
| 177 | #define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) | ||
| 178 | #define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) | ||
| 179 | |||
| 180 | #define S_BCM1480_MC_ROW09 8 | ||
| 181 | #define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) | ||
| 182 | #define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) | ||
| 183 | #define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) | ||
| 184 | |||
| 185 | #define S_BCM1480_MC_ROW10 16 | ||
| 186 | #define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) | ||
| 187 | #define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) | ||
| 188 | #define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) | ||
| 189 | |||
| 190 | #define S_BCM1480_MC_ROW11 24 | ||
| 191 | #define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) | ||
| 192 | #define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) | ||
| 193 | #define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) | ||
| 194 | |||
| 195 | #define S_BCM1480_MC_ROW12 32 | ||
| 196 | #define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) | ||
| 197 | #define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) | ||
| 198 | #define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) | ||
| 199 | |||
| 200 | #define S_BCM1480_MC_ROW13 40 | ||
| 201 | #define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) | ||
| 202 | #define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) | ||
| 203 | #define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) | ||
| 204 | |||
| 205 | #define S_BCM1480_MC_ROW14 48 | ||
| 206 | #define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) | ||
| 207 | #define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) | ||
| 208 | #define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) | ||
| 209 | |||
| 210 | #define K_BCM1480_MC_ROWX_BIT_SPACING 8 | ||
| 211 | |||
| 212 | /* | ||
| 213 | * Column Address Bit Select Register 0 (Table 86) | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define S_BCM1480_MC_COL00 0 | ||
| 217 | #define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) | ||
| 218 | #define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) | ||
| 219 | #define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) | ||
| 220 | |||
| 221 | #define S_BCM1480_MC_COL01 8 | ||
| 222 | #define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) | ||
| 223 | #define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) | ||
| 224 | #define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) | ||
| 225 | |||
| 226 | #define S_BCM1480_MC_COL02 16 | ||
| 227 | #define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) | ||
| 228 | #define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) | ||
| 229 | #define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) | ||
| 230 | |||
| 231 | #define S_BCM1480_MC_COL03 24 | ||
| 232 | #define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) | ||
| 233 | #define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) | ||
| 234 | #define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) | ||
| 235 | |||
| 236 | #define S_BCM1480_MC_COL04 32 | ||
| 237 | #define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) | ||
| 238 | #define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) | ||
| 239 | #define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) | ||
| 240 | |||
| 241 | #define S_BCM1480_MC_COL05 40 | ||
| 242 | #define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) | ||
| 243 | #define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) | ||
| 244 | #define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) | ||
| 245 | |||
| 246 | #define S_BCM1480_MC_COL06 48 | ||
| 247 | #define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) | ||
| 248 | #define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) | ||
| 249 | #define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) | ||
| 250 | |||
| 251 | #define S_BCM1480_MC_COL07 56 | ||
| 252 | #define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) | ||
| 253 | #define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) | ||
| 254 | #define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) | ||
| 255 | |||
| 256 | /* | ||
| 257 | * Column Address Bit Select Register 1 (Table 87) | ||
| 258 | */ | ||
| 259 | |||
| 260 | #define S_BCM1480_MC_COL08 0 | ||
| 261 | #define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) | ||
| 262 | #define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) | ||
| 263 | #define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) | ||
| 264 | |||
| 265 | #define S_BCM1480_MC_COL09 8 | ||
| 266 | #define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) | ||
| 267 | #define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) | ||
| 268 | #define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) | ||
| 269 | |||
| 270 | #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ | ||
| 271 | |||
| 272 | #define S_BCM1480_MC_COL11 24 | ||
| 273 | #define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) | ||
| 274 | #define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) | ||
| 275 | #define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) | ||
| 276 | |||
| 277 | #define S_BCM1480_MC_COL12 32 | ||
| 278 | #define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) | ||
| 279 | #define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) | ||
| 280 | #define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) | ||
| 281 | |||
| 282 | #define S_BCM1480_MC_COL13 40 | ||
| 283 | #define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) | ||
| 284 | #define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) | ||
| 285 | #define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) | ||
| 286 | |||
| 287 | #define S_BCM1480_MC_COL14 48 | ||
| 288 | #define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) | ||
| 289 | #define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) | ||
| 290 | #define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) | ||
| 291 | |||
| 292 | #define K_BCM1480_MC_COLX_BIT_SPACING 8 | ||
| 293 | |||
| 294 | /* | ||
| 295 | * CS0 and CS1 Bank Address Bit Select Register (Table 88) | ||
| 296 | */ | ||
| 297 | |||
| 298 | #define S_BCM1480_MC_CS01_BANK0 0 | ||
| 299 | #define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) | ||
| 300 | #define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) | ||
| 301 | #define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) | ||
| 302 | |||
| 303 | #define S_BCM1480_MC_CS01_BANK1 8 | ||
| 304 | #define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) | ||
| 305 | #define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) | ||
| 306 | #define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) | ||
| 307 | |||
| 308 | #define S_BCM1480_MC_CS01_BANK2 16 | ||
| 309 | #define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) | ||
| 310 | #define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) | ||
| 311 | #define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) | ||
| 312 | |||
| 313 | /* | ||
| 314 | * CS2 and CS3 Bank Address Bit Select Register (Table 89) | ||
| 315 | */ | ||
| 316 | |||
| 317 | #define S_BCM1480_MC_CS23_BANK0 0 | ||
| 318 | #define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) | ||
| 319 | #define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) | ||
| 320 | #define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) | ||
| 321 | |||
| 322 | #define S_BCM1480_MC_CS23_BANK1 8 | ||
| 323 | #define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) | ||
| 324 | #define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) | ||
| 325 | #define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) | ||
| 326 | |||
| 327 | #define S_BCM1480_MC_CS23_BANK2 16 | ||
| 328 | #define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) | ||
| 329 | #define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) | ||
| 330 | #define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) | ||
| 331 | |||
| 332 | #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 | ||
| 333 | |||
| 334 | /* | ||
| 335 | * DRAM Command Register (Table 90) | ||
| 336 | */ | ||
| 337 | |||
| 338 | #define S_BCM1480_MC_COMMAND 0 | ||
| 339 | #define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) | ||
| 340 | #define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) | ||
| 341 | #define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) | ||
| 342 | |||
| 343 | #define K_BCM1480_MC_COMMAND_EMRS 0 | ||
| 344 | #define K_BCM1480_MC_COMMAND_MRS 1 | ||
| 345 | #define K_BCM1480_MC_COMMAND_PRE 2 | ||
| 346 | #define K_BCM1480_MC_COMMAND_AR 3 | ||
| 347 | #define K_BCM1480_MC_COMMAND_SETRFSH 4 | ||
| 348 | #define K_BCM1480_MC_COMMAND_CLRRFSH 5 | ||
| 349 | #define K_BCM1480_MC_COMMAND_SETPWRDN 6 | ||
| 350 | #define K_BCM1480_MC_COMMAND_CLRPWRDN 7 | ||
| 351 | |||
| 352 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 353 | #define K_BCM1480_MC_COMMAND_EMRS2 8 | ||
| 354 | #define K_BCM1480_MC_COMMAND_EMRS3 9 | ||
| 355 | #define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 | ||
| 356 | #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 | ||
| 357 | #endif | ||
| 358 | |||
| 359 | #define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) | ||
| 360 | #define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) | ||
| 361 | #define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) | ||
| 362 | #define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) | ||
| 363 | #define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) | ||
| 364 | #define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) | ||
| 365 | #define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) | ||
| 366 | #define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) | ||
| 367 | |||
| 368 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 369 | #define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) | ||
| 370 | #define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) | ||
| 371 | #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) | ||
| 372 | #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) | ||
| 373 | #endif | ||
| 374 | |||
| 375 | #define S_BCM1480_MC_CS0 4 | ||
| 376 | #define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) | ||
| 377 | #define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) | ||
| 378 | #define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) | ||
| 379 | #define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) | ||
| 380 | #define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) | ||
| 381 | #define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) | ||
| 382 | #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) | ||
| 383 | #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) | ||
| 384 | |||
| 385 | #define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) | ||
| 386 | #define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) | ||
| 387 | #define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) | ||
| 388 | |||
| 389 | #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) | ||
| 390 | |||
| 391 | /* | ||
| 392 | * DRAM Mode Register (Table 91) | ||
| 393 | */ | ||
| 394 | |||
| 395 | #define S_BCM1480_MC_EMODE 0 | ||
| 396 | #define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) | ||
| 397 | #define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) | ||
| 398 | #define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) | ||
| 399 | #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) | ||
| 400 | |||
| 401 | #define S_BCM1480_MC_MODE 16 | ||
| 402 | #define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) | ||
| 403 | #define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) | ||
| 404 | #define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) | ||
| 405 | #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) | ||
| 406 | |||
| 407 | #define S_BCM1480_MC_DRAM_TYPE 32 | ||
| 408 | #define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) | ||
| 409 | #define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) | ||
| 410 | #define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) | ||
| 411 | |||
| 412 | #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 | ||
| 413 | #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 | ||
| 414 | |||
| 415 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 416 | #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 | ||
| 417 | #endif | ||
| 418 | |||
| 419 | #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 | ||
| 420 | |||
| 421 | #define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) | ||
| 422 | #define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) | ||
| 423 | |||
| 424 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 425 | #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) | ||
| 426 | #endif | ||
| 427 | |||
| 428 | #define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) | ||
| 429 | #define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) | ||
| 430 | #define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) | ||
| 431 | #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) | ||
| 432 | |||
| 433 | #define S_BCM1480_MC_PG_POLICY 40 | ||
| 434 | #define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) | ||
| 435 | #define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) | ||
| 436 | #define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) | ||
| 437 | |||
| 438 | #define K_BCM1480_MC_PG_POLICY_CLOSED 0 | ||
| 439 | #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 | ||
| 440 | |||
| 441 | #define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) | ||
| 442 | #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) | ||
| 443 | |||
| 444 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 445 | #define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) | ||
| 446 | #define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) | ||
| 447 | #endif | ||
| 448 | |||
| 449 | #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ | ||
| 450 | V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) | ||
| 451 | |||
| 452 | /* | ||
| 453 | * Memory Clock Configuration Register (Table 92) | ||
| 454 | */ | ||
| 455 | |||
| 456 | #define S_BCM1480_MC_CLK_RATIO 0 | ||
| 457 | #define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) | ||
| 458 | #define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) | ||
| 459 | #define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) | ||
| 460 | |||
| 461 | #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) | ||
| 462 | |||
| 463 | #define S_BCM1480_MC_REF_RATE 8 | ||
| 464 | #define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) | ||
| 465 | #define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) | ||
| 466 | #define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) | ||
| 467 | |||
| 468 | #define K_BCM1480_MC_REF_RATE_100MHz 0x31 | ||
| 469 | #define K_BCM1480_MC_REF_RATE_200MHz 0x62 | ||
| 470 | #define K_BCM1480_MC_REF_RATE_400MHz 0xC4 | ||
| 471 | |||
| 472 | #define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) | ||
| 473 | #define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) | ||
| 474 | #define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) | ||
| 475 | #define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz | ||
| 476 | |||
| 477 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 478 | #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) | ||
| 479 | #endif | ||
| 480 | |||
| 481 | /* | ||
| 482 | * ODT Register (Table 99) | ||
| 483 | */ | ||
| 484 | |||
| 485 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 486 | #define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) | ||
| 487 | #define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) | ||
| 488 | #define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) | ||
| 489 | #define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) | ||
| 490 | #define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) | ||
| 491 | #define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) | ||
| 492 | #define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) | ||
| 493 | #define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) | ||
| 494 | #define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) | ||
| 495 | #define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) | ||
| 496 | #define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) | ||
| 497 | #define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) | ||
| 498 | #define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) | ||
| 499 | #define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) | ||
| 500 | #define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) | ||
| 501 | #define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) | ||
| 502 | #define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) | ||
| 503 | #define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) | ||
| 504 | #define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) | ||
| 505 | #define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) | ||
| 506 | #define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) | ||
| 507 | #define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) | ||
| 508 | #define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) | ||
| 509 | #define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) | ||
| 510 | #define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) | ||
| 511 | #define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) | ||
| 512 | #define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) | ||
| 513 | #define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) | ||
| 514 | #define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) | ||
| 515 | #define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) | ||
| 516 | #define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) | ||
| 517 | #define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) | ||
| 518 | |||
| 519 | #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) | ||
| 520 | |||
| 521 | #define S_BCM1480_MC_ODT0 0 | ||
| 522 | #define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) | ||
| 523 | #define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) | ||
| 524 | |||
| 525 | #define S_BCM1480_MC_ODT2 8 | ||
| 526 | #define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) | ||
| 527 | #define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) | ||
| 528 | |||
| 529 | #define S_BCM1480_MC_ODT4 16 | ||
| 530 | #define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) | ||
| 531 | #define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) | ||
| 532 | |||
| 533 | #define S_BCM1480_MC_ODT6 24 | ||
| 534 | #define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) | ||
| 535 | #define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) | ||
| 536 | #endif | ||
| 537 | |||
| 538 | /* | ||
| 539 | * Memory DLL Configuration Register (Table 93) | ||
| 540 | */ | ||
| 541 | |||
| 542 | #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 | ||
| 543 | #define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 544 | #define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 545 | #define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) | ||
| 546 | #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) | ||
| 547 | |||
| 548 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 549 | #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 | ||
| 550 | #define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 551 | #define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 552 | #define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) | ||
| 553 | #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) | ||
| 554 | #endif | ||
| 555 | |||
| 556 | #define S_BCM1480_MC_ADDR_FINE_ADJ 8 | ||
| 557 | #define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 558 | #define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 559 | #define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) | ||
| 560 | #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) | ||
| 561 | |||
| 562 | #define S_BCM1480_MC_DQI_COARSE_ADJ 16 | ||
| 563 | #define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 564 | #define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 565 | #define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) | ||
| 566 | #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) | ||
| 567 | |||
| 568 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 569 | #define S_BCM1480_MC_DQI_FREQ_RANGE 24 | ||
| 570 | #define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 571 | #define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 572 | #define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) | ||
| 573 | #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) | ||
| 574 | #endif | ||
| 575 | |||
| 576 | #define S_BCM1480_MC_DQI_FINE_ADJ 24 | ||
| 577 | #define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) | ||
| 578 | #define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) | ||
| 579 | #define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) | ||
| 580 | #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) | ||
| 581 | |||
| 582 | #define S_BCM1480_MC_DQO_COARSE_ADJ 32 | ||
| 583 | #define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 584 | #define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 585 | #define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) | ||
| 586 | #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) | ||
| 587 | |||
| 588 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 589 | #define S_BCM1480_MC_DQO_FREQ_RANGE 40 | ||
| 590 | #define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 591 | #define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 592 | #define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) | ||
| 593 | #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) | ||
| 594 | #endif | ||
| 595 | |||
| 596 | #define S_BCM1480_MC_DQO_FINE_ADJ 40 | ||
| 597 | #define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) | ||
| 598 | #define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) | ||
| 599 | #define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) | ||
| 600 | #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) | ||
| 601 | |||
| 602 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 603 | #define S_BCM1480_MC_DLL_PDSEL 44 | ||
| 604 | #define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) | ||
| 605 | #define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) | ||
| 606 | #define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) | ||
| 607 | #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) | ||
| 608 | |||
| 609 | #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) | ||
| 610 | #define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) | ||
| 611 | #endif | ||
| 612 | |||
| 613 | #define S_BCM1480_MC_DLL_DEFAULT 48 | ||
| 614 | #define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) | ||
| 615 | #define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) | ||
| 616 | #define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) | ||
| 617 | #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) | ||
| 618 | |||
| 619 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 620 | #define S_BCM1480_MC_DLL_REGCTRL 54 | ||
| 621 | #define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) | ||
| 622 | #define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) | ||
| 623 | #define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) | ||
| 624 | #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) | ||
| 625 | #endif | ||
| 626 | |||
| 627 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 628 | #define S_BCM1480_MC_DLL_FREQ_RANGE 56 | ||
| 629 | #define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 630 | #define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 631 | #define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) | ||
| 632 | #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) | ||
| 633 | #endif | ||
| 634 | |||
| 635 | #define S_BCM1480_MC_DLL_STEP_SIZE 56 | ||
| 636 | #define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) | ||
| 637 | #define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) | ||
| 638 | #define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) | ||
| 639 | #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) | ||
| 640 | |||
| 641 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 642 | #define S_BCM1480_MC_DLL_BGCTRL 60 | ||
| 643 | #define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) | ||
| 644 | #define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) | ||
| 645 | #define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) | ||
| 646 | #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) | ||
| 647 | #endif | ||
| 648 | |||
| 649 | #define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) | ||
| 650 | |||
| 651 | /* | ||
| 652 | * Memory Drive Configuration Register (Table 94) | ||
| 653 | */ | ||
| 654 | |||
| 655 | #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 | ||
| 656 | #define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 657 | #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 658 | #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) | ||
| 659 | |||
| 660 | #define S_BCM1480_MC_RTT_BYP_PULLUP 6 | ||
| 661 | #define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 662 | #define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 663 | #define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) | ||
| 664 | |||
| 665 | #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) | ||
| 666 | #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) | ||
| 667 | |||
| 668 | #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 | ||
| 669 | #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 670 | #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 671 | #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | ||
| 672 | |||
| 673 | #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 | ||
| 674 | #define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 675 | #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 676 | #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) | ||
| 677 | |||
| 678 | #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 | ||
| 679 | #define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 680 | #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 681 | #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | ||
| 682 | |||
| 683 | #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 | ||
| 684 | #define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 685 | #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 686 | #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) | ||
| 687 | |||
| 688 | #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) | ||
| 689 | #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) | ||
| 690 | |||
| 691 | #define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) | ||
| 692 | #define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) | ||
| 693 | #define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) | ||
| 694 | |||
| 695 | #define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) | ||
| 696 | #define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) | ||
| 697 | #define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) | ||
| 698 | #define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) | ||
| 699 | #define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) | ||
| 700 | |||
| 701 | /* | ||
| 702 | * ECC Test Data Register (Table 95) | ||
| 703 | */ | ||
| 704 | |||
| 705 | #define S_BCM1480_MC_DATA_INVERT 0 | ||
| 706 | #define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) | ||
| 707 | |||
| 708 | /* | ||
| 709 | * ECC Test ECC Register (Table 96) | ||
| 710 | */ | ||
| 711 | |||
| 712 | #define S_BCM1480_MC_ECC_INVERT 0 | ||
| 713 | #define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) | ||
| 714 | |||
| 715 | /* | ||
| 716 | * SDRAM Timing Register (Table 97) | ||
| 717 | */ | ||
| 718 | |||
| 719 | #define S_BCM1480_MC_tRCD 0 | ||
| 720 | #define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) | ||
| 721 | #define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) | ||
| 722 | #define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) | ||
| 723 | #define K_BCM1480_MC_tRCD_DEFAULT 3 | ||
| 724 | #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) | ||
| 725 | |||
| 726 | #define S_BCM1480_MC_tCL 4 | ||
| 727 | #define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) | ||
| 728 | #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) | ||
| 729 | #define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) | ||
| 730 | #define K_BCM1480_MC_tCL_DEFAULT 2 | ||
| 731 | #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) | ||
| 732 | |||
| 733 | #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) | ||
| 734 | |||
| 735 | #define S_BCM1480_MC_tWR 9 | ||
| 736 | #define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) | ||
| 737 | #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) | ||
| 738 | #define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) | ||
| 739 | #define K_BCM1480_MC_tWR_DEFAULT 2 | ||
| 740 | #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) | ||
| 741 | |||
| 742 | #define S_BCM1480_MC_tCwD 12 | ||
| 743 | #define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) | ||
| 744 | #define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) | ||
| 745 | #define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) | ||
| 746 | #define K_BCM1480_MC_tCwD_DEFAULT 1 | ||
| 747 | #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) | ||
| 748 | |||
| 749 | #define S_BCM1480_MC_tRP 16 | ||
| 750 | #define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) | ||
| 751 | #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) | ||
| 752 | #define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) | ||
| 753 | #define K_BCM1480_MC_tRP_DEFAULT 4 | ||
| 754 | #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) | ||
| 755 | |||
| 756 | #define S_BCM1480_MC_tRRD 20 | ||
| 757 | #define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) | ||
| 758 | #define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) | ||
| 759 | #define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) | ||
| 760 | #define K_BCM1480_MC_tRRD_DEFAULT 2 | ||
| 761 | #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) | ||
| 762 | |||
| 763 | #define S_BCM1480_MC_tRCw 24 | ||
| 764 | #define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) | ||
| 765 | #define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) | ||
| 766 | #define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) | ||
| 767 | #define K_BCM1480_MC_tRCw_DEFAULT 10 | ||
| 768 | #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) | ||
| 769 | |||
| 770 | #define S_BCM1480_MC_tRCr 32 | ||
| 771 | #define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) | ||
| 772 | #define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) | ||
| 773 | #define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) | ||
| 774 | #define K_BCM1480_MC_tRCr_DEFAULT 9 | ||
| 775 | #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) | ||
| 776 | |||
| 777 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 778 | #define S_BCM1480_MC_tFAW 40 | ||
| 779 | #define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) | ||
| 780 | #define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) | ||
| 781 | #define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) | ||
| 782 | #define K_BCM1480_MC_tFAW_DEFAULT 0 | ||
| 783 | #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) | ||
| 784 | #endif | ||
| 785 | |||
| 786 | #define S_BCM1480_MC_tRFC 48 | ||
| 787 | #define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) | ||
| 788 | #define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) | ||
| 789 | #define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) | ||
| 790 | #define K_BCM1480_MC_tRFC_DEFAULT 12 | ||
| 791 | #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) | ||
| 792 | |||
| 793 | #define S_BCM1480_MC_tFIFO 56 | ||
| 794 | #define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) | ||
| 795 | #define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) | ||
| 796 | #define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) | ||
| 797 | #define K_BCM1480_MC_tFIFO_DEFAULT 0 | ||
| 798 | #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) | ||
| 799 | |||
| 800 | #define S_BCM1480_MC_tW2R 58 | ||
| 801 | #define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) | ||
| 802 | #define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) | ||
| 803 | #define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) | ||
| 804 | #define K_BCM1480_MC_tW2R_DEFAULT 1 | ||
| 805 | #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) | ||
| 806 | |||
| 807 | #define S_BCM1480_MC_tR2W 60 | ||
| 808 | #define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) | ||
| 809 | #define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) | ||
| 810 | #define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) | ||
| 811 | #define K_BCM1480_MC_tR2W_DEFAULT 0 | ||
| 812 | #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) | ||
| 813 | |||
| 814 | #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) | ||
| 815 | |||
| 816 | #define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ | ||
| 817 | V_BCM1480_MC_tFIFO_DEFAULT | \ | ||
| 818 | V_BCM1480_MC_tR2W_DEFAULT | \ | ||
| 819 | V_BCM1480_MC_tW2R_DEFAULT | \ | ||
| 820 | V_BCM1480_MC_tRFC_DEFAULT | \ | ||
| 821 | V_BCM1480_MC_tRCr_DEFAULT | \ | ||
| 822 | V_BCM1480_MC_tRCw_DEFAULT | \ | ||
| 823 | V_BCM1480_MC_tRRD_DEFAULT | \ | ||
| 824 | V_BCM1480_MC_tRP_DEFAULT | \ | ||
| 825 | V_BCM1480_MC_tCwD_DEFAULT | \ | ||
| 826 | V_BCM1480_MC_tWR_DEFAULT | \ | ||
| 827 | M_BCM1480_MC_tCrDh | \ | ||
| 828 | V_BCM1480_MC_tCL_DEFAULT | \ | ||
| 829 | V_BCM1480_MC_tRCD_DEFAULT) | ||
| 830 | |||
| 831 | /* | ||
| 832 | * SDRAM Timing Register 2 | ||
| 833 | */ | ||
| 834 | |||
| 835 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 836 | |||
| 837 | #define S_BCM1480_MC_tAL 0 | ||
| 838 | #define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) | ||
| 839 | #define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) | ||
| 840 | #define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) | ||
| 841 | #define K_BCM1480_MC_tAL_DEFAULT 0 | ||
| 842 | #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) | ||
| 843 | |||
| 844 | #define S_BCM1480_MC_tRTP 4 | ||
| 845 | #define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) | ||
| 846 | #define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) | ||
| 847 | #define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) | ||
| 848 | #define K_BCM1480_MC_tRTP_DEFAULT 2 | ||
| 849 | #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) | ||
| 850 | |||
| 851 | #define S_BCM1480_MC_tW2W 8 | ||
| 852 | #define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) | ||
| 853 | #define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) | ||
| 854 | #define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) | ||
| 855 | #define K_BCM1480_MC_tW2W_DEFAULT 0 | ||
| 856 | #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) | ||
| 857 | |||
| 858 | #define S_BCM1480_MC_tRAP 12 | ||
| 859 | #define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) | ||
| 860 | #define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) | ||
| 861 | #define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) | ||
| 862 | #define K_BCM1480_MC_tRAP_DEFAULT 0 | ||
| 863 | #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) | ||
| 864 | |||
| 865 | #endif | ||
| 866 | |||
| 867 | |||
| 868 | |||
| 869 | /* | ||
| 870 | * Global Registers: single instances per BCM1480 | ||
| 871 | */ | ||
| 872 | |||
| 873 | /* | ||
| 874 | * Global Configuration Register (Table 99) | ||
| 875 | */ | ||
| 876 | |||
| 877 | #define S_BCM1480_MC_BLK_SET_MARK 8 | ||
| 878 | #define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) | ||
| 879 | #define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) | ||
| 880 | #define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) | ||
| 881 | |||
| 882 | #define S_BCM1480_MC_BLK_CLR_MARK 12 | ||
| 883 | #define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) | ||
| 884 | #define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) | ||
| 885 | #define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) | ||
| 886 | |||
| 887 | #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) | ||
| 888 | |||
| 889 | #define S_BCM1480_MC_MAX_AGE 20 | ||
| 890 | #define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) | ||
| 891 | #define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) | ||
| 892 | #define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) | ||
| 893 | |||
| 894 | #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) | ||
| 895 | #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) | ||
| 896 | #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) | ||
| 897 | |||
| 898 | #define S_BCM1480_MC_SLEW 33 | ||
| 899 | #define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) | ||
| 900 | #define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) | ||
| 901 | #define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) | ||
| 902 | |||
| 903 | #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) | ||
| 904 | |||
| 905 | /* | ||
| 906 | * Global Channel Interleave Register (Table 100) | ||
| 907 | */ | ||
| 908 | |||
| 909 | #define S_BCM1480_MC_INTLV0 0 | ||
| 910 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) | ||
| 911 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) | ||
| 912 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) | ||
| 913 | |||
| 914 | #define S_BCM1480_MC_INTLV1 8 | ||
| 915 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) | ||
| 916 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) | ||
| 917 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) | ||
| 918 | |||
| 919 | #define S_BCM1480_MC_INTLV_MODE 16 | ||
| 920 | #define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) | ||
| 921 | #define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) | ||
| 922 | #define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) | ||
| 923 | |||
| 924 | #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 | ||
| 925 | #define K_BCM1480_MC_INTLV_MODE_01 0x1 | ||
| 926 | #define K_BCM1480_MC_INTLV_MODE_23 0x2 | ||
| 927 | #define K_BCM1480_MC_INTLV_MODE_01_23 0x3 | ||
| 928 | #define K_BCM1480_MC_INTLV_MODE_0123 0x4 | ||
| 929 | |||
| 930 | #define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) | ||
| 931 | #define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) | ||
| 932 | #define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) | ||
| 933 | #define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) | ||
| 934 | #define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) | ||
| 935 | |||
| 936 | /* | ||
| 937 | * ECC Status Register | ||
| 938 | */ | ||
| 939 | |||
| 940 | #define S_BCM1480_MC_ECC_ERR_ADDR 0 | ||
| 941 | #define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) | ||
| 942 | #define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) | ||
| 943 | #define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) | ||
| 944 | |||
| 945 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 946 | #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) | ||
| 947 | #endif | ||
| 948 | |||
| 949 | #define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) | ||
| 950 | #define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) | ||
| 951 | #define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) | ||
| 952 | |||
| 953 | /* | ||
| 954 | * Global ECC Address Register (Table 102) | ||
| 955 | */ | ||
| 956 | |||
| 957 | #define S_BCM1480_MC_ECC_CORR_ADDR 0 | ||
| 958 | #define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) | ||
| 959 | #define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) | ||
| 960 | #define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) | ||
| 961 | |||
| 962 | /* | ||
| 963 | * Global ECC Correction Register (Table 103) | ||
| 964 | */ | ||
| 965 | |||
| 966 | #define S_BCM1480_MC_ECC_CORRECT 0 | ||
| 967 | #define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) | ||
| 968 | #define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) | ||
| 969 | #define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) | ||
| 970 | |||
| 971 | /* | ||
| 972 | * Global ECC Performance Counters Control Register (Table 104) | ||
| 973 | */ | ||
| 974 | |||
| 975 | #define S_BCM1480_MC_CHANNEL_SELECT 0 | ||
| 976 | #define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) | ||
| 977 | #define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) | ||
| 978 | #define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) | ||
| 979 | #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 | ||
| 980 | #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 | ||
| 981 | #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 | ||
| 982 | #define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 | ||
| 983 | |||
| 984 | #endif /* _BCM1480_MC_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h new file mode 100644 index 000000000000..b4077bb72611 --- /dev/null +++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h | |||
| @@ -0,0 +1,902 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package | ||
| 3 | * | ||
| 4 | * Register Definitions File: bcm1480_regs.h | ||
| 5 | * | ||
| 6 | * This module contains the addresses of the on-chip peripherals | ||
| 7 | * on the BCM1280 and BCM1480. | ||
| 8 | * | ||
| 9 | * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _BCM1480_REGS_H | ||
| 33 | #define _BCM1480_REGS_H | ||
| 34 | |||
| 35 | #include "sb1250_defs.h" | ||
| 36 | |||
| 37 | /* ********************************************************************* | ||
| 38 | * Pull in the BCM1250's registers since a great deal of the 1480's | ||
| 39 | * functions are the same as the BCM1250. | ||
| 40 | ********************************************************************* */ | ||
| 41 | |||
| 42 | #include "sb1250_regs.h" | ||
| 43 | |||
| 44 | |||
| 45 | /* ********************************************************************* | ||
| 46 | * Some general notes: | ||
| 47 | * | ||
| 48 | * Register addresses are grouped by function and follow the order | ||
| 49 | * of the User Manual. | ||
| 50 | * | ||
| 51 | * For the most part, when there is more than one peripheral | ||
| 52 | * of the same type on the SOC, the constants below will be | ||
| 53 | * offsets from the base of each peripheral. For example, | ||
| 54 | * the MAC registers are described as offsets from the first | ||
| 55 | * MAC register, and there will be a MAC_REGISTER() macro | ||
| 56 | * to calculate the base address of a given MAC. | ||
| 57 | * | ||
| 58 | * The information in this file is based on the BCM1X55/BCM1X80 | ||
| 59 | * User Manual, Document 1X55_1X80-UM100-R, 22/12/03. | ||
| 60 | * | ||
| 61 | * This file is basically a "what's new" header file. Since the | ||
| 62 | * BCM1250 and the new BCM1480 (and derivatives) share many common | ||
| 63 | * features, this file contains only what's new or changed from | ||
| 64 | * the 1250. (above, you can see that we include the 1250 symbols | ||
| 65 | * to get the base functionality). | ||
| 66 | * | ||
| 67 | * In software, be sure to use the correct symbols, particularly | ||
| 68 | * for blocks that are different between the two chip families. | ||
| 69 | * All BCM1480-specific symbols have _BCM1480_ in their names, | ||
| 70 | * and all BCM1250-specific and "base" functions that are common in | ||
| 71 | * both chips have no special names (this is for compatibility with | ||
| 72 | * older include files). Therefore, if you're working with the | ||
| 73 | * SCD, which is very different on each chip, A_SCD_xxx implies | ||
| 74 | * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 | ||
| 75 | * version. | ||
| 76 | ********************************************************************* */ | ||
| 77 | |||
| 78 | |||
| 79 | /* ********************************************************************* | ||
| 80 | * Memory Controller Registers (Section 6) | ||
| 81 | ********************************************************************* */ | ||
| 82 | |||
| 83 | #define A_BCM1480_MC_BASE_0 0x0010050000 | ||
| 84 | #define A_BCM1480_MC_BASE_1 0x0010051000 | ||
| 85 | #define A_BCM1480_MC_BASE_2 0x0010052000 | ||
| 86 | #define A_BCM1480_MC_BASE_3 0x0010053000 | ||
| 87 | #define BCM1480_MC_REGISTER_SPACING 0x1000 | ||
| 88 | |||
| 89 | #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING) | ||
| 90 | #define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) | ||
| 91 | |||
| 92 | #define R_BCM1480_MC_CONFIG 0x0000000100 | ||
| 93 | #define R_BCM1480_MC_CS_START 0x0000000120 | ||
| 94 | #define R_BCM1480_MC_CS_END 0x0000000140 | ||
| 95 | #define S_BCM1480_MC_CS_STARTEND 24 | ||
| 96 | |||
| 97 | #define R_BCM1480_MC_CS01_ROW0 0x0000000180 | ||
| 98 | #define R_BCM1480_MC_CS01_ROW1 0x00000001A0 | ||
| 99 | #define R_BCM1480_MC_CS23_ROW0 0x0000000200 | ||
| 100 | #define R_BCM1480_MC_CS23_ROW1 0x0000000220 | ||
| 101 | #define R_BCM1480_MC_CS01_COL0 0x0000000280 | ||
| 102 | #define R_BCM1480_MC_CS01_COL1 0x00000002A0 | ||
| 103 | #define R_BCM1480_MC_CS23_COL0 0x0000000300 | ||
| 104 | #define R_BCM1480_MC_CS23_COL1 0x0000000320 | ||
| 105 | |||
| 106 | #define R_BCM1480_MC_CSX_BASE 0x0000000180 | ||
| 107 | #define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */ | ||
| 108 | #define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */ | ||
| 109 | #define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */ | ||
| 110 | #define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */ | ||
| 111 | #define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */ | ||
| 112 | |||
| 113 | #define R_BCM1480_MC_CS01_BA 0x0000000380 | ||
| 114 | #define R_BCM1480_MC_CS23_BA 0x00000003A0 | ||
| 115 | #define R_BCM1480_MC_DRAMCMD 0x0000000400 | ||
| 116 | #define R_BCM1480_MC_DRAMMODE 0x0000000420 | ||
| 117 | #define R_BCM1480_MC_CLOCK_CFG 0x0000000440 | ||
| 118 | #define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG | ||
| 119 | #define R_BCM1480_MC_TEST_DATA 0x0000000480 | ||
| 120 | #define R_BCM1480_MC_TEST_ECC 0x00000004A0 | ||
| 121 | #define R_BCM1480_MC_TIMING1 0x00000004C0 | ||
| 122 | #define R_BCM1480_MC_TIMING2 0x00000004E0 | ||
| 123 | #define R_BCM1480_MC_DLL_CFG 0x0000000500 | ||
| 124 | #define R_BCM1480_MC_DRIVE_CFG 0x0000000520 | ||
| 125 | |||
| 126 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | ||
| 127 | #define R_BCM1480_MC_ODT 0x0000000460 | ||
| 128 | #define R_BCM1480_MC_ECC_STATUS 0x0000000540 | ||
| 129 | #endif | ||
| 130 | |||
| 131 | /* Global registers (single instance) */ | ||
| 132 | #define A_BCM1480_MC_GLB_CONFIG 0x0010054100 | ||
| 133 | #define A_BCM1480_MC_GLB_INTLV 0x0010054120 | ||
| 134 | #define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140 | ||
| 135 | #define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160 | ||
| 136 | #define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180 | ||
| 137 | #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0 | ||
| 138 | |||
| 139 | /* ********************************************************************* | ||
| 140 | * L2 Cache Control Registers (Section 5) | ||
| 141 | ********************************************************************* */ | ||
| 142 | |||
| 143 | #define A_BCM1480_L2_BASE 0x0010040000 | ||
| 144 | |||
| 145 | #define A_BCM1480_L2_READ_TAG 0x0010040018 | ||
| 146 | #define A_BCM1480_L2_ECC_TAG 0x0010040038 | ||
| 147 | #define A_BCM1480_L2_MISC0_VALUE 0x0010040058 | ||
| 148 | #define A_BCM1480_L2_MISC1_VALUE 0x0010040078 | ||
| 149 | #define A_BCM1480_L2_MISC2_VALUE 0x0010040098 | ||
| 150 | #define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */ | ||
| 151 | #define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */ | ||
| 152 | #define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12)) | ||
| 153 | #define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */ | ||
| 154 | #define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */ | ||
| 155 | #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12)) | ||
| 156 | #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12)) | ||
| 157 | #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12)) | ||
| 158 | #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12)) | ||
| 159 | #define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */ | ||
| 160 | #define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */ | ||
| 161 | #define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */ | ||
| 162 | #define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */ | ||
| 163 | #define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */ | ||
| 164 | #define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */ | ||
| 165 | #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8)) | ||
| 166 | #define A_BCM1480_L2_BANK_BASE 0x00D0300000 | ||
| 167 | #define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17)) | ||
| 168 | #define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000 | ||
| 169 | |||
| 170 | |||
| 171 | /* ********************************************************************* | ||
| 172 | * PCI-X Interface Registers (Section 7) | ||
| 173 | ********************************************************************* */ | ||
| 174 | |||
| 175 | #define A_BCM1480_PCI_BASE 0x0010061400 | ||
| 176 | |||
| 177 | #define A_BCM1480_PCI_RESET 0x0010061400 | ||
| 178 | #define A_BCM1480_PCI_DLL 0x0010061500 | ||
| 179 | |||
| 180 | #define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000 | ||
| 181 | |||
| 182 | /* ********************************************************************* | ||
| 183 | * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6) | ||
| 184 | ********************************************************************* */ | ||
| 185 | |||
| 186 | /* No register changes with Rev.C BCM1250, but one additional MAC */ | ||
| 187 | |||
| 188 | #define A_BCM1480_MAC_BASE_2 0x0010066000 | ||
| 189 | |||
| 190 | #ifndef A_MAC_BASE_2 | ||
| 191 | #define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2 | ||
| 192 | #endif | ||
| 193 | |||
| 194 | #define A_BCM1480_MAC_BASE_3 0x0010067000 | ||
| 195 | #define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3 | ||
| 196 | |||
| 197 | #define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038 | ||
| 198 | |||
| 199 | #ifndef R_MAC_DMA_OODPKTLOST | ||
| 200 | #define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST | ||
| 201 | #endif | ||
| 202 | |||
| 203 | |||
| 204 | /* ********************************************************************* | ||
| 205 | * DUART Registers (Section 14) | ||
| 206 | ********************************************************************* */ | ||
| 207 | |||
| 208 | /* No significant differences from BCM1250, two DUARTs */ | ||
| 209 | |||
| 210 | /* Conventions, per user manual: | ||
| 211 | * DUART generic, channels A,B,C,D | ||
| 212 | * DUART0 implementing channels A,B | ||
| 213 | * DUART1 inplementing channels C,D | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define BCM1480_DUART_NUM_PORTS 4 | ||
| 217 | |||
| 218 | #define A_BCM1480_DUART0 0x0010060000 | ||
| 219 | #define A_BCM1480_DUART1 0x0010060400 | ||
| 220 | #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1) | ||
| 221 | |||
| 222 | #define BCM1480_DUART_CHANREG_SPACING 0x100 | ||
| 223 | #define A_BCM1480_DUART_CHANREG(chan, reg) \ | ||
| 224 | (A_BCM1480_DUART(chan) + \ | ||
| 225 | BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) | ||
| 226 | #define A_BCM1480_DUART_CTRLREG(chan, reg) \ | ||
| 227 | (A_BCM1480_DUART(chan) + \ | ||
| 228 | BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) | ||
| 229 | |||
| 230 | #define DUART_IMRISR_SPACING 0x20 | ||
| 231 | #define DUART_INCHNG_SPACING 0x10 | ||
| 232 | |||
| 233 | #define R_BCM1480_DUART_IMRREG(chan) \ | ||
| 234 | (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING) | ||
| 235 | #define R_BCM1480_DUART_ISRREG(chan) \ | ||
| 236 | (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING) | ||
| 237 | #define R_BCM1480_DUART_INCHREG(chan) \ | ||
| 238 | (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING) | ||
| 239 | |||
| 240 | #define A_BCM1480_DUART_IMRREG(chan) \ | ||
| 241 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan))) | ||
| 242 | #define A_BCM1480_DUART_ISRREG(chan) \ | ||
| 243 | (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan))) | ||
| 244 | |||
| 245 | #define A_BCM1480_DUART_IN_PORT(chan) \ | ||
| 246 | (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT)) | ||
| 247 | |||
| 248 | /* | ||
| 249 | * These constants are the absolute addresses. | ||
| 250 | */ | ||
| 251 | |||
| 252 | #define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400 | ||
| 253 | #define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410 | ||
| 254 | #define A_BCM1480_DUART_STATUS_C 0x0010060420 | ||
| 255 | #define A_BCM1480_DUART_CLK_SEL_C 0x0010060430 | ||
| 256 | #define A_BCM1480_DUART_FULL_CTL_C 0x0010060440 | ||
| 257 | #define A_BCM1480_DUART_CMD_C 0x0010060450 | ||
| 258 | #define A_BCM1480_DUART_RX_HOLD_C 0x0010060460 | ||
| 259 | #define A_BCM1480_DUART_TX_HOLD_C 0x0010060470 | ||
| 260 | #define A_BCM1480_DUART_OPCR_C 0x0010060480 | ||
| 261 | #define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490 | ||
| 262 | |||
| 263 | #define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500 | ||
| 264 | #define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510 | ||
| 265 | #define A_BCM1480_DUART_STATUS_D 0x0010060520 | ||
| 266 | #define A_BCM1480_DUART_CLK_SEL_D 0x0010060530 | ||
| 267 | #define A_BCM1480_DUART_FULL_CTL_D 0x0010060540 | ||
| 268 | #define A_BCM1480_DUART_CMD_D 0x0010060550 | ||
| 269 | #define A_BCM1480_DUART_RX_HOLD_D 0x0010060560 | ||
| 270 | #define A_BCM1480_DUART_TX_HOLD_D 0x0010060570 | ||
| 271 | #define A_BCM1480_DUART_OPCR_D 0x0010060580 | ||
| 272 | #define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590 | ||
| 273 | |||
| 274 | #define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600 | ||
| 275 | #define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610 | ||
| 276 | #define A_BCM1480_DUART_ISR_C 0x0010060620 | ||
| 277 | #define A_BCM1480_DUART_IMR_C 0x0010060630 | ||
| 278 | #define A_BCM1480_DUART_ISR_D 0x0010060640 | ||
| 279 | #define A_BCM1480_DUART_IMR_D 0x0010060650 | ||
| 280 | #define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660 | ||
| 281 | #define A_BCM1480_DUART_OPCR_CD 0x0010060670 | ||
| 282 | #define A_BCM1480_DUART_IN_PORT_CD 0x0010060680 | ||
| 283 | #define A_BCM1480_DUART_ISR_CD 0x0010060690 | ||
| 284 | #define A_BCM1480_DUART_IMR_CD 0x00100606A0 | ||
| 285 | #define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0 | ||
| 286 | #define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0 | ||
| 287 | #define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0 | ||
| 288 | #define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0 | ||
| 289 | |||
| 290 | |||
| 291 | /* ********************************************************************* | ||
| 292 | * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16) | ||
| 293 | ********************************************************************* */ | ||
| 294 | |||
| 295 | #define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58 | ||
| 296 | #define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68 | ||
| 297 | |||
| 298 | /* ********************************************************************* | ||
| 299 | * GPIO Registers (Section 17) | ||
| 300 | ********************************************************************* */ | ||
| 301 | |||
| 302 | /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */ | ||
| 303 | |||
| 304 | #define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78 | ||
| 305 | #define R_BCM1480_GPIO_INT_ADD_TYPE (-8) | ||
| 306 | |||
| 307 | #define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE | ||
| 308 | #define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE | ||
| 309 | |||
| 310 | /* ********************************************************************* | ||
| 311 | * SMBus Registers (Section 18) | ||
| 312 | ********************************************************************* */ | ||
| 313 | |||
| 314 | /* No changes from BCM1250 */ | ||
| 315 | |||
| 316 | /* ********************************************************************* | ||
| 317 | * Timer Registers (Sections 4.6) | ||
| 318 | ********************************************************************* */ | ||
| 319 | |||
| 320 | /* BCM1480 has two additional watchdogs */ | ||
| 321 | |||
| 322 | /* Watchdog timers */ | ||
| 323 | |||
| 324 | #define A_BCM1480_SCD_WDOG_2 0x0010022050 | ||
| 325 | #define A_BCM1480_SCD_WDOG_3 0x0010022150 | ||
| 326 | |||
| 327 | #define BCM1480_SCD_NUM_WDOGS 4 | ||
| 328 | |||
| 329 | #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100) | ||
| 330 | #define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r)) | ||
| 331 | |||
| 332 | #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050 | ||
| 333 | #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058 | ||
| 334 | #define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060 | ||
| 335 | |||
| 336 | #define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150 | ||
| 337 | #define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158 | ||
| 338 | #define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160 | ||
| 339 | |||
| 340 | /* BCM1480 has two additional compare registers */ | ||
| 341 | |||
| 342 | #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT | ||
| 343 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00 | ||
| 344 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0 | ||
| 345 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1 | ||
| 346 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10 | ||
| 347 | #define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18 | ||
| 348 | |||
| 349 | /* ********************************************************************* | ||
| 350 | * System Control Registers (Section 4.2) | ||
| 351 | ********************************************************************* */ | ||
| 352 | |||
| 353 | /* Scratch register in different place */ | ||
| 354 | |||
| 355 | #define A_BCM1480_SCD_SCRATCH 0x100200A0 | ||
| 356 | |||
| 357 | /* ********************************************************************* | ||
| 358 | * System Address Trap Registers (Section 4.9) | ||
| 359 | ********************************************************************* */ | ||
| 360 | |||
| 361 | /* No changes from BCM1250 */ | ||
| 362 | |||
| 363 | /* ********************************************************************* | ||
| 364 | * System Interrupt Mapper Registers (Sections 4.3-4.5) | ||
| 365 | ********************************************************************* */ | ||
| 366 | |||
| 367 | #define A_BCM1480_IMR_CPU0_BASE 0x0010020000 | ||
| 368 | #define A_BCM1480_IMR_CPU1_BASE 0x0010022000 | ||
| 369 | #define A_BCM1480_IMR_CPU2_BASE 0x0010024000 | ||
| 370 | #define A_BCM1480_IMR_CPU3_BASE 0x0010026000 | ||
| 371 | #define BCM1480_IMR_REGISTER_SPACING 0x2000 | ||
| 372 | #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13 | ||
| 373 | |||
| 374 | #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING) | ||
| 375 | #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) | ||
| 376 | |||
| 377 | /* Most IMR registers are 128 bits, implemented as non-contiguous | ||
| 378 | 64-bit registers high (_H) and low (_L) */ | ||
| 379 | #define BCM1480_IMR_HL_SPACING 0x1000 | ||
| 380 | |||
| 381 | #define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010 | ||
| 382 | #define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018 | ||
| 383 | #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020 | ||
| 384 | #define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028 | ||
| 385 | #define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038 | ||
| 386 | #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040 | ||
| 387 | #define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048 | ||
| 388 | #define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0 | ||
| 389 | #define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8 | ||
| 390 | #define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0 | ||
| 391 | #define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0 | ||
| 392 | #define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8 | ||
| 393 | #define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0 | ||
| 394 | #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100 | ||
| 395 | #define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8 | ||
| 396 | #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200 | ||
| 397 | #define BCM1480_IMR_INTERRUPT_MAP_COUNT 64 | ||
| 398 | |||
| 399 | #define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010 | ||
| 400 | #define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018 | ||
| 401 | #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020 | ||
| 402 | #define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028 | ||
| 403 | #define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038 | ||
| 404 | #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040 | ||
| 405 | #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100 | ||
| 406 | #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200 | ||
| 407 | |||
| 408 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000 | ||
| 409 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100 | ||
| 410 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200 | ||
| 411 | #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300 | ||
| 412 | #define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100 | ||
| 413 | |||
| 414 | #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \ | ||
| 415 | (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING) | ||
| 416 | #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) | ||
| 417 | |||
| 418 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */ | ||
| 419 | #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */ | ||
| 420 | |||
| 421 | /* | ||
| 422 | * these macros work together to build the address of a mailbox | ||
| 423 | * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2) | ||
| 424 | * for mbox_0_set_cpu2 returns 0x00100240C8 | ||
| 425 | */ | ||
| 426 | #define R_BCM1480_IMR_MAILBOX_CPU 0x00 | ||
| 427 | #define R_BCM1480_IMR_MAILBOX_SET 0x08 | ||
| 428 | #define R_BCM1480_IMR_MAILBOX_CLR 0x10 | ||
| 429 | #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20 | ||
| 430 | #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ | ||
| 431 | (A_BCM1480_IMR_CPU0_BASE + \ | ||
| 432 | (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \ | ||
| 433 | (cpu * BCM1480_IMR_REGISTER_SPACING) + \ | ||
| 434 | (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) | ||
| 435 | |||
| 436 | /* ********************************************************************* | ||
| 437 | * System Performance Counter Registers (Section 4.7) | ||
| 438 | ********************************************************************* */ | ||
| 439 | |||
| 440 | /* BCM1480 has four more performance counter registers, and two control | ||
| 441 | registers. */ | ||
| 442 | |||
| 443 | #define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0 | ||
| 444 | |||
| 445 | #define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0 | ||
| 446 | #define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0 | ||
| 447 | #define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8 | ||
| 448 | #define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1 | ||
| 449 | |||
| 450 | #define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0 | ||
| 451 | #define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1 | ||
| 452 | #define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2 | ||
| 453 | #define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3 | ||
| 454 | |||
| 455 | #define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0 | ||
| 456 | #define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8 | ||
| 457 | #define A_BCM1480_SCD_PERF_CNT_6 0x0010020500 | ||
| 458 | #define A_BCM1480_SCD_PERF_CNT_7 0x0010020508 | ||
| 459 | |||
| 460 | #define BCM1480_SCD_NUM_PERF_CNT 8 | ||
| 461 | #define BCM1480_SCD_PERF_CNT_SPACING 8 | ||
| 462 | #define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING)) | ||
| 463 | |||
| 464 | /* ********************************************************************* | ||
| 465 | * System Bus Watcher Registers (Section 4.8) | ||
| 466 | ********************************************************************* */ | ||
| 467 | |||
| 468 | |||
| 469 | /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ | ||
| 470 | |||
| 471 | #define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8 | ||
| 472 | |||
| 473 | /* ********************************************************************* | ||
| 474 | * System Debug Controller Registers (Section 19) | ||
| 475 | ********************************************************************* */ | ||
| 476 | |||
| 477 | /* Same as 1250 */ | ||
| 478 | |||
| 479 | /* ********************************************************************* | ||
| 480 | * System Trace Unit Registers (Sections 4.10) | ||
| 481 | ********************************************************************* */ | ||
| 482 | |||
| 483 | /* Same as 1250 */ | ||
| 484 | |||
| 485 | /* ********************************************************************* | ||
| 486 | * Data Mover DMA Registers (Section 10.7) | ||
| 487 | ********************************************************************* */ | ||
| 488 | |||
| 489 | /* Same as 1250 */ | ||
| 490 | |||
| 491 | |||
| 492 | /* ********************************************************************* | ||
| 493 | * HyperTransport Interface Registers (Section 8) | ||
| 494 | ********************************************************************* */ | ||
| 495 | |||
| 496 | #define BCM1480_HT_NUM_PORTS 3 | ||
| 497 | #define BCM1480_HT_PORT_SPACING 0x800 | ||
| 498 | #define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING)) | ||
| 499 | |||
| 500 | #define A_BCM1480_HT_PORT0_HEADER 0x00FE000000 | ||
| 501 | #define A_BCM1480_HT_PORT1_HEADER 0x00FE000800 | ||
| 502 | #define A_BCM1480_HT_PORT2_HEADER 0x00FE001000 | ||
| 503 | #define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000 | ||
| 504 | |||
| 505 | |||
| 506 | /* ********************************************************************* | ||
| 507 | * Node Controller Registers (Section 9) | ||
| 508 | ********************************************************************* */ | ||
| 509 | |||
| 510 | #define A_BCM1480_NC_BASE 0x00DFBD0000 | ||
| 511 | |||
| 512 | #define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000 | ||
| 513 | #define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020 | ||
| 514 | #define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040 | ||
| 515 | #define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060 | ||
| 516 | #define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080 | ||
| 517 | #define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0 | ||
| 518 | #define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0 | ||
| 519 | |||
| 520 | #define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0 | ||
| 521 | #define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100 | ||
| 522 | #define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120 | ||
| 523 | #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140 | ||
| 524 | |||
| 525 | #define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200 | ||
| 526 | #define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220 | ||
| 527 | #define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240 | ||
| 528 | #define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260 | ||
| 529 | #define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280 | ||
| 530 | #define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0 | ||
| 531 | #define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0 | ||
| 532 | #define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0 | ||
| 533 | #define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300 | ||
| 534 | #define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320 | ||
| 535 | #define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000 | ||
| 536 | #define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020 | ||
| 537 | #define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040 | ||
| 538 | |||
| 539 | #define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060 | ||
| 540 | #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080 | ||
| 541 | |||
| 542 | |||
| 543 | /* ********************************************************************* | ||
| 544 | * H&R Block Configuration Registers (Section 12.4) | ||
| 545 | ********************************************************************* */ | ||
| 546 | |||
| 547 | #define A_BCM1480_HR_BASE_0 0x00DF820000 | ||
| 548 | #define A_BCM1480_HR_BASE_1 0x00DF8A0000 | ||
| 549 | #define A_BCM1480_HR_BASE_2 0x00DF920000 | ||
| 550 | #define BCM1480_HR_REGISTER_SPACING 0x80000 | ||
| 551 | |||
| 552 | #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING)) | ||
| 553 | #define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) | ||
| 554 | |||
| 555 | #define R_BCM1480_HR_CFG 0x0000000000 | ||
| 556 | |||
| 557 | #define R_BCM1480_HR_MAPPING 0x0000010010 | ||
| 558 | |||
| 559 | #define BCM1480_HR_RULE_SPACING 0x0000000010 | ||
| 560 | #define BCM1480_HR_NUM_RULES 16 | ||
| 561 | #define BCM1480_HR_OP_OFFSET 0x0000000100 | ||
| 562 | #define BCM1480_HR_TYPE_OFFSET 0x0000000108 | ||
| 563 | #define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) | ||
| 564 | #define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING)) | ||
| 565 | |||
| 566 | #define BCM1480_HR_LEAF_SPACING 0x0000000010 | ||
| 567 | #define BCM1480_HR_NUM_LEAVES 10 | ||
| 568 | #define BCM1480_HR_LEAF_OFFSET 0x0000000300 | ||
| 569 | #define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING)) | ||
| 570 | |||
| 571 | #define R_BCM1480_HR_EX_LEAF0 0x00000003A0 | ||
| 572 | |||
| 573 | #define BCM1480_HR_PATH_SPACING 0x0000000010 | ||
| 574 | #define BCM1480_HR_NUM_PATHS 16 | ||
| 575 | #define BCM1480_HR_PATH_OFFSET 0x0000000600 | ||
| 576 | #define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING)) | ||
| 577 | |||
| 578 | #define R_BCM1480_HR_PATH_DEFAULT 0x0000000700 | ||
| 579 | |||
| 580 | #define BCM1480_HR_ROUTE_SPACING 8 | ||
| 581 | #define BCM1480_HR_NUM_ROUTES 512 | ||
| 582 | #define BCM1480_HR_ROUTE_OFFSET 0x0000001000 | ||
| 583 | #define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING)) | ||
| 584 | |||
| 585 | |||
| 586 | /* checked to here - ehs */ | ||
| 587 | /* ********************************************************************* | ||
| 588 | * Packet Manager DMA Registers (Section 12.5) | ||
| 589 | ********************************************************************* */ | ||
| 590 | |||
| 591 | #define A_BCM1480_PM_BASE 0x0010056000 | ||
| 592 | |||
| 593 | #define A_BCM1480_PMI_LCL_0 0x0010058000 | ||
| 594 | #define A_BCM1480_PMO_LCL_0 0x001005C000 | ||
| 595 | #define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE) | ||
| 596 | #define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE) | ||
| 597 | |||
| 598 | #define BCM1480_PM_LCL_REGISTER_SPACING 0x100 | ||
| 599 | #define BCM1480_PM_NUM_CHANNELS 32 | ||
| 600 | |||
| 601 | #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | ||
| 602 | #define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) | ||
| 603 | #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING)) | ||
| 604 | #define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) | ||
| 605 | |||
| 606 | #define BCM1480_PM_INT_PACKING 8 | ||
| 607 | #define BCM1480_PM_INT_FUNCTION_SPACING 0x40 | ||
| 608 | #define BCM1480_PM_INT_NUM_FUNCTIONS 3 | ||
| 609 | |||
| 610 | /* | ||
| 611 | * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n) | ||
| 612 | */ | ||
| 613 | |||
| 614 | #define R_BCM1480_PM_BASE_SIZE 0x0000000000 | ||
| 615 | #define R_BCM1480_PM_CNT 0x0000000008 | ||
| 616 | #define R_BCM1480_PM_PFCNT 0x0000000010 | ||
| 617 | #define R_BCM1480_PM_LAST 0x0000000018 | ||
| 618 | #define R_BCM1480_PM_PFINDX 0x0000000020 | ||
| 619 | #define R_BCM1480_PM_INT_WMK 0x0000000028 | ||
| 620 | #define R_BCM1480_PM_CONFIG0 0x0000000030 | ||
| 621 | #define R_BCM1480_PM_LOCALDEBUG 0x0000000078 | ||
| 622 | #define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */ | ||
| 623 | #define R_BCM1480_PM_INT_CNFG 0x0000000088 | ||
| 624 | #define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090 | ||
| 625 | #define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */ | ||
| 626 | #define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */ | ||
| 627 | |||
| 628 | /* | ||
| 629 | * Global Registers (Not Channelized) | ||
| 630 | */ | ||
| 631 | |||
| 632 | #define A_BCM1480_PMI_GLB_0 0x0010056000 | ||
| 633 | #define A_BCM1480_PMO_GLB_0 0x0010057000 | ||
| 634 | |||
| 635 | /* | ||
| 636 | * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0 | ||
| 637 | */ | ||
| 638 | |||
| 639 | #define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */ | ||
| 640 | |||
| 641 | #define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING) | ||
| 642 | |||
| 643 | /* | ||
| 644 | * Interrupt mapping registers | ||
| 645 | */ | ||
| 646 | |||
| 647 | |||
| 648 | #define A_BCM1480_PMI_INT_0 0x0010056800 | ||
| 649 | #define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8)) | ||
| 650 | #define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE) | ||
| 651 | #define A_BCM1480_PMO_INT_0 0x0010057800 | ||
| 652 | #define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8)) | ||
| 653 | #define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE) | ||
| 654 | |||
| 655 | /* | ||
| 656 | * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0 | ||
| 657 | */ | ||
| 658 | |||
| 659 | #define R_BCM1480_PM_INT_ST 0x0000000000 | ||
| 660 | #define R_BCM1480_PM_INT_MSK 0x0000000040 | ||
| 661 | #define R_BCM1480_PM_INT_CLR 0x0000000080 | ||
| 662 | #define R_BCM1480_PM_MRGD_INT 0x00000000C0 | ||
| 663 | |||
| 664 | /* | ||
| 665 | * Debug registers (global) | ||
| 666 | */ | ||
| 667 | |||
| 668 | #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000 | ||
| 669 | #define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8 | ||
| 670 | #define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8 | ||
| 671 | #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000 | ||
| 672 | #define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8 | ||
| 673 | #define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8 | ||
| 674 | |||
| 675 | /* ********************************************************************* | ||
| 676 | * Switch performance counters | ||
| 677 | ********************************************************************* */ | ||
| 678 | |||
| 679 | #define A_BCM1480_SWPERF_CFG 0xdfb91800 | ||
| 680 | #define A_BCM1480_SWPERF_CNT0 0xdfb91880 | ||
| 681 | #define A_BCM1480_SWPERF_CNT1 0xdfb91888 | ||
| 682 | #define A_BCM1480_SWPERF_CNT2 0xdfb91890 | ||
| 683 | #define A_BCM1480_SWPERF_CNT3 0xdfb91898 | ||
| 684 | |||
| 685 | |||
| 686 | /* ********************************************************************* | ||
| 687 | * Switch Trace Unit | ||
| 688 | ********************************************************************* */ | ||
| 689 | |||
| 690 | #define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000 | ||
| 691 | #define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100 | ||
| 692 | #define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108 | ||
| 693 | #define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200 | ||
| 694 | #define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208 | ||
| 695 | #define A_BCM1480_SWTRC_EVENT_0 0xDFB91300 | ||
| 696 | #define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400 | ||
| 697 | |||
| 698 | #define A_BCM1480_SWTRC_CFG 0xDFB91500 | ||
| 699 | #define A_BCM1480_SWTRC_READ 0xDFB91508 | ||
| 700 | |||
| 701 | #define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000 | ||
| 702 | |||
| 703 | #define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8)) | ||
| 704 | #define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8)) | ||
| 705 | #define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8)) | ||
| 706 | |||
| 707 | #define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16)) | ||
| 708 | #define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16)) | ||
| 709 | #define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16)) | ||
| 710 | #define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16)) | ||
| 711 | |||
| 712 | |||
| 713 | |||
| 714 | /* ********************************************************************* | ||
| 715 | * High-Speed Port Registers (Section 13) | ||
| 716 | ********************************************************************* */ | ||
| 717 | |||
| 718 | #define A_BCM1480_HSP_BASE_0 0x00DF810000 | ||
| 719 | #define A_BCM1480_HSP_BASE_1 0x00DF890000 | ||
| 720 | #define A_BCM1480_HSP_BASE_2 0x00DF910000 | ||
| 721 | #define BCM1480_HSP_REGISTER_SPACING 0x80000 | ||
| 722 | |||
| 723 | #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING)) | ||
| 724 | #define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) | ||
| 725 | |||
| 726 | #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000 | ||
| 727 | #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008 | ||
| 728 | #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010 | ||
| 729 | #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018 | ||
| 730 | #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020 | ||
| 731 | #define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028 | ||
| 732 | |||
| 733 | #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200 | ||
| 734 | #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208 | ||
| 735 | |||
| 736 | #define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800 | ||
| 737 | #define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808 | ||
| 738 | #define R_BCM1480_HSP_RX_TEST 0x0000000810 | ||
| 739 | #define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818 | ||
| 740 | #define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820 | ||
| 741 | #define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828 | ||
| 742 | #define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830 | ||
| 743 | #define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838 | ||
| 744 | |||
| 745 | #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870 | ||
| 746 | |||
| 747 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020 | ||
| 748 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028 | ||
| 749 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030 | ||
| 750 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038 | ||
| 751 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040 | ||
| 752 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048 | ||
| 753 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050 | ||
| 754 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058 | ||
| 755 | #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx)) | ||
| 756 | |||
| 757 | /* XXX Following registers were shuffled. Renamed/renumbered per errata. */ | ||
| 758 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078 | ||
| 759 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080 | ||
| 760 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088 | ||
| 761 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090 | ||
| 762 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098 | ||
| 763 | #define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0 | ||
| 764 | |||
| 765 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0 | ||
| 766 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8 | ||
| 767 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0 | ||
| 768 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8 | ||
| 769 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0 | ||
| 770 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8 | ||
| 771 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0 | ||
| 772 | #define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8 | ||
| 773 | #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx)) | ||
| 774 | |||
| 775 | #define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0 | ||
| 776 | #define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8 | ||
| 777 | #define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100 | ||
| 778 | #define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108 | ||
| 779 | #define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110 | ||
| 780 | #define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118 | ||
| 781 | #define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120 | ||
| 782 | |||
| 783 | #define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000 | ||
| 784 | #define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008 | ||
| 785 | #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010 | ||
| 786 | |||
| 787 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020 | ||
| 788 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028 | ||
| 789 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030 | ||
| 790 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038 | ||
| 791 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040 | ||
| 792 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048 | ||
| 793 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050 | ||
| 794 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058 | ||
| 795 | #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx)) | ||
| 796 | #define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078 | ||
| 797 | #define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080 | ||
| 798 | #define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088 | ||
| 799 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090 | ||
| 800 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098 | ||
| 801 | #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0 | ||
| 802 | |||
| 803 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0 | ||
| 804 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8 | ||
| 805 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0 | ||
| 806 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8 | ||
| 807 | #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx)) | ||
| 808 | #define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0 | ||
| 809 | #define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8 | ||
| 810 | |||
| 811 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0 | ||
| 812 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8 | ||
| 813 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0 | ||
| 814 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8 | ||
| 815 | #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx)) | ||
| 816 | #define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100 | ||
| 817 | #define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108 | ||
| 818 | |||
| 819 | #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200 | ||
| 820 | #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208 | ||
| 821 | |||
| 822 | #define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800 | ||
| 823 | #define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808 | ||
| 824 | #define R_BCM1480_HSP_TX_TEST 0x0000040810 | ||
| 825 | |||
| 826 | #define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840 | ||
| 827 | #define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848 | ||
| 828 | #define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850 | ||
| 829 | #define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860 | ||
| 830 | #define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868 | ||
| 831 | #define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870 | ||
| 832 | #define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878 | ||
| 833 | |||
| 834 | #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880 | ||
| 835 | #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888 | ||
| 836 | |||
| 837 | #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400 | ||
| 838 | #define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x)) | ||
| 839 | |||
| 840 | |||
| 841 | |||
| 842 | /* ********************************************************************* | ||
| 843 | * Physical Address Map (Table 10 and Figure 7) | ||
| 844 | ********************************************************************* */ | ||
| 845 | |||
| 846 | #define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) | ||
| 847 | #define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) | ||
| 848 | #define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) | ||
| 849 | #define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) | ||
| 850 | #define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000) | ||
| 851 | #define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000) | ||
| 852 | #define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000) | ||
| 853 | #define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000) | ||
| 854 | #define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000) | ||
| 855 | #define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000) | ||
| 856 | #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000) | ||
| 857 | #define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000) | ||
| 858 | #define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000) | ||
| 859 | #define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000) | ||
| 860 | #define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) | ||
| 861 | #define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) | ||
| 862 | #define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000) | ||
| 863 | #define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000) | ||
| 864 | #define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000) | ||
| 865 | #define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000) | ||
| 866 | #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000) | ||
| 867 | #define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000) | ||
| 868 | #define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) | ||
| 869 | #define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) | ||
| 870 | #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) | ||
| 871 | #define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) | ||
| 872 | #define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) | ||
| 873 | #define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000) | ||
| 874 | #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) | ||
| 875 | #define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) | ||
| 876 | #define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) | ||
| 877 | #define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) | ||
| 878 | #define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) | ||
| 879 | #define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000) | ||
| 880 | #define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000) | ||
| 881 | #define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000) | ||
| 882 | #define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000) | ||
| 883 | #define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000) | ||
| 884 | |||
| 885 | |||
| 886 | /* ********************************************************************* | ||
| 887 | * L2 Cache as RAM (Table 54) | ||
| 888 | ********************************************************************* */ | ||
| 889 | |||
| 890 | #define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) | ||
| 891 | #define BCM1480_PHYS_L2CACHE_NUM_WAYS 8 | ||
| 892 | #define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000) | ||
| 893 | #define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000) | ||
| 894 | #define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000) | ||
| 895 | #define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000) | ||
| 896 | #define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000) | ||
| 897 | #define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000) | ||
| 898 | #define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000) | ||
| 899 | #define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000) | ||
| 900 | #define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000) | ||
| 901 | |||
| 902 | #endif /* _BCM1480_REGS_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h new file mode 100644 index 000000000000..25ef24cbb92a --- /dev/null +++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h | |||
| @@ -0,0 +1,406 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * BCM1280/BCM1400 Board Support Package | ||
| 3 | * | ||
| 4 | * SCD Constants and Macros File: bcm1480_scd.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the System Control and Debug module. | ||
| 8 | * | ||
| 9 | * BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003,2004,2005 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _BCM1480_SCD_H | ||
| 33 | #define _BCM1480_SCD_H | ||
| 34 | |||
| 35 | #include "sb1250_defs.h" | ||
| 36 | |||
| 37 | /* ********************************************************************* | ||
| 38 | * Pull in the BCM1250's SCD since lots of stuff is the same. | ||
| 39 | ********************************************************************* */ | ||
| 40 | |||
| 41 | #include "sb1250_scd.h" | ||
| 42 | |||
| 43 | /* ********************************************************************* | ||
| 44 | * Some general notes: | ||
| 45 | * | ||
| 46 | * This file is basically a "what's new" header file. Since the | ||
| 47 | * BCM1250 and the new BCM1480 (and derivatives) share many common | ||
| 48 | * features, this file contains only what's new or changed from | ||
| 49 | * the 1250. (above, you can see that we include the 1250 symbols | ||
| 50 | * to get the base functionality). | ||
| 51 | * | ||
| 52 | * In software, be sure to use the correct symbols, particularly | ||
| 53 | * for blocks that are different between the two chip families. | ||
| 54 | * All BCM1480-specific symbols have _BCM1480_ in their names, | ||
| 55 | * and all BCM1250-specific and "base" functions that are common in | ||
| 56 | * both chips have no special names (this is for compatibility with | ||
| 57 | * older include files). Therefore, if you're working with the | ||
| 58 | * SCD, which is very different on each chip, A_SCD_xxx implies | ||
| 59 | * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 | ||
| 60 | * version. | ||
| 61 | ********************************************************************* */ | ||
| 62 | |||
| 63 | /* ********************************************************************* | ||
| 64 | * System control/debug registers | ||
| 65 | ********************************************************************* */ | ||
| 66 | |||
| 67 | /* | ||
| 68 | * System Identification and Revision Register (Table 12) | ||
| 69 | * Register: SCD_SYSTEM_REVISION | ||
| 70 | * This register is field compatible with the 1250. | ||
| 71 | */ | ||
| 72 | |||
| 73 | /* | ||
| 74 | * New part definitions | ||
| 75 | */ | ||
| 76 | |||
| 77 | #define K_SYS_PART_BCM1480 0x1406 | ||
| 78 | #define K_SYS_PART_BCM1280 0x1206 | ||
| 79 | #define K_SYS_PART_BCM1455 0x1407 | ||
| 80 | #define K_SYS_PART_BCM1255 0x1257 | ||
| 81 | #define K_SYS_PART_BCM1158 0x1156 | ||
| 82 | |||
| 83 | /* | ||
| 84 | * Manufacturing Information Register (Table 14) | ||
| 85 | * Register: SCD_SYSTEM_MANUF | ||
| 86 | */ | ||
| 87 | |||
| 88 | /* | ||
| 89 | * System Configuration Register (Table 15) | ||
| 90 | * Register: SCD_SYSTEM_CFG | ||
| 91 | * Entire register is different from 1250, all new constants below | ||
| 92 | */ | ||
| 93 | |||
| 94 | #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) | ||
| 95 | #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) | ||
| 96 | #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) | ||
| 97 | #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) | ||
| 98 | #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) | ||
| 99 | #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) | ||
| 100 | |||
| 101 | #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) | ||
| 102 | #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) | ||
| 103 | #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) | ||
| 104 | #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) | ||
| 105 | |||
| 106 | #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) | ||
| 107 | #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) | ||
| 108 | #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) | ||
| 109 | #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) | ||
| 110 | |||
| 111 | #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | ||
| 112 | #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) | ||
| 113 | |||
| 114 | #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) | ||
| 115 | #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) | ||
| 116 | #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) | ||
| 117 | #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) | ||
| 118 | #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 | ||
| 119 | #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 | ||
| 120 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 | ||
| 121 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 | ||
| 122 | #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) | ||
| 123 | |||
| 124 | #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) | ||
| 125 | #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) | ||
| 126 | #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | ||
| 127 | #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) | ||
| 128 | #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) | ||
| 129 | #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) | ||
| 130 | |||
| 131 | #define S_BCM1480_SYS_CONFIG 26 | ||
| 132 | #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) | ||
| 133 | #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) | ||
| 134 | #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) | ||
| 135 | |||
| 136 | #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) | ||
| 137 | |||
| 138 | #define S_BCM1480_SYS_NODEID 47 | ||
| 139 | #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) | ||
| 140 | #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) | ||
| 141 | #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) | ||
| 142 | |||
| 143 | #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) | ||
| 144 | #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) | ||
| 145 | #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) | ||
| 146 | #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) | ||
| 147 | #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) | ||
| 148 | #define S_BCM1480_SYS_DISABLECPU0 56 | ||
| 149 | #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) | ||
| 150 | #define S_BCM1480_SYS_DISABLECPU1 57 | ||
| 151 | #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) | ||
| 152 | #define S_BCM1480_SYS_DISABLECPU2 58 | ||
| 153 | #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) | ||
| 154 | #define S_BCM1480_SYS_DISABLECPU3 59 | ||
| 155 | #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) | ||
| 156 | |||
| 157 | #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) | ||
| 158 | #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) | ||
| 159 | #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) | ||
| 160 | #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) | ||
| 161 | |||
| 162 | /* | ||
| 163 | * Scratch Register (Table 16) | ||
| 164 | * Register: SCD_SYSTEM_SCRATCH | ||
| 165 | * Same as BCM1250 | ||
| 166 | */ | ||
| 167 | |||
| 168 | |||
| 169 | /* | ||
| 170 | * Mailbox Registers (Table 17) | ||
| 171 | * Registers: SCD_MBOX_{0,1}_CPU_x | ||
| 172 | * Same as BCM1250 | ||
| 173 | */ | ||
| 174 | |||
| 175 | |||
| 176 | /* | ||
| 177 | * See bcm1480_int.h for interrupt mapper registers. | ||
| 178 | */ | ||
| 179 | |||
| 180 | |||
| 181 | /* | ||
| 182 | * Watchdog Timer Initial Count Registers (Table 23) | ||
| 183 | * Registers: SCD_WDOG_INIT_CNT_x | ||
| 184 | * | ||
| 185 | * The watchdogs are almost the same as the 1250, except | ||
| 186 | * the configuration register has more bits to control the | ||
| 187 | * other CPUs. | ||
| 188 | */ | ||
| 189 | |||
| 190 | |||
| 191 | /* | ||
| 192 | * Watchdog Timer Configuration Registers (Table 25) | ||
| 193 | * Registers: SCD_WDOG_CFG_x | ||
| 194 | */ | ||
| 195 | |||
| 196 | #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) | ||
| 197 | |||
| 198 | #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 | ||
| 199 | #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 200 | #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 201 | #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) | ||
| 202 | |||
| 203 | #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | ||
| 204 | #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 | ||
| 205 | #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 | ||
| 206 | #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 | ||
| 207 | #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 | ||
| 208 | #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 | ||
| 209 | #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 | ||
| 210 | |||
| 211 | |||
| 212 | #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) | ||
| 213 | |||
| 214 | /* | ||
| 215 | * General Timer Initial Count Registers (Table 26) | ||
| 216 | * Registers: SCD_TIMER_INIT_x | ||
| 217 | * | ||
| 218 | * The timer registers are the same as the BCM1250 | ||
| 219 | */ | ||
| 220 | |||
| 221 | |||
| 222 | /* | ||
| 223 | * ZBbus Count Register (Table 29) | ||
| 224 | * Register: ZBBUS_CYCLE_COUNT | ||
| 225 | * | ||
| 226 | * Same as BCM1250 | ||
| 227 | */ | ||
| 228 | |||
| 229 | /* | ||
| 230 | * ZBbus Compare Registers (Table 30) | ||
| 231 | * Registers: ZBBUS_CYCLE_CPx | ||
| 232 | * | ||
| 233 | * Same as BCM1250 | ||
| 234 | */ | ||
| 235 | |||
| 236 | |||
| 237 | /* | ||
| 238 | * System Performance Counter Configuration Register (Table 31) | ||
| 239 | * Register: PERF_CNT_CFG_0 | ||
| 240 | * | ||
| 241 | * SPC_CFG_SRC[0-3] is the same as the 1250. | ||
| 242 | * SPC_CFG_SRC[4-7] only exist on the 1480 | ||
| 243 | * The clear/enable bits are in different locations on the 1250 and 1480. | ||
| 244 | */ | ||
| 245 | |||
| 246 | #define S_SPC_CFG_SRC4 32 | ||
| 247 | #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) | ||
| 248 | #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) | ||
| 249 | #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) | ||
| 250 | |||
| 251 | #define S_SPC_CFG_SRC5 40 | ||
| 252 | #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) | ||
| 253 | #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) | ||
| 254 | #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) | ||
| 255 | |||
| 256 | #define S_SPC_CFG_SRC6 48 | ||
| 257 | #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) | ||
| 258 | #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) | ||
| 259 | #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) | ||
| 260 | |||
| 261 | #define S_SPC_CFG_SRC7 56 | ||
| 262 | #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) | ||
| 263 | #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) | ||
| 264 | #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) | ||
| 265 | |||
| 266 | /* | ||
| 267 | * System Performance Counter Control Register (Table 32) | ||
| 268 | * Register: PERF_CNT_CFG_1 | ||
| 269 | * BCM1480 specific | ||
| 270 | */ | ||
| 271 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) | ||
| 272 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) | ||
| 273 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 274 | #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR | ||
| 275 | #define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE | ||
| 276 | #endif | ||
| 277 | |||
| 278 | /* | ||
| 279 | * System Performance Counters (Table 33) | ||
| 280 | * Registers: PERF_CNT_x | ||
| 281 | */ | ||
| 282 | |||
| 283 | #define S_BCM1480_SPC_CNT_COUNT 0 | ||
| 284 | #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) | ||
| 285 | #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) | ||
| 286 | #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) | ||
| 287 | |||
| 288 | #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) | ||
| 289 | |||
| 290 | |||
| 291 | /* | ||
| 292 | * Bus Watcher Error Status Register (Tables 36, 37) | ||
| 293 | * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG | ||
| 294 | * Same as BCM1250. | ||
| 295 | */ | ||
| 296 | |||
| 297 | /* | ||
| 298 | * Bus Watcher Error Data Registers (Table 38) | ||
| 299 | * Registers: BUS_ERR_DATA_x | ||
| 300 | * Same as BCM1250. | ||
| 301 | */ | ||
| 302 | |||
| 303 | /* | ||
| 304 | * Bus Watcher L2 ECC Counter Register (Table 39) | ||
| 305 | * Register: BUS_L2_ERRORS | ||
| 306 | * Same as BCM1250. | ||
| 307 | */ | ||
| 308 | |||
| 309 | |||
| 310 | /* | ||
| 311 | * Bus Watcher Memory and I/O Error Counter Register (Table 40) | ||
| 312 | * Register: BUS_MEM_IO_ERRORS | ||
| 313 | * Same as BCM1250. | ||
| 314 | */ | ||
| 315 | |||
| 316 | |||
| 317 | /* | ||
| 318 | * Address Trap Registers | ||
| 319 | * | ||
| 320 | * Register layout same as BCM1250, almost. The bus agents | ||
| 321 | * are different, and the address trap configuration bits are | ||
| 322 | * slightly different. | ||
| 323 | */ | ||
| 324 | |||
| 325 | #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) | ||
| 326 | #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) | ||
| 327 | |||
| 328 | #define S_BCM1480_ATRAP_CFG_CNT 0 | ||
| 329 | #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) | ||
| 330 | #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) | ||
| 331 | #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) | ||
| 332 | |||
| 333 | #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | ||
| 334 | #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | ||
| 335 | #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) | ||
| 336 | #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | ||
| 337 | #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | ||
| 338 | |||
| 339 | #define S_BCM1480_ATRAP_CFG_AGENTID 8 | ||
| 340 | #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) | ||
| 341 | #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) | ||
| 342 | #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) | ||
| 343 | |||
| 344 | |||
| 345 | #define K_BCM1480_BUS_AGENT_CPU0 0 | ||
| 346 | #define K_BCM1480_BUS_AGENT_CPU1 1 | ||
| 347 | #define K_BCM1480_BUS_AGENT_NC 2 | ||
| 348 | #define K_BCM1480_BUS_AGENT_IOB 3 | ||
| 349 | #define K_BCM1480_BUS_AGENT_SCD 4 | ||
| 350 | #define K_BCM1480_BUS_AGENT_L2C 6 | ||
| 351 | #define K_BCM1480_BUS_AGENT_MC 7 | ||
| 352 | #define K_BCM1480_BUS_AGENT_CPU2 8 | ||
| 353 | #define K_BCM1480_BUS_AGENT_CPU3 9 | ||
| 354 | #define K_BCM1480_BUS_AGENT_PM 10 | ||
| 355 | |||
| 356 | #define S_BCM1480_ATRAP_CFG_CATTR 12 | ||
| 357 | #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) | ||
| 358 | #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) | ||
| 359 | #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) | ||
| 360 | |||
| 361 | #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 | ||
| 362 | #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 | ||
| 363 | #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 | ||
| 364 | #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 | ||
| 365 | |||
| 366 | #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) | ||
| 367 | |||
| 368 | |||
| 369 | /* | ||
| 370 | * Trace Event Registers (Table 47) | ||
| 371 | * Same as BCM1250. | ||
| 372 | */ | ||
| 373 | |||
| 374 | /* | ||
| 375 | * Trace Sequence Control Registers (Table 48) | ||
| 376 | * Registers: TRACE_SEQUENCE_x | ||
| 377 | * | ||
| 378 | * Same as BCM1250 except for two new fields. | ||
| 379 | */ | ||
| 380 | |||
| 381 | |||
| 382 | #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) | ||
| 383 | |||
| 384 | #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 | ||
| 385 | #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 386 | #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 387 | #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) | ||
| 388 | |||
| 389 | /* | ||
| 390 | * Trace Control Register (Table 49) | ||
| 391 | * Register: TRACE_CFG | ||
| 392 | * | ||
| 393 | * BCM1480 changes to this register (other than location of the CUR_ADDR field) | ||
| 394 | * are defined below. | ||
| 395 | */ | ||
| 396 | |||
| 397 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 | ||
| 398 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 399 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 400 | #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) | ||
| 401 | |||
| 402 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 | ||
| 403 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 | ||
| 404 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 | ||
| 405 | |||
| 406 | #endif /* _BCM1480_SCD_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h new file mode 100644 index 000000000000..ebefe797fc1d --- /dev/null +++ b/arch/mips/include/asm/sibyte/bigsur.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | #ifndef __ASM_SIBYTE_BIGSUR_H | ||
| 19 | #define __ASM_SIBYTE_BIGSUR_H | ||
| 20 | |||
| 21 | #include <asm/sibyte/sb1250.h> | ||
| 22 | #include <asm/sibyte/bcm1480_int.h> | ||
| 23 | |||
| 24 | #ifdef CONFIG_SIBYTE_BIGSUR | ||
| 25 | #define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)" | ||
| 26 | #define SIBYTE_HAVE_PCMCIA 1 | ||
| 27 | #define SIBYTE_HAVE_IDE 1 | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* Generic bus chip selects */ | ||
| 31 | #define LEDS_CS 3 | ||
| 32 | #define LEDS_PHYS 0x100a0000 | ||
| 33 | |||
| 34 | #ifdef SIBYTE_HAVE_IDE | ||
| 35 | #define IDE_CS 4 | ||
| 36 | #define IDE_PHYS 0x100b0000 | ||
| 37 | #define K_GPIO_GB_IDE 4 | ||
| 38 | #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #ifdef SIBYTE_HAVE_PCMCIA | ||
| 42 | #define PCMCIA_CS 6 | ||
| 43 | #define PCMCIA_PHYS 0x11000000 | ||
| 44 | #define K_GPIO_PC_READY 9 | ||
| 45 | #define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) | ||
| 46 | #endif | ||
| 47 | |||
| 48 | #endif /* __ASM_SIBYTE_BIGSUR_H */ | ||
| 49 | |||
diff --git a/arch/mips/include/asm/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h new file mode 100644 index 000000000000..25372ae0e814 --- /dev/null +++ b/arch/mips/include/asm/sibyte/board.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _SIBYTE_BOARD_H | ||
| 20 | #define _SIBYTE_BOARD_H | ||
| 21 | |||
| 22 | #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \ | ||
| 23 | defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR) | ||
| 24 | #include <asm/sibyte/swarm.h> | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE) | ||
| 28 | #include <asm/sibyte/sentosa.h> | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #ifdef CONFIG_SIBYTE_CARMEL | ||
| 32 | #include <asm/sibyte/carmel.h> | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #ifdef CONFIG_SIBYTE_BIGSUR | ||
| 36 | #include <asm/sibyte/bigsur.h> | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #ifdef __ASSEMBLY__ | ||
| 40 | |||
| 41 | #ifdef LEDS_PHYS | ||
| 42 | #define setleds(t0, t1, c0, c1, c2, c3) \ | ||
| 43 | li t0, (LEDS_PHYS|0xa0000000); \ | ||
| 44 | li t1, c0; \ | ||
| 45 | sb t1, 0x18(t0); \ | ||
| 46 | li t1, c1; \ | ||
| 47 | sb t1, 0x10(t0); \ | ||
| 48 | li t1, c2; \ | ||
| 49 | sb t1, 0x08(t0); \ | ||
| 50 | li t1, c3; \ | ||
| 51 | sb t1, 0x00(t0) | ||
| 52 | #else | ||
| 53 | #define setleds(t0, t1, c0, c1, c2, c3) | ||
| 54 | #endif /* LEDS_PHYS */ | ||
| 55 | |||
| 56 | #else | ||
| 57 | |||
| 58 | void swarm_setup(void); | ||
| 59 | |||
| 60 | #ifdef LEDS_PHYS | ||
| 61 | extern void setleds(char *str); | ||
| 62 | #else | ||
| 63 | #define setleds(s) do { } while (0) | ||
| 64 | #endif /* LEDS_PHYS */ | ||
| 65 | |||
| 66 | #endif /* __ASSEMBLY__ */ | ||
| 67 | |||
| 68 | #endif /* _SIBYTE_BOARD_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h new file mode 100644 index 000000000000..11cad71323e8 --- /dev/null +++ b/arch/mips/include/asm/sibyte/carmel.h | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2002 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | #ifndef __ASM_SIBYTE_CARMEL_H | ||
| 19 | #define __ASM_SIBYTE_CARMEL_H | ||
| 20 | |||
| 21 | #include <asm/sibyte/sb1250.h> | ||
| 22 | #include <asm/sibyte/sb1250_int.h> | ||
| 23 | |||
| 24 | #define SIBYTE_BOARD_NAME "Carmel" | ||
| 25 | |||
| 26 | #define GPIO_PHY_INTERRUPT 2 | ||
| 27 | #define GPIO_NONMASKABLE_INT 3 | ||
| 28 | #define GPIO_CF_INSERTED 6 | ||
| 29 | #define GPIO_MONTEREY_RESET 7 | ||
| 30 | #define GPIO_QUADUART_INT 8 | ||
| 31 | #define GPIO_CF_INT 9 | ||
| 32 | #define GPIO_FPGA_CCLK 10 | ||
| 33 | #define GPIO_FPGA_DOUT 11 | ||
| 34 | #define GPIO_FPGA_DIN 12 | ||
| 35 | #define GPIO_FPGA_PGM 13 | ||
| 36 | #define GPIO_FPGA_DONE 14 | ||
| 37 | #define GPIO_FPGA_INIT 15 | ||
| 38 | |||
| 39 | #define LEDS_CS 2 | ||
| 40 | #define LEDS_PHYS 0x100C0000 | ||
| 41 | #define MLEDS_CS 3 | ||
| 42 | #define MLEDS_PHYS 0x100A0000 | ||
| 43 | #define UART_CS 4 | ||
| 44 | #define UART_PHYS 0x100D0000 | ||
| 45 | #define ARAVALI_CS 5 | ||
| 46 | #define ARAVALI_PHYS 0x11000000 | ||
| 47 | #define IDE_CS 6 | ||
| 48 | #define IDE_PHYS 0x100B0000 | ||
| 49 | #define ARAVALI2_CS 7 | ||
| 50 | #define ARAVALI2_PHYS 0x100E0000 | ||
| 51 | |||
| 52 | #if defined(CONFIG_SIBYTE_CARMEL) | ||
| 53 | #define K_GPIO_GB_IDE 9 | ||
| 54 | #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) | ||
| 55 | #endif | ||
| 56 | |||
| 57 | |||
| 58 | #endif /* __ASM_SIBYTE_CARMEL_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h new file mode 100644 index 000000000000..80c1a052662a --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _ASM_SIBYTE_SB1250_H | ||
| 20 | #define _ASM_SIBYTE_SB1250_H | ||
| 21 | |||
| 22 | /* | ||
| 23 | * yymmddpp: year, month, day, patch. | ||
| 24 | * should sync with Makefile EXTRAVERSION | ||
| 25 | */ | ||
| 26 | #define SIBYTE_RELEASE 0x02111403 | ||
| 27 | |||
| 28 | #define SB1250_NR_IRQS 64 | ||
| 29 | |||
| 30 | #define BCM1480_NR_IRQS 128 | ||
| 31 | #define BCM1480_NR_IRQS_HALF 64 | ||
| 32 | |||
| 33 | #define SB1250_DUART_MINOR_BASE 64 | ||
| 34 | |||
| 35 | #ifndef __ASSEMBLY__ | ||
| 36 | |||
| 37 | #include <asm/addrspace.h> | ||
| 38 | |||
| 39 | /* For revision/pass information */ | ||
| 40 | #include <asm/sibyte/sb1250_scd.h> | ||
| 41 | #include <asm/sibyte/bcm1480_scd.h> | ||
| 42 | extern unsigned int sb1_pass; | ||
| 43 | extern unsigned int soc_pass; | ||
| 44 | extern unsigned int soc_type; | ||
| 45 | extern unsigned int periph_rev; | ||
| 46 | extern unsigned int zbbus_mhz; | ||
| 47 | |||
| 48 | extern void sb1250_time_init(void); | ||
| 49 | extern void sb1250_mask_irq(int cpu, int irq); | ||
| 50 | extern void sb1250_unmask_irq(int cpu, int irq); | ||
| 51 | |||
| 52 | extern void bcm1480_time_init(void); | ||
| 53 | extern void bcm1480_mask_irq(int cpu, int irq); | ||
| 54 | extern void bcm1480_unmask_irq(int cpu, int irq); | ||
| 55 | |||
| 56 | #define AT_spin \ | ||
| 57 | __asm__ __volatile__ ( \ | ||
| 58 | ".set noat\n" \ | ||
| 59 | "li $at, 0\n" \ | ||
| 60 | "1: beqz $at, 1b\n" \ | ||
| 61 | ".set at\n" \ | ||
| 62 | ) | ||
| 63 | |||
| 64 | #endif | ||
| 65 | |||
| 66 | #define IOADDR(a) ((void __iomem *)(IO_BASE + (a))) | ||
| 67 | |||
| 68 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h new file mode 100644 index 000000000000..09365f9111fa --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_defs.h | |||
| @@ -0,0 +1,259 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Global constants and macros File: sb1250_defs.h | ||
| 5 | * | ||
| 6 | * This file contains macros and definitions used by the other | ||
| 7 | * include files. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _SB1250_DEFS_H | ||
| 33 | #define _SB1250_DEFS_H | ||
| 34 | |||
| 35 | /* | ||
| 36 | * These headers require ANSI C89 string concatenation, and GCC or other | ||
| 37 | * 'long long' (64-bit integer) support. | ||
| 38 | */ | ||
| 39 | #if !defined(__STDC__) && !defined(_MSC_VER) | ||
| 40 | #error SiByte headers require ANSI C89 support | ||
| 41 | #endif | ||
| 42 | |||
| 43 | |||
| 44 | /* ********************************************************************* | ||
| 45 | * Macros for feature tests, used to enable include file features | ||
| 46 | * for chip features only present in certain chip revisions. | ||
| 47 | * | ||
| 48 | * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision | ||
| 49 | * which is to be exposed by the headers. If undefined, it defaults to | ||
| 50 | * "all features." | ||
| 51 | * | ||
| 52 | * Use like: | ||
| 53 | * | ||
| 54 | * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1 | ||
| 55 | * | ||
| 56 | * Generate defines only for that revision of chip. | ||
| 57 | * | ||
| 58 | * #if SIBYTE_HDR_FEATURE(chip,pass) | ||
| 59 | * | ||
| 60 | * True if header features for that revision or later of | ||
| 61 | * that particular chip type are enabled in SIBYTE_HDR_FEATURES. | ||
| 62 | * (Use this to bracket #defines for features present in a given | ||
| 63 | * revision and later.) | ||
| 64 | * | ||
| 65 | * Note that there is no implied ordering between chip types. | ||
| 66 | * | ||
| 67 | * Note also that 'chip' and 'pass' must textually exactly | ||
| 68 | * match the defines below. So, for example, | ||
| 69 | * SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but | ||
| 70 | * SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons). | ||
| 71 | * | ||
| 72 | * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass) | ||
| 73 | * | ||
| 74 | * Same as SIBYTE_HDR_FEATURE, but true for the named revision | ||
| 75 | * and earlier revisions of the named chip type. | ||
| 76 | * | ||
| 77 | * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass) | ||
| 78 | * | ||
| 79 | * Same as SIBYTE_HDR_FEATURE, but only true for the named | ||
| 80 | * revision of the named chip type. (Note that this CANNOT | ||
| 81 | * be used to verify that you're compiling only for that | ||
| 82 | * particular chip/revision. It will be true any time this | ||
| 83 | * chip/revision is included in SIBYTE_HDR_FEATURES.) | ||
| 84 | * | ||
| 85 | * #if SIBYTE_HDR_FEATURE_CHIP(chip) | ||
| 86 | * | ||
| 87 | * True if header features for (any revision of) that chip type | ||
| 88 | * are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket | ||
| 89 | * #defines for features specific to a given chip type.) | ||
| 90 | * | ||
| 91 | * Mask values currently include room for additional revisions of each | ||
| 92 | * chip type, but can be renumbered at will. Note that they MUST fit | ||
| 93 | * into 31 bits and may not include C type constructs, for safe use in | ||
| 94 | * CPP conditionals. Bit positions within chip types DO indicate | ||
| 95 | * ordering, so be careful when adding support for new minor revs. | ||
| 96 | ********************************************************************* */ | ||
| 97 | |||
| 98 | #define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff | ||
| 99 | #define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001 | ||
| 100 | #define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002 | ||
| 101 | #define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004 | ||
| 102 | |||
| 103 | #define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00 | ||
| 104 | #define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100 | ||
| 105 | |||
| 106 | #define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000 | ||
| 107 | #define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000 | ||
| 108 | #define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000 | ||
| 109 | |||
| 110 | /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */ | ||
| 111 | #define SIBYTE_HDR_FMASK(chip, pass) \ | ||
| 112 | (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass) | ||
| 113 | #define SIBYTE_HDR_FMASK_ALLREVS(chip) \ | ||
| 114 | (SIBYTE_HDR_FMASK_ ## chip ## _ALL) | ||
| 115 | |||
| 116 | /* Default constant value for all chips, all revisions */ | ||
| 117 | #define SIBYTE_HDR_FMASK_ALL \ | ||
| 118 | (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \ | ||
| 119 | | SIBYTE_HDR_FMASK_1480_ALL) | ||
| 120 | |||
| 121 | /* This one is used for the "original" BCM1250/BCM112x chips. We use this | ||
| 122 | to weed out constants and macros that do not exist on later chips like | ||
| 123 | the BCM1480 */ | ||
| 124 | #define SIBYTE_HDR_FMASK_1250_112x_ALL \ | ||
| 125 | (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL) | ||
| 126 | #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL | ||
| 127 | |||
| 128 | #ifndef SIBYTE_HDR_FEATURES | ||
| 129 | #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL | ||
| 130 | #endif | ||
| 131 | |||
| 132 | |||
| 133 | /* Bit mask for revisions of chip exclusively before the named revision. */ | ||
| 134 | #define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \ | ||
| 135 | ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip)) | ||
| 136 | |||
| 137 | /* Bit mask for revisions of chip exclusively after the named revision. */ | ||
| 138 | #define SIBYTE_HDR_FMASK_AFTER(chip, pass) \ | ||
| 139 | (~(SIBYTE_HDR_FMASK(chip, pass) \ | ||
| 140 | | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip)) | ||
| 141 | |||
| 142 | |||
| 143 | /* True if header features enabled for (any revision of) that chip type. */ | ||
| 144 | #define SIBYTE_HDR_FEATURE_CHIP(chip) \ | ||
| 145 | (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES)) | ||
| 146 | |||
| 147 | /* True for all versions of the BCM1250 and BCM1125, but not true for | ||
| 148 | anything else */ | ||
| 149 | #define SIBYTE_HDR_FEATURE_1250_112x \ | ||
| 150 | (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) | ||
| 151 | /* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */ | ||
| 152 | |||
| 153 | /* True if header features enabled for that rev or later, inclusive. */ | ||
| 154 | #define SIBYTE_HDR_FEATURE(chip, pass) \ | ||
| 155 | (!! ((SIBYTE_HDR_FMASK(chip, pass) \ | ||
| 156 | | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES)) | ||
| 157 | |||
| 158 | /* True if header features enabled for exactly that rev. */ | ||
| 159 | #define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \ | ||
| 160 | (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES)) | ||
| 161 | |||
| 162 | /* True if header features enabled for that rev or before, inclusive. */ | ||
| 163 | #define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \ | ||
| 164 | (!! ((SIBYTE_HDR_FMASK(chip, pass) \ | ||
| 165 | | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES)) | ||
| 166 | |||
| 167 | |||
| 168 | /* ********************************************************************* | ||
| 169 | * Naming schemes for constants in these files: | ||
| 170 | * | ||
| 171 | * M_xxx MASK constant (identifies bits in a register). | ||
| 172 | * For multi-bit fields, all bits in the field will | ||
| 173 | * be set. | ||
| 174 | * | ||
| 175 | * K_xxx "Code" constant (value for data in a multi-bit | ||
| 176 | * field). The value is right justified. | ||
| 177 | * | ||
| 178 | * V_xxx "Value" constant. This is the same as the | ||
| 179 | * corresponding "K_xxx" constant, except it is | ||
| 180 | * shifted to the correct position in the register. | ||
| 181 | * | ||
| 182 | * S_xxx SHIFT constant. This is the number of bits that | ||
| 183 | * a field value (code) needs to be shifted | ||
| 184 | * (towards the left) to put the value in the right | ||
| 185 | * position for the register. | ||
| 186 | * | ||
| 187 | * A_xxx ADDRESS constant. This will be a physical | ||
| 188 | * address. Use the PHYS_TO_K1 macro to generate | ||
| 189 | * a K1SEG address. | ||
| 190 | * | ||
| 191 | * R_xxx RELATIVE offset constant. This is an offset from | ||
| 192 | * an A_xxx constant (usually the first register in | ||
| 193 | * a group). | ||
| 194 | * | ||
| 195 | * G_xxx(X) GET value. This macro obtains a multi-bit field | ||
| 196 | * from a register, masks it, and shifts it to | ||
| 197 | * the bottom of the register (retrieving a K_xxx | ||
| 198 | * value, for example). | ||
| 199 | * | ||
| 200 | * V_xxx(X) VALUE. This macro computes the value of a | ||
| 201 | * K_xxx constant shifted to the correct position | ||
| 202 | * in the register. | ||
| 203 | ********************************************************************* */ | ||
| 204 | |||
| 205 | |||
| 206 | |||
| 207 | |||
| 208 | /* | ||
| 209 | * Cast to 64-bit number. Presumably the syntax is different in | ||
| 210 | * assembly language. | ||
| 211 | * | ||
| 212 | * Note: you'll need to define uint32_t and uint64_t in your headers. | ||
| 213 | */ | ||
| 214 | |||
| 215 | #if !defined(__ASSEMBLY__) | ||
| 216 | #define _SB_MAKE64(x) ((uint64_t)(x)) | ||
| 217 | #define _SB_MAKE32(x) ((uint32_t)(x)) | ||
| 218 | #else | ||
| 219 | #define _SB_MAKE64(x) (x) | ||
| 220 | #define _SB_MAKE32(x) (x) | ||
| 221 | #endif | ||
| 222 | |||
| 223 | |||
| 224 | /* | ||
| 225 | * Make a mask for 1 bit at position 'n' | ||
| 226 | */ | ||
| 227 | |||
| 228 | #define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n)) | ||
| 229 | #define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n)) | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Make a mask for 'v' bits at position 'n' | ||
| 233 | */ | ||
| 234 | |||
| 235 | #define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n)) | ||
| 236 | #define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n)) | ||
| 237 | |||
| 238 | /* | ||
| 239 | * Make a value at 'v' at bit position 'n' | ||
| 240 | */ | ||
| 241 | |||
| 242 | #define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n)) | ||
| 243 | #define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n)) | ||
| 244 | |||
| 245 | #define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n)) | ||
| 246 | #define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n)) | ||
| 247 | |||
| 248 | /* | ||
| 249 | * Macros to read/write on-chip registers | ||
| 250 | * XXX should we do the PHYS_TO_K1 here? | ||
| 251 | */ | ||
| 252 | |||
| 253 | |||
| 254 | #if defined(__mips64) && !defined(__ASSEMBLY__) | ||
| 255 | #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) | ||
| 256 | #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) | ||
| 257 | #endif /* __ASSEMBLY__ */ | ||
| 258 | |||
| 259 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h new file mode 100644 index 000000000000..bad56171d747 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_dma.h | |||
| @@ -0,0 +1,594 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * DMA definitions File: sb1250_dma.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * programming the SB1250's DMA controllers, both the data mover | ||
| 8 | * and the Ethernet DMA. | ||
| 9 | * | ||
| 10 | * SB1250 specification level: User's manual 10/21/02 | ||
| 11 | * BCM1280 specification level: User's manual 11/24/03 | ||
| 12 | * | ||
| 13 | ********************************************************************* | ||
| 14 | * | ||
| 15 | * Copyright 2000,2001,2002,2003 | ||
| 16 | * Broadcom Corporation. All rights reserved. | ||
| 17 | * | ||
| 18 | * This program is free software; you can redistribute it and/or | ||
| 19 | * modify it under the terms of the GNU General Public License as | ||
| 20 | * published by the Free Software Foundation; either version 2 of | ||
| 21 | * the License, or (at your option) any later version. | ||
| 22 | * | ||
| 23 | * This program is distributed in the hope that it will be useful, | ||
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 26 | * GNU General Public License for more details. | ||
| 27 | * | ||
| 28 | * You should have received a copy of the GNU General Public License | ||
| 29 | * along with this program; if not, write to the Free Software | ||
| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 31 | * MA 02111-1307 USA | ||
| 32 | ********************************************************************* */ | ||
| 33 | |||
| 34 | |||
| 35 | #ifndef _SB1250_DMA_H | ||
| 36 | #define _SB1250_DMA_H | ||
| 37 | |||
| 38 | |||
| 39 | #include "sb1250_defs.h" | ||
| 40 | |||
| 41 | /* ********************************************************************* | ||
| 42 | * DMA Registers | ||
| 43 | ********************************************************************* */ | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Ethernet and Serial DMA Configuration Register 0 (Table 7-4) | ||
| 47 | * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 | ||
| 48 | * Registers: DMA_CONFIG0_MAC_x_TX_CH_0 | ||
| 49 | * Registers: DMA_CONFIG0_SER_x_RX | ||
| 50 | * Registers: DMA_CONFIG0_SER_x_TX | ||
| 51 | */ | ||
| 52 | |||
| 53 | |||
| 54 | #define M_DMA_DROP _SB_MAKEMASK1(0) | ||
| 55 | |||
| 56 | #define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1) | ||
| 57 | #define M_DMA_RESERVED1 _SB_MAKEMASK1(2) | ||
| 58 | |||
| 59 | #define S_DMA_DESC_TYPE _SB_MAKE64(1) | ||
| 60 | #define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE) | ||
| 61 | #define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE) | ||
| 62 | #define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE) | ||
| 63 | |||
| 64 | #define K_DMA_DESC_TYPE_RING_AL 0 | ||
| 65 | #define K_DMA_DESC_TYPE_CHAIN_AL 1 | ||
| 66 | |||
| 67 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 68 | #define K_DMA_DESC_TYPE_RING_UAL_WI 2 | ||
| 69 | #define K_DMA_DESC_TYPE_RING_UAL_RMW 3 | ||
| 70 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 71 | |||
| 72 | #define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3) | ||
| 73 | #define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4) | ||
| 74 | #define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5) | ||
| 75 | #define M_DMA_TBX_EN _SB_MAKEMASK1(6) | ||
| 76 | #define M_DMA_TDX_EN _SB_MAKEMASK1(7) | ||
| 77 | |||
| 78 | #define S_DMA_INT_PKTCNT _SB_MAKE64(8) | ||
| 79 | #define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT) | ||
| 80 | #define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT) | ||
| 81 | #define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT) | ||
| 82 | |||
| 83 | #define S_DMA_RINGSZ _SB_MAKE64(16) | ||
| 84 | #define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ) | ||
| 85 | #define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ) | ||
| 86 | #define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ) | ||
| 87 | |||
| 88 | #define S_DMA_HIGH_WATERMARK _SB_MAKE64(32) | ||
| 89 | #define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK) | ||
| 90 | #define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK) | ||
| 91 | #define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK) | ||
| 92 | |||
| 93 | #define S_DMA_LOW_WATERMARK _SB_MAKE64(48) | ||
| 94 | #define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK) | ||
| 95 | #define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK) | ||
| 96 | #define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK) | ||
| 97 | |||
| 98 | /* | ||
| 99 | * Ethernet and Serial DMA Configuration Register 1 (Table 7-5) | ||
| 100 | * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 | ||
| 101 | * Registers: DMA_CONFIG1_DMA_x_TX_CH_0 | ||
| 102 | * Registers: DMA_CONFIG1_SER_x_RX | ||
| 103 | * Registers: DMA_CONFIG1_SER_x_TX | ||
| 104 | */ | ||
| 105 | |||
| 106 | #define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0) | ||
| 107 | #define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1) | ||
| 108 | #define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2) | ||
| 109 | #define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3) | ||
| 110 | #define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4) | ||
| 111 | #define M_DMA_L2CA _SB_MAKEMASK1(5) | ||
| 112 | |||
| 113 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 114 | #define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6) | ||
| 115 | #define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6) | ||
| 116 | #define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7) | ||
| 117 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 118 | |||
| 119 | #define M_DMA_MBZ1 _SB_MAKEMASK(6, 15) | ||
| 120 | |||
| 121 | #define S_DMA_HDR_SIZE _SB_MAKE64(21) | ||
| 122 | #define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE) | ||
| 123 | #define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE) | ||
| 124 | #define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE) | ||
| 125 | |||
| 126 | #define M_DMA_MBZ2 _SB_MAKEMASK(5, 32) | ||
| 127 | |||
| 128 | #define S_DMA_ASICXFR_SIZE _SB_MAKE64(37) | ||
| 129 | #define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE) | ||
| 130 | #define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE) | ||
| 131 | #define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE) | ||
| 132 | |||
| 133 | #define S_DMA_INT_TIMEOUT _SB_MAKE64(48) | ||
| 134 | #define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT) | ||
| 135 | #define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT) | ||
| 136 | #define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT) | ||
| 137 | |||
| 138 | /* | ||
| 139 | * Ethernet and Serial DMA Descriptor base address (Table 7-6) | ||
| 140 | */ | ||
| 141 | |||
| 142 | #define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0) | ||
| 143 | |||
| 144 | |||
| 145 | /* | ||
| 146 | * ASIC Mode Base Address (Table 7-7) | ||
| 147 | */ | ||
| 148 | |||
| 149 | #define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0) | ||
| 150 | |||
| 151 | /* | ||
| 152 | * DMA Descriptor Count Registers (Table 7-8) | ||
| 153 | */ | ||
| 154 | |||
| 155 | /* No bitfields */ | ||
| 156 | |||
| 157 | |||
| 158 | /* | ||
| 159 | * Current Descriptor Address Register (Table 7-11) | ||
| 160 | */ | ||
| 161 | |||
| 162 | #define S_DMA_CURDSCR_ADDR _SB_MAKE64(0) | ||
| 163 | #define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR) | ||
| 164 | #define S_DMA_CURDSCR_COUNT _SB_MAKE64(40) | ||
| 165 | #define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT) | ||
| 166 | |||
| 167 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 168 | #define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56) | ||
| 169 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Receive Packet Drop Registers | ||
| 173 | */ | ||
| 174 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 175 | #define S_DMA_OODLOST_RX _SB_MAKE64(0) | ||
| 176 | #define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX) | ||
| 177 | #define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX) | ||
| 178 | |||
| 179 | #define S_DMA_EOP_COUNT_RX _SB_MAKE64(16) | ||
| 180 | #define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX) | ||
| 181 | #define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX) | ||
| 182 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 183 | |||
| 184 | /* ********************************************************************* | ||
| 185 | * DMA Descriptors | ||
| 186 | ********************************************************************* */ | ||
| 187 | |||
| 188 | /* | ||
| 189 | * Descriptor doubleword "A" (Table 7-12) | ||
| 190 | */ | ||
| 191 | |||
| 192 | #define S_DMA_DSCRA_OFFSET _SB_MAKE64(0) | ||
| 193 | #define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET) | ||
| 194 | #define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET) | ||
| 195 | #define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET) | ||
| 196 | |||
| 197 | /* Note: Don't shift the address over, just mask it with the mask below */ | ||
| 198 | #define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5) | ||
| 199 | #define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR) | ||
| 200 | |||
| 201 | #define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR) | ||
| 202 | |||
| 203 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 204 | #define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0) | ||
| 205 | #define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA) | ||
| 206 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 207 | |||
| 208 | #define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40) | ||
| 209 | #define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE) | ||
| 210 | #define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE) | ||
| 211 | #define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE) | ||
| 212 | |||
| 213 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 214 | #define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40) | ||
| 215 | #define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT) | ||
| 216 | #define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT) | ||
| 217 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 218 | |||
| 219 | #define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49) | ||
| 220 | #define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50) | ||
| 221 | |||
| 222 | #define S_DMA_DSCRA_STATUS _SB_MAKE64(51) | ||
| 223 | #define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS) | ||
| 224 | #define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS) | ||
| 225 | #define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS) | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Descriptor doubleword "B" (Table 7-13) | ||
| 229 | */ | ||
| 230 | |||
| 231 | |||
| 232 | #define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0) | ||
| 233 | #define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS) | ||
| 234 | #define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS) | ||
| 235 | #define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS) | ||
| 236 | |||
| 237 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 238 | #define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8) | ||
| 239 | #define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE) | ||
| 240 | #define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE) | ||
| 241 | #define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE) | ||
| 242 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 243 | |||
| 244 | #define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10) | ||
| 245 | |||
| 246 | /* Note: Don't shift the address over, just mask it with the mask below */ | ||
| 247 | #define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5) | ||
| 248 | #define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR) | ||
| 249 | |||
| 250 | #define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40) | ||
| 251 | #define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE) | ||
| 252 | #define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE) | ||
| 253 | #define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE) | ||
| 254 | |||
| 255 | #define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49) | ||
| 256 | |||
| 257 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 258 | #define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48) | ||
| 259 | #define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB) | ||
| 260 | #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB) | ||
| 261 | #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB) | ||
| 262 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 263 | |||
| 264 | #define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50) | ||
| 265 | #define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE) | ||
| 266 | #define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE) | ||
| 267 | #define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE) | ||
| 268 | |||
| 269 | /* | ||
| 270 | * from pass2 some bits in dscr_b are also used for rx status | ||
| 271 | */ | ||
| 272 | #define S_DMA_DSCRB_STATUS _SB_MAKE64(0) | ||
| 273 | #define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS) | ||
| 274 | #define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS) | ||
| 275 | #define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS) | ||
| 276 | |||
| 277 | /* | ||
| 278 | * Ethernet Descriptor Status Bits (Table 7-15) | ||
| 279 | */ | ||
| 280 | |||
| 281 | #define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51) | ||
| 282 | #define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52) | ||
| 283 | |||
| 284 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 285 | /* Note: This bit is in the DSCR_B options field */ | ||
| 286 | #define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0) | ||
| 287 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 288 | |||
| 289 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 290 | /* Note: These bits are in the DSCR_B options field */ | ||
| 291 | #define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1) | ||
| 292 | #define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2) | ||
| 293 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 294 | |||
| 295 | #define S_DMA_ETHRX_RXCH 53 | ||
| 296 | #define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH) | ||
| 297 | #define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH) | ||
| 298 | #define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH) | ||
| 299 | |||
| 300 | #define S_DMA_ETHRX_PKTTYPE 55 | ||
| 301 | #define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE) | ||
| 302 | #define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE) | ||
| 303 | #define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE) | ||
| 304 | |||
| 305 | #define K_DMA_ETHRX_PKTTYPE_IPV4 0 | ||
| 306 | #define K_DMA_ETHRX_PKTTYPE_ARPV4 1 | ||
| 307 | #define K_DMA_ETHRX_PKTTYPE_802 2 | ||
| 308 | #define K_DMA_ETHRX_PKTTYPE_OTHER 3 | ||
| 309 | #define K_DMA_ETHRX_PKTTYPE_USER0 4 | ||
| 310 | #define K_DMA_ETHRX_PKTTYPE_USER1 5 | ||
| 311 | #define K_DMA_ETHRX_PKTTYPE_USER2 6 | ||
| 312 | #define K_DMA_ETHRX_PKTTYPE_USER3 7 | ||
| 313 | |||
| 314 | #define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58) | ||
| 315 | #define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59) | ||
| 316 | #define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60) | ||
| 317 | #define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61) | ||
| 318 | #define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62) | ||
| 319 | #define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63) | ||
| 320 | |||
| 321 | /* | ||
| 322 | * Ethernet Transmit Status Bits (Table 7-16) | ||
| 323 | */ | ||
| 324 | |||
| 325 | #define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63) | ||
| 326 | |||
| 327 | /* | ||
| 328 | * Ethernet Transmit Options (Table 7-17) | ||
| 329 | */ | ||
| 330 | |||
| 331 | #define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00) | ||
| 332 | #define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01) | ||
| 333 | #define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02) | ||
| 334 | #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03) | ||
| 335 | #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04) | ||
| 336 | #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05) | ||
| 337 | #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6) | ||
| 338 | #define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07) | ||
| 339 | #define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08) | ||
| 340 | #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09) | ||
| 341 | #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A) | ||
| 342 | #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B) | ||
| 343 | #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C) | ||
| 344 | #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D) | ||
| 345 | #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E) | ||
| 346 | #define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F) | ||
| 347 | |||
| 348 | /* | ||
| 349 | * Serial Receive Options (Table 7-18) | ||
| 350 | */ | ||
| 351 | #define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56) | ||
| 352 | #define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57) | ||
| 353 | #define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58) | ||
| 354 | #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59) | ||
| 355 | #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60) | ||
| 356 | #define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61) | ||
| 357 | #define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62) | ||
| 358 | #define M_DMA_SERRX_SOP _SB_MAKEMASK1(63) | ||
| 359 | |||
| 360 | /* | ||
| 361 | * Serial Transmit Status Bits (Table 7-20) | ||
| 362 | */ | ||
| 363 | |||
| 364 | #define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63) | ||
| 365 | |||
| 366 | /* | ||
| 367 | * Serial Transmit Options (Table 7-21) | ||
| 368 | */ | ||
| 369 | |||
| 370 | #define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0) | ||
| 371 | #define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1) | ||
| 372 | #define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2) | ||
| 373 | #define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3) | ||
| 374 | |||
| 375 | |||
| 376 | /* ********************************************************************* | ||
| 377 | * Data Mover Registers | ||
| 378 | ********************************************************************* */ | ||
| 379 | |||
| 380 | /* | ||
| 381 | * Data Mover Descriptor Base Address Register (Table 7-22) | ||
| 382 | * Register: DM_DSCR_BASE_0 | ||
| 383 | * Register: DM_DSCR_BASE_1 | ||
| 384 | * Register: DM_DSCR_BASE_2 | ||
| 385 | * Register: DM_DSCR_BASE_3 | ||
| 386 | */ | ||
| 387 | |||
| 388 | #define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0) | ||
| 389 | |||
| 390 | /* Note: Just mask the base address and then OR it in. */ | ||
| 391 | #define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4) | ||
| 392 | #define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR) | ||
| 393 | |||
| 394 | #define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40) | ||
| 395 | #define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ) | ||
| 396 | #define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ) | ||
| 397 | #define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ) | ||
| 398 | |||
| 399 | #define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56) | ||
| 400 | #define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY) | ||
| 401 | #define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY) | ||
| 402 | #define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY) | ||
| 403 | |||
| 404 | #define K_DM_DSCR_BASE_PRIORITY_1 0 | ||
| 405 | #define K_DM_DSCR_BASE_PRIORITY_2 1 | ||
| 406 | #define K_DM_DSCR_BASE_PRIORITY_4 2 | ||
| 407 | #define K_DM_DSCR_BASE_PRIORITY_8 3 | ||
| 408 | #define K_DM_DSCR_BASE_PRIORITY_16 4 | ||
| 409 | |||
| 410 | #define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59) | ||
| 411 | #define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60) | ||
| 412 | #define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */ | ||
| 413 | #define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */ | ||
| 414 | #define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62) | ||
| 415 | #define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63) | ||
| 416 | |||
| 417 | /* | ||
| 418 | * Data Mover Descriptor Count Register (Table 7-25) | ||
| 419 | */ | ||
| 420 | |||
| 421 | /* no bitfields */ | ||
| 422 | |||
| 423 | /* | ||
| 424 | * Data Mover Current Descriptor Address (Table 7-24) | ||
| 425 | * Register: DM_CUR_DSCR_ADDR_0 | ||
| 426 | * Register: DM_CUR_DSCR_ADDR_1 | ||
| 427 | * Register: DM_CUR_DSCR_ADDR_2 | ||
| 428 | * Register: DM_CUR_DSCR_ADDR_3 | ||
| 429 | */ | ||
| 430 | |||
| 431 | #define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0) | ||
| 432 | #define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR) | ||
| 433 | |||
| 434 | #define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48) | ||
| 435 | #define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT) | ||
| 436 | #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT) | ||
| 437 | #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\ | ||
| 438 | M_DM_CUR_DSCR_DSCR_COUNT) | ||
| 439 | |||
| 440 | |||
| 441 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 442 | /* | ||
| 443 | * Data Mover Channel Partial Result Registers | ||
| 444 | * Register: DM_PARTIAL_0 | ||
| 445 | * Register: DM_PARTIAL_1 | ||
| 446 | * Register: DM_PARTIAL_2 | ||
| 447 | * Register: DM_PARTIAL_3 | ||
| 448 | */ | ||
| 449 | #define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0) | ||
| 450 | #define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL) | ||
| 451 | #define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL) | ||
| 452 | #define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\ | ||
| 453 | M_DM_PARTIAL_CRC_PARTIAL) | ||
| 454 | |||
| 455 | #define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32) | ||
| 456 | #define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL) | ||
| 457 | #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL) | ||
| 458 | #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\ | ||
| 459 | M_DM_PARTIAL_TCPCS_PARTIAL) | ||
| 460 | |||
| 461 | #define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48) | ||
| 462 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 463 | |||
| 464 | |||
| 465 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 466 | /* | ||
| 467 | * Data Mover CRC Definition Registers | ||
| 468 | * Register: CRC_DEF_0 | ||
| 469 | * Register: CRC_DEF_1 | ||
| 470 | */ | ||
| 471 | #define S_CRC_DEF_CRC_INIT _SB_MAKE64(0) | ||
| 472 | #define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT) | ||
| 473 | #define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT) | ||
| 474 | #define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\ | ||
| 475 | M_CRC_DEF_CRC_INIT) | ||
| 476 | |||
| 477 | #define S_CRC_DEF_CRC_POLY _SB_MAKE64(32) | ||
| 478 | #define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY) | ||
| 479 | #define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY) | ||
| 480 | #define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\ | ||
| 481 | M_CRC_DEF_CRC_POLY) | ||
| 482 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 483 | |||
| 484 | |||
| 485 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 486 | /* | ||
| 487 | * Data Mover CRC/Checksum Definition Registers | ||
| 488 | * Register: CTCP_DEF_0 | ||
| 489 | * Register: CTCP_DEF_1 | ||
| 490 | */ | ||
| 491 | #define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0) | ||
| 492 | #define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR) | ||
| 493 | #define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR) | ||
| 494 | #define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\ | ||
| 495 | M_CTCP_DEF_CRC_TXOR) | ||
| 496 | |||
| 497 | #define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32) | ||
| 498 | #define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT) | ||
| 499 | #define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT) | ||
| 500 | #define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\ | ||
| 501 | M_CTCP_DEF_TCPCS_INIT) | ||
| 502 | |||
| 503 | #define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48) | ||
| 504 | #define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH) | ||
| 505 | #define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH) | ||
| 506 | #define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\ | ||
| 507 | M_CTCP_DEF_CRC_WIDTH) | ||
| 508 | |||
| 509 | #define K_CTCP_DEF_CRC_WIDTH_4 0 | ||
| 510 | #define K_CTCP_DEF_CRC_WIDTH_2 1 | ||
| 511 | #define K_CTCP_DEF_CRC_WIDTH_1 2 | ||
| 512 | |||
| 513 | #define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50) | ||
| 514 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 515 | |||
| 516 | |||
| 517 | /* | ||
| 518 | * Data Mover Descriptor Doubleword "A" (Table 7-26) | ||
| 519 | */ | ||
| 520 | |||
| 521 | #define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0) | ||
| 522 | #define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR) | ||
| 523 | |||
| 524 | #define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40) | ||
| 525 | #define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41) | ||
| 526 | #define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42) | ||
| 527 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | ||
| 528 | #define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43) | ||
| 529 | #endif /* up to 1250 PASS1 */ | ||
| 530 | |||
| 531 | #define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44) | ||
| 532 | #define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST) | ||
| 533 | #define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST) | ||
| 534 | #define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST) | ||
| 535 | |||
| 536 | #define K_DM_DSCRA_DIR_DEST_INCR 0 | ||
| 537 | #define K_DM_DSCRA_DIR_DEST_DECR 1 | ||
| 538 | #define K_DM_DSCRA_DIR_DEST_CONST 2 | ||
| 539 | |||
| 540 | #define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST) | ||
| 541 | #define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST) | ||
| 542 | #define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST) | ||
| 543 | |||
| 544 | #define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46) | ||
| 545 | #define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC) | ||
| 546 | #define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC) | ||
| 547 | #define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC) | ||
| 548 | |||
| 549 | #define K_DM_DSCRA_DIR_SRC_INCR 0 | ||
| 550 | #define K_DM_DSCRA_DIR_SRC_DECR 1 | ||
| 551 | #define K_DM_DSCRA_DIR_SRC_CONST 2 | ||
| 552 | |||
| 553 | #define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC) | ||
| 554 | #define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC) | ||
| 555 | #define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC) | ||
| 556 | |||
| 557 | |||
| 558 | #define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48) | ||
| 559 | #define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49) | ||
| 560 | #define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50) | ||
| 561 | #define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51) | ||
| 562 | |||
| 563 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 564 | #define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52) | ||
| 565 | #define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53) | ||
| 566 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 567 | |||
| 568 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 569 | #define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54) | ||
| 570 | #define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55) | ||
| 571 | #define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56) | ||
| 572 | #define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57) | ||
| 573 | #define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58) | ||
| 574 | #define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59) | ||
| 575 | #define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60) | ||
| 576 | #define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61) | ||
| 577 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 578 | |||
| 579 | #define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61) | ||
| 580 | |||
| 581 | /* | ||
| 582 | * Data Mover Descriptor Doubleword "B" (Table 7-25) | ||
| 583 | */ | ||
| 584 | |||
| 585 | #define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0) | ||
| 586 | #define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR) | ||
| 587 | |||
| 588 | #define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40) | ||
| 589 | #define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH) | ||
| 590 | #define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH) | ||
| 591 | #define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH) | ||
| 592 | |||
| 593 | |||
| 594 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h new file mode 100644 index 000000000000..94e9c7c8e783 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h | |||
| @@ -0,0 +1,474 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Generic Bus Constants File: sb1250_genbus.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the SB1250's Generic Bus interface | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 10/21/02 | ||
| 10 | * BCM1280 specification level: User's Manual 11/14/03 | ||
| 11 | * | ||
| 12 | ********************************************************************* | ||
| 13 | * | ||
| 14 | * Copyright 2000, 2001, 2002, 2003 | ||
| 15 | * Broadcom Corporation. All rights reserved. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or | ||
| 18 | * modify it under the terms of the GNU General Public License as | ||
| 19 | * published by the Free Software Foundation; either version 2 of | ||
| 20 | * the License, or (at your option) any later version. | ||
| 21 | * | ||
| 22 | * This program is distributed in the hope that it will be useful, | ||
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 25 | * GNU General Public License for more details. | ||
| 26 | * | ||
| 27 | * You should have received a copy of the GNU General Public License | ||
| 28 | * along with this program; if not, write to the Free Software | ||
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 30 | * MA 02111-1307 USA | ||
| 31 | ********************************************************************* */ | ||
| 32 | |||
| 33 | |||
| 34 | #ifndef _SB1250_GENBUS_H | ||
| 35 | #define _SB1250_GENBUS_H | ||
| 36 | |||
| 37 | #include "sb1250_defs.h" | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Generic Bus Region Configuration Registers (Table 11-4) | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define S_IO_RDY_ACTIVE 0 | ||
| 44 | #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) | ||
| 45 | |||
| 46 | #define S_IO_ENA_RDY 1 | ||
| 47 | #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) | ||
| 48 | |||
| 49 | #define S_IO_WIDTH_SEL 2 | ||
| 50 | #define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) | ||
| 51 | #define K_IO_WIDTH_SEL_1 0 | ||
| 52 | #define K_IO_WIDTH_SEL_2 1 | ||
| 53 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | ||
| 54 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 55 | #define K_IO_WIDTH_SEL_1L 2 | ||
| 56 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 57 | #define K_IO_WIDTH_SEL_4 3 | ||
| 58 | #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) | ||
| 59 | #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) | ||
| 60 | |||
| 61 | #define S_IO_PARITY_ENA 4 | ||
| 62 | #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) | ||
| 63 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | ||
| 64 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 65 | #define S_IO_BURST_EN 5 | ||
| 66 | #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) | ||
| 67 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 68 | #define S_IO_PARITY_ODD 6 | ||
| 69 | #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) | ||
| 70 | #define S_IO_NONMUX 7 | ||
| 71 | #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) | ||
| 72 | |||
| 73 | #define S_IO_TIMEOUT 8 | ||
| 74 | #define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) | ||
| 75 | #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) | ||
| 76 | #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Generic Bus Region Size register (Table 11-5) | ||
| 80 | */ | ||
| 81 | |||
| 82 | #define S_IO_MULT_SIZE 0 | ||
| 83 | #define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) | ||
| 84 | #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) | ||
| 85 | #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) | ||
| 86 | |||
| 87 | #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ | ||
| 88 | |||
| 89 | /* | ||
| 90 | * Generic Bus Region Address (Table 11-6) | ||
| 91 | */ | ||
| 92 | |||
| 93 | #define S_IO_START_ADDR 0 | ||
| 94 | #define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) | ||
| 95 | #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) | ||
| 96 | #define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) | ||
| 97 | |||
| 98 | #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ | ||
| 99 | |||
| 100 | #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Generic Bus Timing 0 Registers (Table 11-7) | ||
| 105 | */ | ||
| 106 | |||
| 107 | #define S_IO_ALE_WIDTH 0 | ||
| 108 | #define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) | ||
| 109 | #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) | ||
| 110 | #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) | ||
| 111 | |||
| 112 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | ||
| 113 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 114 | #define M_IO_EARLY_CS _SB_MAKEMASK1(3) | ||
| 115 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 116 | |||
| 117 | #define S_IO_ALE_TO_CS 4 | ||
| 118 | #define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) | ||
| 119 | #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) | ||
| 120 | #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) | ||
| 121 | |||
| 122 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | ||
| 123 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 124 | #define S_IO_BURST_WIDTH _SB_MAKE64(6) | ||
| 125 | #define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) | ||
| 126 | #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) | ||
| 127 | #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) | ||
| 128 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 129 | |||
| 130 | #define S_IO_CS_WIDTH 8 | ||
| 131 | #define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) | ||
| 132 | #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) | ||
| 133 | #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) | ||
| 134 | |||
| 135 | #define S_IO_RDY_SMPLE 13 | ||
| 136 | #define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) | ||
| 137 | #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) | ||
| 138 | #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) | ||
| 139 | |||
| 140 | |||
| 141 | /* | ||
| 142 | * Generic Bus Timing 1 Registers (Table 11-8) | ||
| 143 | */ | ||
| 144 | |||
| 145 | #define S_IO_ALE_TO_WRITE 0 | ||
| 146 | #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) | ||
| 147 | #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) | ||
| 148 | #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) | ||
| 149 | |||
| 150 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ | ||
| 151 | || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 152 | #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) | ||
| 153 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 154 | |||
| 155 | #define S_IO_WRITE_WIDTH 4 | ||
| 156 | #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) | ||
| 157 | #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) | ||
| 158 | #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) | ||
| 159 | |||
| 160 | #define S_IO_IDLE_CYCLE 8 | ||
| 161 | #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) | ||
| 162 | #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) | ||
| 163 | #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) | ||
| 164 | |||
| 165 | #define S_IO_OE_TO_CS 12 | ||
| 166 | #define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) | ||
| 167 | #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) | ||
| 168 | #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) | ||
| 169 | |||
| 170 | #define S_IO_CS_TO_OE 14 | ||
| 171 | #define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) | ||
| 172 | #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) | ||
| 173 | #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) | ||
| 174 | |||
| 175 | /* | ||
| 176 | * Generic Bus Interrupt Status Register (Table 11-9) | ||
| 177 | */ | ||
| 178 | |||
| 179 | #define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) | ||
| 180 | #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) | ||
| 181 | #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) | ||
| 182 | #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) | ||
| 183 | #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) | ||
| 184 | #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) | ||
| 185 | #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) | ||
| 186 | #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) | ||
| 187 | #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) | ||
| 188 | |||
| 189 | #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) | ||
| 190 | #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) | ||
| 191 | #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) | ||
| 192 | #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) | ||
| 193 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 194 | #define M_IO_COH_ERR _SB_MAKEMASK1(14) | ||
| 195 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 196 | |||
| 197 | |||
| 198 | /* | ||
| 199 | * Generic Bus Output Drive Control Register 0 (Table 14-18) | ||
| 200 | */ | ||
| 201 | |||
| 202 | #define S_IO_SLEW0 0 | ||
| 203 | #define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) | ||
| 204 | #define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) | ||
| 205 | #define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) | ||
| 206 | |||
| 207 | #define S_IO_DRV_A 2 | ||
| 208 | #define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) | ||
| 209 | #define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) | ||
| 210 | #define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) | ||
| 211 | |||
| 212 | #define S_IO_DRV_B 6 | ||
| 213 | #define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) | ||
| 214 | #define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) | ||
| 215 | #define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) | ||
| 216 | |||
| 217 | #define S_IO_DRV_C 10 | ||
| 218 | #define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) | ||
| 219 | #define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) | ||
| 220 | #define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) | ||
| 221 | |||
| 222 | #define S_IO_DRV_D 14 | ||
| 223 | #define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) | ||
| 224 | #define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) | ||
| 225 | #define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) | ||
| 226 | |||
| 227 | /* | ||
| 228 | * Generic Bus Output Drive Control Register 1 (Table 14-19) | ||
| 229 | */ | ||
| 230 | |||
| 231 | #define S_IO_DRV_E 2 | ||
| 232 | #define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) | ||
| 233 | #define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) | ||
| 234 | #define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) | ||
| 235 | |||
| 236 | #define S_IO_DRV_F 6 | ||
| 237 | #define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) | ||
| 238 | #define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) | ||
| 239 | #define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) | ||
| 240 | |||
| 241 | #define S_IO_SLEW1 8 | ||
| 242 | #define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) | ||
| 243 | #define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) | ||
| 244 | #define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) | ||
| 245 | |||
| 246 | #define S_IO_DRV_G 10 | ||
| 247 | #define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) | ||
| 248 | #define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) | ||
| 249 | #define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) | ||
| 250 | |||
| 251 | #define S_IO_SLEW2 12 | ||
| 252 | #define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) | ||
| 253 | #define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) | ||
| 254 | #define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) | ||
| 255 | |||
| 256 | #define S_IO_DRV_H 14 | ||
| 257 | #define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) | ||
| 258 | #define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) | ||
| 259 | #define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) | ||
| 260 | |||
| 261 | /* | ||
| 262 | * Generic Bus Output Drive Control Register 2 (Table 14-20) | ||
| 263 | */ | ||
| 264 | |||
| 265 | #define S_IO_DRV_J 2 | ||
| 266 | #define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) | ||
| 267 | #define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) | ||
| 268 | #define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) | ||
| 269 | |||
| 270 | #define S_IO_DRV_K 6 | ||
| 271 | #define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) | ||
| 272 | #define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) | ||
| 273 | #define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) | ||
| 274 | |||
| 275 | #define S_IO_DRV_L 10 | ||
| 276 | #define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) | ||
| 277 | #define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) | ||
| 278 | #define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) | ||
| 279 | |||
| 280 | #define S_IO_DRV_M 14 | ||
| 281 | #define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) | ||
| 282 | #define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) | ||
| 283 | #define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) | ||
| 284 | |||
| 285 | /* | ||
| 286 | * Generic Bus Output Drive Control Register 3 (Table 14-21) | ||
| 287 | */ | ||
| 288 | |||
| 289 | #define S_IO_SLEW3 0 | ||
| 290 | #define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) | ||
| 291 | #define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) | ||
| 292 | #define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) | ||
| 293 | |||
| 294 | #define S_IO_DRV_N 2 | ||
| 295 | #define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) | ||
| 296 | #define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) | ||
| 297 | #define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) | ||
| 298 | |||
| 299 | #define S_IO_DRV_P 6 | ||
| 300 | #define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) | ||
| 301 | #define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) | ||
| 302 | #define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) | ||
| 303 | |||
| 304 | #define S_IO_DRV_Q 10 | ||
| 305 | #define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) | ||
| 306 | #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) | ||
| 307 | #define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) | ||
| 308 | |||
| 309 | #define S_IO_DRV_R 14 | ||
| 310 | #define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) | ||
| 311 | #define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) | ||
| 312 | #define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) | ||
| 313 | |||
| 314 | |||
| 315 | /* | ||
| 316 | * PCMCIA configuration register (Table 12-6) | ||
| 317 | */ | ||
| 318 | |||
| 319 | #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) | ||
| 320 | #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) | ||
| 321 | #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) | ||
| 322 | #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) | ||
| 323 | #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) | ||
| 324 | #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) | ||
| 325 | #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) | ||
| 326 | #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) | ||
| 327 | #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) | ||
| 328 | #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) | ||
| 329 | |||
| 330 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 331 | #define S_PCMCIA_MODE 16 | ||
| 332 | #define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) | ||
| 333 | #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) | ||
| 334 | #define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) | ||
| 335 | |||
| 336 | #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ | ||
| 337 | #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ | ||
| 338 | #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ | ||
| 339 | #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ | ||
| 340 | #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ | ||
| 341 | #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ | ||
| 342 | #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ | ||
| 343 | #endif | ||
| 344 | |||
| 345 | |||
| 346 | /* | ||
| 347 | * PCMCIA status register (Table 12-7) | ||
| 348 | */ | ||
| 349 | |||
| 350 | #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) | ||
| 351 | #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) | ||
| 352 | #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) | ||
| 353 | #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) | ||
| 354 | #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) | ||
| 355 | #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) | ||
| 356 | #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) | ||
| 357 | #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) | ||
| 358 | #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) | ||
| 359 | #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) | ||
| 360 | #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) | ||
| 361 | |||
| 362 | /* | ||
| 363 | * GPIO Interrupt Type Register (table 13-3) | ||
| 364 | */ | ||
| 365 | |||
| 366 | #define K_GPIO_INTR_DISABLE 0 | ||
| 367 | #define K_GPIO_INTR_EDGE 1 | ||
| 368 | #define K_GPIO_INTR_LEVEL 2 | ||
| 369 | #define K_GPIO_INTR_SPLIT 3 | ||
| 370 | |||
| 371 | #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) | ||
| 372 | #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) | ||
| 373 | #define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) | ||
| 374 | #define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) | ||
| 375 | |||
| 376 | #define S_GPIO_INTR_TYPE0 0 | ||
| 377 | #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) | ||
| 378 | #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) | ||
| 379 | #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) | ||
| 380 | |||
| 381 | #define S_GPIO_INTR_TYPE2 2 | ||
| 382 | #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) | ||
| 383 | #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) | ||
| 384 | #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) | ||
| 385 | |||
| 386 | #define S_GPIO_INTR_TYPE4 4 | ||
| 387 | #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) | ||
| 388 | #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) | ||
| 389 | #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) | ||
| 390 | |||
| 391 | #define S_GPIO_INTR_TYPE6 6 | ||
| 392 | #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) | ||
| 393 | #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) | ||
| 394 | #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) | ||
| 395 | |||
| 396 | #define S_GPIO_INTR_TYPE8 8 | ||
| 397 | #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) | ||
| 398 | #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) | ||
| 399 | #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) | ||
| 400 | |||
| 401 | #define S_GPIO_INTR_TYPE10 10 | ||
| 402 | #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) | ||
| 403 | #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) | ||
| 404 | #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) | ||
| 405 | |||
| 406 | #define S_GPIO_INTR_TYPE12 12 | ||
| 407 | #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) | ||
| 408 | #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) | ||
| 409 | #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) | ||
| 410 | |||
| 411 | #define S_GPIO_INTR_TYPE14 14 | ||
| 412 | #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) | ||
| 413 | #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) | ||
| 414 | #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) | ||
| 415 | |||
| 416 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 417 | |||
| 418 | /* | ||
| 419 | * GPIO Interrupt Additional Type Register | ||
| 420 | */ | ||
| 421 | |||
| 422 | #define K_GPIO_INTR_BOTHEDGE 0 | ||
| 423 | #define K_GPIO_INTR_RISEEDGE 1 | ||
| 424 | #define K_GPIO_INTR_UNPRED1 2 | ||
| 425 | #define K_GPIO_INTR_UNPRED2 3 | ||
| 426 | |||
| 427 | #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) | ||
| 428 | #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) | ||
| 429 | #define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) | ||
| 430 | #define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) | ||
| 431 | |||
| 432 | #define S_GPIO_INTR_ATYPE0 0 | ||
| 433 | #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) | ||
| 434 | #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) | ||
| 435 | #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) | ||
| 436 | |||
| 437 | #define S_GPIO_INTR_ATYPE2 2 | ||
| 438 | #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) | ||
| 439 | #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) | ||
| 440 | #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) | ||
| 441 | |||
| 442 | #define S_GPIO_INTR_ATYPE4 4 | ||
| 443 | #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) | ||
| 444 | #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) | ||
| 445 | #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) | ||
| 446 | |||
| 447 | #define S_GPIO_INTR_ATYPE6 6 | ||
| 448 | #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) | ||
| 449 | #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) | ||
| 450 | #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) | ||
| 451 | |||
| 452 | #define S_GPIO_INTR_ATYPE8 8 | ||
| 453 | #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) | ||
| 454 | #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) | ||
| 455 | #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) | ||
| 456 | |||
| 457 | #define S_GPIO_INTR_ATYPE10 10 | ||
| 458 | #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) | ||
| 459 | #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) | ||
| 460 | #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) | ||
| 461 | |||
| 462 | #define S_GPIO_INTR_ATYPE12 12 | ||
| 463 | #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) | ||
| 464 | #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) | ||
| 465 | #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) | ||
| 466 | |||
| 467 | #define S_GPIO_INTR_ATYPE14 14 | ||
| 468 | #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) | ||
| 469 | #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) | ||
| 470 | #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) | ||
| 471 | #endif | ||
| 472 | |||
| 473 | |||
| 474 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h new file mode 100644 index 000000000000..f2850b4bcfd4 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_int.h | |||
| @@ -0,0 +1,248 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Interrupt Mapper definitions File: sb1250_int.h | ||
| 5 | * | ||
| 6 | * This module contains constants for manipulating the SB1250's | ||
| 7 | * interrupt mapper and definitions for the interrupt sources. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000, 2001, 2002, 2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_INT_H | ||
| 34 | #define _SB1250_INT_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* ********************************************************************* | ||
| 39 | * Interrupt Mapper Constants | ||
| 40 | ********************************************************************* */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Interrupt sources (Table 4-8, UM 0.2) | ||
| 44 | * | ||
| 45 | * First, the interrupt numbers. | ||
| 46 | */ | ||
| 47 | |||
| 48 | #define K_INT_SOURCES 64 | ||
| 49 | |||
| 50 | #define K_INT_WATCHDOG_TIMER_0 0 | ||
| 51 | #define K_INT_WATCHDOG_TIMER_1 1 | ||
| 52 | #define K_INT_TIMER_0 2 | ||
| 53 | #define K_INT_TIMER_1 3 | ||
| 54 | #define K_INT_TIMER_2 4 | ||
| 55 | #define K_INT_TIMER_3 5 | ||
| 56 | #define K_INT_SMB_0 6 | ||
| 57 | #define K_INT_SMB_1 7 | ||
| 58 | #define K_INT_UART_0 8 | ||
| 59 | #define K_INT_UART_1 9 | ||
| 60 | #define K_INT_SER_0 10 | ||
| 61 | #define K_INT_SER_1 11 | ||
| 62 | #define K_INT_PCMCIA 12 | ||
| 63 | #define K_INT_ADDR_TRAP 13 | ||
| 64 | #define K_INT_PERF_CNT 14 | ||
| 65 | #define K_INT_TRACE_FREEZE 15 | ||
| 66 | #define K_INT_BAD_ECC 16 | ||
| 67 | #define K_INT_COR_ECC 17 | ||
| 68 | #define K_INT_IO_BUS 18 | ||
| 69 | #define K_INT_MAC_0 19 | ||
| 70 | #define K_INT_MAC_1 20 | ||
| 71 | #define K_INT_MAC_2 21 | ||
| 72 | #define K_INT_DM_CH_0 22 | ||
| 73 | #define K_INT_DM_CH_1 23 | ||
| 74 | #define K_INT_DM_CH_2 24 | ||
| 75 | #define K_INT_DM_CH_3 25 | ||
| 76 | #define K_INT_MBOX_0 26 | ||
| 77 | #define K_INT_MBOX_1 27 | ||
| 78 | #define K_INT_MBOX_2 28 | ||
| 79 | #define K_INT_MBOX_3 29 | ||
| 80 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 81 | #define K_INT_CYCLE_CP0_INT 30 | ||
| 82 | #define K_INT_CYCLE_CP1_INT 31 | ||
| 83 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 84 | #define K_INT_GPIO_0 32 | ||
| 85 | #define K_INT_GPIO_1 33 | ||
| 86 | #define K_INT_GPIO_2 34 | ||
| 87 | #define K_INT_GPIO_3 35 | ||
| 88 | #define K_INT_GPIO_4 36 | ||
| 89 | #define K_INT_GPIO_5 37 | ||
| 90 | #define K_INT_GPIO_6 38 | ||
| 91 | #define K_INT_GPIO_7 39 | ||
| 92 | #define K_INT_GPIO_8 40 | ||
| 93 | #define K_INT_GPIO_9 41 | ||
| 94 | #define K_INT_GPIO_10 42 | ||
| 95 | #define K_INT_GPIO_11 43 | ||
| 96 | #define K_INT_GPIO_12 44 | ||
| 97 | #define K_INT_GPIO_13 45 | ||
| 98 | #define K_INT_GPIO_14 46 | ||
| 99 | #define K_INT_GPIO_15 47 | ||
| 100 | #define K_INT_LDT_FATAL 48 | ||
| 101 | #define K_INT_LDT_NONFATAL 49 | ||
| 102 | #define K_INT_LDT_SMI 50 | ||
| 103 | #define K_INT_LDT_NMI 51 | ||
| 104 | #define K_INT_LDT_INIT 52 | ||
| 105 | #define K_INT_LDT_STARTUP 53 | ||
| 106 | #define K_INT_LDT_EXT 54 | ||
| 107 | #define K_INT_PCI_ERROR 55 | ||
| 108 | #define K_INT_PCI_INTA 56 | ||
| 109 | #define K_INT_PCI_INTB 57 | ||
| 110 | #define K_INT_PCI_INTC 58 | ||
| 111 | #define K_INT_PCI_INTD 59 | ||
| 112 | #define K_INT_SPARE_2 60 | ||
| 113 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 114 | #define K_INT_MAC_0_CH1 61 | ||
| 115 | #define K_INT_MAC_1_CH1 62 | ||
| 116 | #define K_INT_MAC_2_CH1 63 | ||
| 117 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 118 | |||
| 119 | /* | ||
| 120 | * Mask values for each interrupt | ||
| 121 | */ | ||
| 122 | |||
| 123 | #define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) | ||
| 124 | #define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) | ||
| 125 | #define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) | ||
| 126 | #define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) | ||
| 127 | #define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) | ||
| 128 | #define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) | ||
| 129 | #define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) | ||
| 130 | #define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) | ||
| 131 | #define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) | ||
| 132 | #define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) | ||
| 133 | #define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) | ||
| 134 | #define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) | ||
| 135 | #define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) | ||
| 136 | #define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) | ||
| 137 | #define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) | ||
| 138 | #define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) | ||
| 139 | #define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) | ||
| 140 | #define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) | ||
| 141 | #define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) | ||
| 142 | #define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) | ||
| 143 | #define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) | ||
| 144 | #define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) | ||
| 145 | #define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) | ||
| 146 | #define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) | ||
| 147 | #define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) | ||
| 148 | #define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) | ||
| 149 | #define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) | ||
| 150 | #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) | ||
| 151 | #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) | ||
| 152 | #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) | ||
| 153 | #define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) | ||
| 154 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 155 | #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) | ||
| 156 | #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) | ||
| 157 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 158 | #define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) | ||
| 159 | #define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) | ||
| 160 | #define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) | ||
| 161 | #define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) | ||
| 162 | #define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) | ||
| 163 | #define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) | ||
| 164 | #define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) | ||
| 165 | #define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) | ||
| 166 | #define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) | ||
| 167 | #define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) | ||
| 168 | #define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) | ||
| 169 | #define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) | ||
| 170 | #define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) | ||
| 171 | #define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) | ||
| 172 | #define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) | ||
| 173 | #define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) | ||
| 174 | #define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) | ||
| 175 | #define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) | ||
| 176 | #define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) | ||
| 177 | #define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) | ||
| 178 | #define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) | ||
| 179 | #define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) | ||
| 180 | #define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) | ||
| 181 | #define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) | ||
| 182 | #define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) | ||
| 183 | #define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) | ||
| 184 | #define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) | ||
| 185 | #define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) | ||
| 186 | #define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) | ||
| 187 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 188 | #define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) | ||
| 189 | #define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) | ||
| 190 | #define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) | ||
| 191 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 192 | |||
| 193 | /* | ||
| 194 | * Interrupt mappings | ||
| 195 | */ | ||
| 196 | |||
| 197 | #define K_INT_MAP_I0 0 /* interrupt pins on processor */ | ||
| 198 | #define K_INT_MAP_I1 1 | ||
| 199 | #define K_INT_MAP_I2 2 | ||
| 200 | #define K_INT_MAP_I3 3 | ||
| 201 | #define K_INT_MAP_I4 4 | ||
| 202 | #define K_INT_MAP_I5 5 | ||
| 203 | #define K_INT_MAP_NMI 6 /* nonmaskable */ | ||
| 204 | #define K_INT_MAP_DINT 7 /* debug interrupt */ | ||
| 205 | |||
| 206 | /* | ||
| 207 | * LDT Interrupt Set Register (table 4-5) | ||
| 208 | */ | ||
| 209 | |||
| 210 | #define S_INT_LDT_INTMSG 0 | ||
| 211 | #define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) | ||
| 212 | #define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) | ||
| 213 | #define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) | ||
| 214 | |||
| 215 | #define K_INT_LDT_INTMSG_FIXED 0 | ||
| 216 | #define K_INT_LDT_INTMSG_ARBITRATED 1 | ||
| 217 | #define K_INT_LDT_INTMSG_SMI 2 | ||
| 218 | #define K_INT_LDT_INTMSG_NMI 3 | ||
| 219 | #define K_INT_LDT_INTMSG_INIT 4 | ||
| 220 | #define K_INT_LDT_INTMSG_STARTUP 5 | ||
| 221 | #define K_INT_LDT_INTMSG_EXTINT 6 | ||
| 222 | #define K_INT_LDT_INTMSG_RESERVED 7 | ||
| 223 | |||
| 224 | #define M_INT_LDT_EDGETRIGGER 0 | ||
| 225 | #define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) | ||
| 226 | |||
| 227 | #define M_INT_LDT_PHYSICALDEST 0 | ||
| 228 | #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) | ||
| 229 | |||
| 230 | #define S_INT_LDT_INTDEST 5 | ||
| 231 | #define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) | ||
| 232 | #define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) | ||
| 233 | #define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) | ||
| 234 | |||
| 235 | #define S_INT_LDT_VECTOR 13 | ||
| 236 | #define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) | ||
| 237 | #define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) | ||
| 238 | #define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) | ||
| 239 | |||
| 240 | /* | ||
| 241 | * Vector format (Table 4-6) | ||
| 242 | */ | ||
| 243 | |||
| 244 | #define M_LDTVECT_RAISEINT 0x00 | ||
| 245 | #define M_LDTVECT_RAISEMBOX 0x40 | ||
| 246 | |||
| 247 | |||
| 248 | #endif /* 1250/112x */ | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h new file mode 100644 index 000000000000..6554dcf05cfe --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h | |||
| @@ -0,0 +1,131 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * L2 Cache constants and macros File: sb1250_l2c.h | ||
| 5 | * | ||
| 6 | * This module contains constants useful for manipulating the | ||
| 7 | * level 2 cache. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_L2C_H | ||
| 34 | #define _SB1250_L2C_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Level 2 Cache Tag register (Table 5-3) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_L2C_TAG_MBZ 0 | ||
| 43 | #define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ) | ||
| 44 | |||
| 45 | #define S_L2C_TAG_INDEX 5 | ||
| 46 | #define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX) | ||
| 47 | #define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX) | ||
| 48 | #define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX) | ||
| 49 | |||
| 50 | #define S_L2C_TAG_TAG 17 | ||
| 51 | #define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG) | ||
| 52 | #define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG) | ||
| 53 | #define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG) | ||
| 54 | |||
| 55 | #define S_L2C_TAG_ECC 40 | ||
| 56 | #define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC) | ||
| 57 | #define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC) | ||
| 58 | #define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC) | ||
| 59 | |||
| 60 | #define S_L2C_TAG_WAY 46 | ||
| 61 | #define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY) | ||
| 62 | #define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY) | ||
| 63 | #define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY) | ||
| 64 | |||
| 65 | #define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48) | ||
| 66 | #define M_L2C_TAG_VALID _SB_MAKEMASK1(49) | ||
| 67 | |||
| 68 | /* | ||
| 69 | * Format of level 2 cache management address (table 5-2) | ||
| 70 | */ | ||
| 71 | |||
| 72 | #define S_L2C_MGMT_INDEX 5 | ||
| 73 | #define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX) | ||
| 74 | #define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX) | ||
| 75 | #define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX) | ||
| 76 | |||
| 77 | #define S_L2C_MGMT_QUADRANT 15 | ||
| 78 | #define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT) | ||
| 79 | #define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT) | ||
| 80 | #define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT) | ||
| 81 | |||
| 82 | #define S_L2C_MGMT_HALF 16 | ||
| 83 | #define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF) | ||
| 84 | |||
| 85 | #define S_L2C_MGMT_WAY 17 | ||
| 86 | #define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY) | ||
| 87 | #define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY) | ||
| 88 | #define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY) | ||
| 89 | |||
| 90 | #define S_L2C_MGMT_ECC_DIAG 21 | ||
| 91 | #define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG) | ||
| 92 | #define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG) | ||
| 93 | #define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG) | ||
| 94 | |||
| 95 | #define S_L2C_MGMT_TAG 23 | ||
| 96 | #define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG) | ||
| 97 | #define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG) | ||
| 98 | #define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG) | ||
| 99 | |||
| 100 | #define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19) | ||
| 101 | #define M_L2C_MGMT_VALID _SB_MAKEMASK1(20) | ||
| 102 | |||
| 103 | #define A_L2C_MGMT_TAG_BASE 0x00D0000000 | ||
| 104 | |||
| 105 | #define L2C_ENTRIES_PER_WAY 4096 | ||
| 106 | #define L2C_NUM_WAYS 4 | ||
| 107 | |||
| 108 | |||
| 109 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 110 | /* | ||
| 111 | * L2 Read Misc. register (A_L2_READ_MISC) | ||
| 112 | */ | ||
| 113 | #define S_L2C_MISC_NO_WAY 10 | ||
| 114 | #define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY) | ||
| 115 | #define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY) | ||
| 116 | #define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY) | ||
| 117 | |||
| 118 | #define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9) | ||
| 119 | #define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8) | ||
| 120 | #define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7) | ||
| 121 | #define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6) | ||
| 122 | #define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5) | ||
| 123 | #define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4) | ||
| 124 | #define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3) | ||
| 125 | #define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2) | ||
| 126 | #define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1) | ||
| 127 | #define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0) | ||
| 128 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 129 | |||
| 130 | |||
| 131 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h new file mode 100644 index 000000000000..081e8b1c4ad0 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h | |||
| @@ -0,0 +1,423 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * LDT constants File: sb1250_ldt.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros to describe | ||
| 7 | * the LDT interface on the SB1250. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000, 2001, 2002, 2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_LDT_H | ||
| 34 | #define _SB1250_LDT_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | #define K_LDT_VENDOR_SIBYTE 0x166D | ||
| 39 | #define K_LDT_DEVICE_SB1250 0x0002 | ||
| 40 | |||
| 41 | /* | ||
| 42 | * LDT Interface Type 1 (bridge) configuration header | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define R_LDT_TYPE1_DEVICEID 0x0000 | ||
| 46 | #define R_LDT_TYPE1_CMDSTATUS 0x0004 | ||
| 47 | #define R_LDT_TYPE1_CLASSREV 0x0008 | ||
| 48 | #define R_LDT_TYPE1_DEVHDR 0x000C | ||
| 49 | #define R_LDT_TYPE1_BAR0 0x0010 /* not used */ | ||
| 50 | #define R_LDT_TYPE1_BAR1 0x0014 /* not used */ | ||
| 51 | |||
| 52 | #define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */ | ||
| 53 | #define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */ | ||
| 54 | #define R_LDT_TYPE1_MEMLIMIT 0x0020 | ||
| 55 | #define R_LDT_TYPE1_PREFETCH 0x0024 | ||
| 56 | #define R_LDT_TYPE1_PREF_BASE 0x0028 | ||
| 57 | #define R_LDT_TYPE1_PREF_LIMIT 0x002C | ||
| 58 | #define R_LDT_TYPE1_IOLIMIT 0x0030 | ||
| 59 | #define R_LDT_TYPE1_CAPPTR 0x0034 | ||
| 60 | #define R_LDT_TYPE1_ROMADDR 0x0038 | ||
| 61 | #define R_LDT_TYPE1_BRCTL 0x003C | ||
| 62 | #define R_LDT_TYPE1_CMD 0x0040 | ||
| 63 | #define R_LDT_TYPE1_LINKCTRL 0x0044 | ||
| 64 | #define R_LDT_TYPE1_LINKFREQ 0x0048 | ||
| 65 | #define R_LDT_TYPE1_RESERVED1 0x004C | ||
| 66 | #define R_LDT_TYPE1_SRICMD 0x0050 | ||
| 67 | #define R_LDT_TYPE1_SRITXNUM 0x0054 | ||
| 68 | #define R_LDT_TYPE1_SRIRXNUM 0x0058 | ||
| 69 | #define R_LDT_TYPE1_ERRSTATUS 0x0068 | ||
| 70 | #define R_LDT_TYPE1_SRICTRL 0x006C | ||
| 71 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 72 | #define R_LDT_TYPE1_ADDSTATUS 0x0070 | ||
| 73 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 74 | #define R_LDT_TYPE1_TXBUFCNT 0x00C8 | ||
| 75 | #define R_LDT_TYPE1_EXPCRC 0x00DC | ||
| 76 | #define R_LDT_TYPE1_RXCRC 0x00F0 | ||
| 77 | |||
| 78 | |||
| 79 | /* | ||
| 80 | * LDT Device ID register | ||
| 81 | */ | ||
| 82 | |||
| 83 | #define S_LDT_DEVICEID_VENDOR 0 | ||
| 84 | #define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR) | ||
| 85 | #define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR) | ||
| 86 | #define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR) | ||
| 87 | |||
| 88 | #define S_LDT_DEVICEID_DEVICEID 16 | ||
| 89 | #define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID) | ||
| 90 | #define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID) | ||
| 91 | #define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID) | ||
| 92 | |||
| 93 | |||
| 94 | /* | ||
| 95 | * LDT Command Register (Table 8-13) | ||
| 96 | */ | ||
| 97 | |||
| 98 | #define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0) | ||
| 99 | #define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1) | ||
| 100 | #define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2) | ||
| 101 | #define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3) | ||
| 102 | #define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4) | ||
| 103 | #define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5) | ||
| 104 | #define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6) | ||
| 105 | #define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7) | ||
| 106 | #define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8) | ||
| 107 | #define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9) | ||
| 108 | |||
| 109 | /* | ||
| 110 | * LDT class and revision registers | ||
| 111 | */ | ||
| 112 | |||
| 113 | #define S_LDT_CLASSREV_REV 0 | ||
| 114 | #define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV) | ||
| 115 | #define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV) | ||
| 116 | #define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV) | ||
| 117 | |||
| 118 | #define S_LDT_CLASSREV_CLASS 8 | ||
| 119 | #define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS) | ||
| 120 | #define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS) | ||
| 121 | #define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS) | ||
| 122 | |||
| 123 | #define K_LDT_REV 0x01 | ||
| 124 | #define K_LDT_CLASS 0x060000 | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Device Header (offset 0x0C) | ||
| 128 | */ | ||
| 129 | |||
| 130 | #define S_LDT_DEVHDR_CLINESZ 0 | ||
| 131 | #define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ) | ||
| 132 | #define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ) | ||
| 133 | #define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ) | ||
| 134 | |||
| 135 | #define S_LDT_DEVHDR_LATTMR 8 | ||
| 136 | #define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR) | ||
| 137 | #define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR) | ||
| 138 | #define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR) | ||
| 139 | |||
| 140 | #define S_LDT_DEVHDR_HDRTYPE 16 | ||
| 141 | #define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE) | ||
| 142 | #define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE) | ||
| 143 | #define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE) | ||
| 144 | |||
| 145 | #define K_LDT_DEVHDR_HDRTYPE_TYPE1 1 | ||
| 146 | |||
| 147 | #define S_LDT_DEVHDR_BIST 24 | ||
| 148 | #define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST) | ||
| 149 | #define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST) | ||
| 150 | #define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST) | ||
| 151 | |||
| 152 | |||
| 153 | |||
| 154 | /* | ||
| 155 | * LDT Status Register (Table 8-14). Note that these constants | ||
| 156 | * assume you've read the command and status register | ||
| 157 | * together (32-bit read at offset 0x04) | ||
| 158 | * | ||
| 159 | * These bits also apply to the secondary status | ||
| 160 | * register (Table 8-15), offset 0x1C | ||
| 161 | */ | ||
| 162 | |||
| 163 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 164 | #define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3) | ||
| 165 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 166 | #define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20) | ||
| 167 | #define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21) | ||
| 168 | #define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22) | ||
| 169 | #define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23) | ||
| 170 | #define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24) | ||
| 171 | |||
| 172 | #define S_LDT_STATUS_DEVSELTIMING 25 | ||
| 173 | #define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING) | ||
| 174 | #define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING) | ||
| 175 | #define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING) | ||
| 176 | |||
| 177 | #define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27) | ||
| 178 | #define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28) | ||
| 179 | #define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29) | ||
| 180 | #define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30) | ||
| 181 | #define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31) | ||
| 182 | |||
| 183 | /* | ||
| 184 | * Bridge Control Register (Table 8-16). Note that these | ||
| 185 | * constants assume you've read the register as a 32-bit | ||
| 186 | * read (offset 0x3C) | ||
| 187 | */ | ||
| 188 | |||
| 189 | #define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16) | ||
| 190 | #define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17) | ||
| 191 | #define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18) | ||
| 192 | #define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19) | ||
| 193 | #define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21) | ||
| 194 | #define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22) | ||
| 195 | #define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23) | ||
| 196 | #define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24) | ||
| 197 | #define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25) | ||
| 198 | #define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26) | ||
| 199 | #define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27) | ||
| 200 | |||
| 201 | /* | ||
| 202 | * LDT Command Register (Table 8-17). Note that these constants | ||
| 203 | * assume you've read the command and status register together | ||
| 204 | * 32-bit read at offset 0x40 | ||
| 205 | */ | ||
| 206 | |||
| 207 | #define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16) | ||
| 208 | #define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17) | ||
| 209 | |||
| 210 | #define S_LDT_CMD_CAPTYPE 29 | ||
| 211 | #define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE) | ||
| 212 | #define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE) | ||
| 213 | #define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE) | ||
| 214 | |||
| 215 | /* | ||
| 216 | * LDT link control register (Table 8-18), and (Table 8-19) | ||
| 217 | */ | ||
| 218 | |||
| 219 | #define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1) | ||
| 220 | #define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2) | ||
| 221 | #define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3) | ||
| 222 | #define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4) | ||
| 223 | #define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5) | ||
| 224 | #define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6) | ||
| 225 | #define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7) | ||
| 226 | |||
| 227 | #define S_LDT_LINKCTRL_CRCERR 8 | ||
| 228 | #define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR) | ||
| 229 | #define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR) | ||
| 230 | #define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR) | ||
| 231 | |||
| 232 | #define S_LDT_LINKCTRL_MAXIN 16 | ||
| 233 | #define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN) | ||
| 234 | #define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN) | ||
| 235 | #define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN) | ||
| 236 | |||
| 237 | #define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19) | ||
| 238 | |||
| 239 | #define S_LDT_LINKCTRL_MAXOUT 20 | ||
| 240 | #define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT) | ||
| 241 | #define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT) | ||
| 242 | #define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT) | ||
| 243 | |||
| 244 | #define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23) | ||
| 245 | |||
| 246 | #define S_LDT_LINKCTRL_WIDTHIN 24 | ||
| 247 | #define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN) | ||
| 248 | #define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN) | ||
| 249 | #define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN) | ||
| 250 | |||
| 251 | #define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27) | ||
| 252 | |||
| 253 | #define S_LDT_LINKCTRL_WIDTHOUT 28 | ||
| 254 | #define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT) | ||
| 255 | #define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT) | ||
| 256 | #define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT) | ||
| 257 | |||
| 258 | #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31) | ||
| 259 | |||
| 260 | /* | ||
| 261 | * LDT Link frequency register (Table 8-20) offset 0x48 | ||
| 262 | */ | ||
| 263 | |||
| 264 | #define S_LDT_LINKFREQ_FREQ 8 | ||
| 265 | #define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ) | ||
| 266 | #define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ) | ||
| 267 | #define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ) | ||
| 268 | |||
| 269 | #define K_LDT_LINKFREQ_200MHZ 0 | ||
| 270 | #define K_LDT_LINKFREQ_300MHZ 1 | ||
| 271 | #define K_LDT_LINKFREQ_400MHZ 2 | ||
| 272 | #define K_LDT_LINKFREQ_500MHZ 3 | ||
| 273 | #define K_LDT_LINKFREQ_600MHZ 4 | ||
| 274 | #define K_LDT_LINKFREQ_800MHZ 5 | ||
| 275 | #define K_LDT_LINKFREQ_1000MHZ 6 | ||
| 276 | |||
| 277 | /* | ||
| 278 | * LDT SRI Command Register (Table 8-21). Note that these constants | ||
| 279 | * assume you've read the command and status register together | ||
| 280 | * 32-bit read at offset 0x50 | ||
| 281 | */ | ||
| 282 | |||
| 283 | #define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16) | ||
| 284 | #define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17) | ||
| 285 | #define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18) | ||
| 286 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | ||
| 287 | #define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */ | ||
| 288 | #endif /* up to 1250 PASS1 */ | ||
| 289 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 290 | #define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19) | ||
| 291 | #define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26) | ||
| 292 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 293 | |||
| 294 | |||
| 295 | #define S_LDT_SRICMD_RXMARGIN 20 | ||
| 296 | #define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN) | ||
| 297 | #define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN) | ||
| 298 | #define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN) | ||
| 299 | |||
| 300 | #define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25) | ||
| 301 | |||
| 302 | #define S_LDT_SRICMD_TXINITIALOFFSET 28 | ||
| 303 | #define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET) | ||
| 304 | #define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET) | ||
| 305 | #define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET) | ||
| 306 | |||
| 307 | #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31) | ||
| 308 | |||
| 309 | /* | ||
| 310 | * LDT Error control and status register (Table 8-22) (Table 8-23) | ||
| 311 | */ | ||
| 312 | |||
| 313 | #define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0) | ||
| 314 | #define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1) | ||
| 315 | #define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2) | ||
| 316 | #define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3) | ||
| 317 | #define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4) | ||
| 318 | #define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5) | ||
| 319 | #define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6) | ||
| 320 | #define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7) | ||
| 321 | #define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8) | ||
| 322 | #define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9) | ||
| 323 | #define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10) | ||
| 324 | #define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11) | ||
| 325 | #define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12) | ||
| 326 | #define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13) | ||
| 327 | #define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14) | ||
| 328 | #define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15) | ||
| 329 | #define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16) | ||
| 330 | #define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17) | ||
| 331 | |||
| 332 | #define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24) | ||
| 333 | #define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25) | ||
| 334 | #define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26) | ||
| 335 | #define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27) | ||
| 336 | #define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28) | ||
| 337 | |||
| 338 | /* | ||
| 339 | * SRI Control register (Table 8-24, 8-25) Offset 0x6C | ||
| 340 | */ | ||
| 341 | |||
| 342 | #define S_LDT_SRICTRL_NEEDRESP 0 | ||
| 343 | #define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP) | ||
| 344 | #define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP) | ||
| 345 | #define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP) | ||
| 346 | |||
| 347 | #define S_LDT_SRICTRL_NEEDNPREQ 2 | ||
| 348 | #define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ) | ||
| 349 | #define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ) | ||
| 350 | #define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ) | ||
| 351 | |||
| 352 | #define S_LDT_SRICTRL_NEEDPREQ 4 | ||
| 353 | #define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ) | ||
| 354 | #define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ) | ||
| 355 | #define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ) | ||
| 356 | |||
| 357 | #define S_LDT_SRICTRL_WANTRESP 8 | ||
| 358 | #define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP) | ||
| 359 | #define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP) | ||
| 360 | #define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP) | ||
| 361 | |||
| 362 | #define S_LDT_SRICTRL_WANTNPREQ 10 | ||
| 363 | #define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ) | ||
| 364 | #define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ) | ||
| 365 | #define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ) | ||
| 366 | |||
| 367 | #define S_LDT_SRICTRL_WANTPREQ 12 | ||
| 368 | #define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ) | ||
| 369 | #define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ) | ||
| 370 | #define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ) | ||
| 371 | |||
| 372 | #define S_LDT_SRICTRL_BUFRELSPACE 16 | ||
| 373 | #define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE) | ||
| 374 | #define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE) | ||
| 375 | #define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE) | ||
| 376 | |||
| 377 | /* | ||
| 378 | * LDT SRI Transmit Buffer Count register (Table 8-26) | ||
| 379 | */ | ||
| 380 | |||
| 381 | #define S_LDT_TXBUFCNT_PCMD 0 | ||
| 382 | #define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD) | ||
| 383 | #define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD) | ||
| 384 | #define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD) | ||
| 385 | |||
| 386 | #define S_LDT_TXBUFCNT_PDATA 4 | ||
| 387 | #define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA) | ||
| 388 | #define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA) | ||
| 389 | #define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA) | ||
| 390 | |||
| 391 | #define S_LDT_TXBUFCNT_NPCMD 8 | ||
| 392 | #define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD) | ||
| 393 | #define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD) | ||
| 394 | #define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD) | ||
| 395 | |||
| 396 | #define S_LDT_TXBUFCNT_NPDATA 12 | ||
| 397 | #define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA) | ||
| 398 | #define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA) | ||
| 399 | #define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA) | ||
| 400 | |||
| 401 | #define S_LDT_TXBUFCNT_RCMD 16 | ||
| 402 | #define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD) | ||
| 403 | #define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD) | ||
| 404 | #define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD) | ||
| 405 | |||
| 406 | #define S_LDT_TXBUFCNT_RDATA 20 | ||
| 407 | #define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA) | ||
| 408 | #define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA) | ||
| 409 | #define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA) | ||
| 410 | |||
| 411 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 412 | /* | ||
| 413 | * Additional Status Register | ||
| 414 | */ | ||
| 415 | |||
| 416 | #define S_LDT_ADDSTATUS_TGTDONE 0 | ||
| 417 | #define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE) | ||
| 418 | #define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE) | ||
| 419 | #define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE) | ||
| 420 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 421 | |||
| 422 | #endif | ||
| 423 | |||
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h new file mode 100644 index 000000000000..b6faf08ca81d --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_mac.h | |||
| @@ -0,0 +1,656 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * MAC constants and macros File: sb1250_mac.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros for the SB1250's | ||
| 7 | * ethernet controllers. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_MAC_H | ||
| 34 | #define _SB1250_MAC_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* ********************************************************************* | ||
| 39 | * Ethernet MAC Registers | ||
| 40 | ********************************************************************* */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * MAC Configuration Register (Table 9-13) | ||
| 44 | * Register: MAC_CFG_0 | ||
| 45 | * Register: MAC_CFG_1 | ||
| 46 | * Register: MAC_CFG_2 | ||
| 47 | */ | ||
| 48 | |||
| 49 | |||
| 50 | #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) | ||
| 51 | #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) | ||
| 52 | #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) | ||
| 53 | #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) | ||
| 54 | #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) | ||
| 55 | #define M_MAC_BURST_EN _SB_MAKEMASK1(5) | ||
| 56 | |||
| 57 | #define S_MAC_TX_PAUSE _SB_MAKE64(6) | ||
| 58 | #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) | ||
| 59 | #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) | ||
| 60 | |||
| 61 | #define K_MAC_TX_PAUSE_CNT_512 0 | ||
| 62 | #define K_MAC_TX_PAUSE_CNT_1K 1 | ||
| 63 | #define K_MAC_TX_PAUSE_CNT_2K 2 | ||
| 64 | #define K_MAC_TX_PAUSE_CNT_4K 3 | ||
| 65 | #define K_MAC_TX_PAUSE_CNT_8K 4 | ||
| 66 | #define K_MAC_TX_PAUSE_CNT_16K 5 | ||
| 67 | #define K_MAC_TX_PAUSE_CNT_32K 6 | ||
| 68 | #define K_MAC_TX_PAUSE_CNT_64K 7 | ||
| 69 | |||
| 70 | #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) | ||
| 71 | #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) | ||
| 72 | #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) | ||
| 73 | #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) | ||
| 74 | #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) | ||
| 75 | #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) | ||
| 76 | #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) | ||
| 77 | #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) | ||
| 78 | |||
| 79 | #define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) | ||
| 80 | |||
| 81 | #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) | ||
| 82 | |||
| 83 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 84 | #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) | ||
| 85 | #endif | ||
| 86 | #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) | ||
| 87 | #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) | ||
| 88 | #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) | ||
| 89 | #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) | ||
| 90 | #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) | ||
| 91 | #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) | ||
| 92 | #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) | ||
| 93 | |||
| 94 | #define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) | ||
| 95 | |||
| 96 | #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) | ||
| 97 | #define M_MAC_HDX_EN _SB_MAKEMASK1(33) | ||
| 98 | |||
| 99 | #define S_MAC_SPEED_SEL _SB_MAKE64(34) | ||
| 100 | #define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) | ||
| 101 | #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) | ||
| 102 | #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) | ||
| 103 | |||
| 104 | #define K_MAC_SPEED_SEL_10MBPS 0 | ||
| 105 | #define K_MAC_SPEED_SEL_100MBPS 1 | ||
| 106 | #define K_MAC_SPEED_SEL_1000MBPS 2 | ||
| 107 | #define K_MAC_SPEED_SEL_RESERVED 3 | ||
| 108 | |||
| 109 | #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) | ||
| 110 | #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) | ||
| 111 | #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) | ||
| 112 | #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) | ||
| 113 | |||
| 114 | #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) | ||
| 115 | #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) | ||
| 116 | #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) | ||
| 117 | #define M_MAC_SS_EN _SB_MAKEMASK1(39) | ||
| 118 | |||
| 119 | #define S_MAC_BYPASS_CFG _SB_MAKE64(40) | ||
| 120 | #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) | ||
| 121 | #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) | ||
| 122 | #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) | ||
| 123 | |||
| 124 | #define K_MAC_BYPASS_GMII 0 | ||
| 125 | #define K_MAC_BYPASS_ENCODED 1 | ||
| 126 | #define K_MAC_BYPASS_SOP 2 | ||
| 127 | #define K_MAC_BYPASS_EOP 3 | ||
| 128 | |||
| 129 | #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) | ||
| 130 | #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) | ||
| 131 | |||
| 132 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 133 | #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) | ||
| 134 | #endif /* 1250 PASS2 || 112x PASS1 || 1480*/ | ||
| 135 | |||
| 136 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 137 | #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) | ||
| 138 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 139 | |||
| 140 | #define S_MAC_BYPASS_IFG _SB_MAKE64(46) | ||
| 141 | #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) | ||
| 142 | #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) | ||
| 143 | #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) | ||
| 144 | |||
| 145 | #define K_MAC_FC_CMD_DISABLED 0 | ||
| 146 | #define K_MAC_FC_CMD_ENABLED 1 | ||
| 147 | #define K_MAC_FC_CMD_ENAB_FALSECARR 2 | ||
| 148 | |||
| 149 | #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) | ||
| 150 | #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) | ||
| 151 | #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) | ||
| 152 | |||
| 153 | #define M_MAC_FC_SEL _SB_MAKEMASK1(54) | ||
| 154 | |||
| 155 | #define S_MAC_FC_CMD _SB_MAKE64(55) | ||
| 156 | #define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) | ||
| 157 | #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) | ||
| 158 | #define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) | ||
| 159 | |||
| 160 | #define S_MAC_RX_CH_SEL _SB_MAKE64(57) | ||
| 161 | #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) | ||
| 162 | #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) | ||
| 163 | #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) | ||
| 164 | |||
| 165 | |||
| 166 | /* | ||
| 167 | * MAC Enable Registers | ||
| 168 | * Register: MAC_ENABLE_0 | ||
| 169 | * Register: MAC_ENABLE_1 | ||
| 170 | * Register: MAC_ENABLE_2 | ||
| 171 | */ | ||
| 172 | |||
| 173 | #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) | ||
| 174 | #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) | ||
| 175 | #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) | ||
| 176 | #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) | ||
| 177 | |||
| 178 | #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) | ||
| 179 | |||
| 180 | #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) | ||
| 181 | #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) | ||
| 182 | #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) | ||
| 183 | #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) | ||
| 184 | #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) | ||
| 185 | #endif | ||
| 186 | |||
| 187 | /* | ||
| 188 | * MAC reset information register (1280/1255) | ||
| 189 | */ | ||
| 190 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 191 | #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) | ||
| 192 | #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) | ||
| 193 | #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) | ||
| 194 | #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) | ||
| 195 | #endif | ||
| 196 | |||
| 197 | /* | ||
| 198 | * MAC DMA Control Register | ||
| 199 | * Register: MAC_TXD_CTL_0 | ||
| 200 | * Register: MAC_TXD_CTL_1 | ||
| 201 | * Register: MAC_TXD_CTL_2 | ||
| 202 | */ | ||
| 203 | |||
| 204 | #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) | ||
| 205 | #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) | ||
| 206 | #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) | ||
| 207 | #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) | ||
| 208 | |||
| 209 | #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) | ||
| 210 | #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) | ||
| 211 | #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) | ||
| 212 | #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) | ||
| 213 | |||
| 214 | /* | ||
| 215 | * MAC Fifo Threshhold registers (Table 9-14) | ||
| 216 | * Register: MAC_THRSH_CFG_0 | ||
| 217 | * Register: MAC_THRSH_CFG_1 | ||
| 218 | * Register: MAC_THRSH_CFG_2 | ||
| 219 | */ | ||
| 220 | |||
| 221 | #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) | ||
| 222 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | ||
| 223 | /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ | ||
| 224 | /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ | ||
| 225 | #endif /* up to 1250 PASS1 */ | ||
| 226 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 227 | #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) | ||
| 228 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 229 | #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) | ||
| 230 | #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) | ||
| 231 | |||
| 232 | #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) | ||
| 233 | #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) | ||
| 234 | /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ | ||
| 235 | /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ | ||
| 236 | #endif /* up to 1250 PASS1 */ | ||
| 237 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 238 | #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) | ||
| 239 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 240 | #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) | ||
| 241 | #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) | ||
| 242 | |||
| 243 | #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) | ||
| 244 | #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) | ||
| 245 | #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) | ||
| 246 | #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) | ||
| 247 | |||
| 248 | #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) | ||
| 249 | #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) | ||
| 250 | #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) | ||
| 251 | #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) | ||
| 252 | |||
| 253 | #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) | ||
| 254 | #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) | ||
| 255 | #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) | ||
| 256 | #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) | ||
| 257 | |||
| 258 | #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) | ||
| 259 | #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) | ||
| 260 | #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) | ||
| 261 | #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) | ||
| 262 | |||
| 263 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 264 | #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) | ||
| 265 | #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) | ||
| 266 | #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) | ||
| 267 | #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) | ||
| 268 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 269 | |||
| 270 | /* | ||
| 271 | * MAC Frame Configuration Registers (Table 9-15) | ||
| 272 | * Register: MAC_FRAME_CFG_0 | ||
| 273 | * Register: MAC_FRAME_CFG_1 | ||
| 274 | * Register: MAC_FRAME_CFG_2 | ||
| 275 | */ | ||
| 276 | |||
| 277 | /* XXXCGD: ??? Unused in pass2? */ | ||
| 278 | #define S_MAC_IFG_RX _SB_MAKE64(0) | ||
| 279 | #define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) | ||
| 280 | #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) | ||
| 281 | #define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) | ||
| 282 | |||
| 283 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 284 | #define S_MAC_PRE_LEN _SB_MAKE64(0) | ||
| 285 | #define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) | ||
| 286 | #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) | ||
| 287 | #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) | ||
| 288 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 289 | |||
| 290 | #define S_MAC_IFG_TX _SB_MAKE64(6) | ||
| 291 | #define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) | ||
| 292 | #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) | ||
| 293 | #define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) | ||
| 294 | |||
| 295 | #define S_MAC_IFG_THRSH _SB_MAKE64(12) | ||
| 296 | #define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) | ||
| 297 | #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) | ||
| 298 | #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) | ||
| 299 | |||
| 300 | #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) | ||
| 301 | #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) | ||
| 302 | #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) | ||
| 303 | #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) | ||
| 304 | |||
| 305 | #define S_MAC_LFSR_SEED _SB_MAKE64(22) | ||
| 306 | #define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) | ||
| 307 | #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) | ||
| 308 | #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) | ||
| 309 | |||
| 310 | #define S_MAC_SLOT_SIZE _SB_MAKE64(30) | ||
| 311 | #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) | ||
| 312 | #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) | ||
| 313 | #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) | ||
| 314 | |||
| 315 | #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) | ||
| 316 | #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) | ||
| 317 | #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) | ||
| 318 | #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) | ||
| 319 | |||
| 320 | #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) | ||
| 321 | #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) | ||
| 322 | #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) | ||
| 323 | #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) | ||
| 324 | |||
| 325 | /* | ||
| 326 | * These constants are used to configure the fields within the Frame | ||
| 327 | * Configuration Register. | ||
| 328 | */ | ||
| 329 | |||
| 330 | #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ | ||
| 331 | #define K_MAC_IFG_RX_100 _SB_MAKE64(0) | ||
| 332 | #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) | ||
| 333 | |||
| 334 | #define K_MAC_IFG_TX_10 _SB_MAKE64(20) | ||
| 335 | #define K_MAC_IFG_TX_100 _SB_MAKE64(20) | ||
| 336 | #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) | ||
| 337 | |||
| 338 | #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) | ||
| 339 | #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) | ||
| 340 | #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) | ||
| 341 | |||
| 342 | #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) | ||
| 343 | #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) | ||
| 344 | #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) | ||
| 345 | |||
| 346 | #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) | ||
| 347 | #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) | ||
| 348 | #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) | ||
| 349 | |||
| 350 | #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) | ||
| 351 | #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) | ||
| 352 | #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) | ||
| 353 | |||
| 354 | #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) | ||
| 355 | #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) | ||
| 356 | #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) | ||
| 357 | |||
| 358 | #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) | ||
| 359 | #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) | ||
| 360 | #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) | ||
| 361 | |||
| 362 | #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) | ||
| 363 | #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) | ||
| 364 | #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) | ||
| 365 | #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) | ||
| 366 | |||
| 367 | #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) | ||
| 368 | #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) | ||
| 369 | #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) | ||
| 370 | #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) | ||
| 371 | |||
| 372 | /* | ||
| 373 | * MAC VLAN Tag Registers (Table 9-16) | ||
| 374 | * Register: MAC_VLANTAG_0 | ||
| 375 | * Register: MAC_VLANTAG_1 | ||
| 376 | * Register: MAC_VLANTAG_2 | ||
| 377 | */ | ||
| 378 | |||
| 379 | #define S_MAC_VLAN_TAG _SB_MAKE64(0) | ||
| 380 | #define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) | ||
| 381 | #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) | ||
| 382 | #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) | ||
| 383 | |||
| 384 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 385 | #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) | ||
| 386 | #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) | ||
| 387 | #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) | ||
| 388 | #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) | ||
| 389 | |||
| 390 | #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) | ||
| 391 | #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) | ||
| 392 | #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) | ||
| 393 | #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) | ||
| 394 | |||
| 395 | #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) | ||
| 396 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 397 | |||
| 398 | /* | ||
| 399 | * MAC Status Registers (Table 9-17) | ||
| 400 | * Also used for the MAC Interrupt Mask Register (Table 9-18) | ||
| 401 | * Register: MAC_STATUS_0 | ||
| 402 | * Register: MAC_STATUS_1 | ||
| 403 | * Register: MAC_STATUS_2 | ||
| 404 | * Register: MAC_INT_MASK_0 | ||
| 405 | * Register: MAC_INT_MASK_1 | ||
| 406 | * Register: MAC_INT_MASK_2 | ||
| 407 | */ | ||
| 408 | |||
| 409 | /* | ||
| 410 | * Use these constants to shift the appropriate channel | ||
| 411 | * into the CH0 position so the same tests can be used | ||
| 412 | * on each channel. | ||
| 413 | */ | ||
| 414 | |||
| 415 | #define S_MAC_RX_CH0 _SB_MAKE64(0) | ||
| 416 | #define S_MAC_RX_CH1 _SB_MAKE64(8) | ||
| 417 | #define S_MAC_TX_CH0 _SB_MAKE64(16) | ||
| 418 | #define S_MAC_TX_CH1 _SB_MAKE64(24) | ||
| 419 | |||
| 420 | #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ | ||
| 421 | #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ | ||
| 422 | |||
| 423 | /* | ||
| 424 | * These are the same as RX channel 0. The idea here | ||
| 425 | * is that you'll use one of the "S_" things above | ||
| 426 | * and pass just the six bits to a DMA-channel-specific ISR | ||
| 427 | */ | ||
| 428 | #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) | ||
| 429 | #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) | ||
| 430 | #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) | ||
| 431 | #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) | ||
| 432 | #define M_MAC_INT_HWM _SB_MAKEMASK1(3) | ||
| 433 | #define M_MAC_INT_LWM _SB_MAKEMASK1(4) | ||
| 434 | #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) | ||
| 435 | #define M_MAC_INT_ERR _SB_MAKEMASK1(6) | ||
| 436 | #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ | ||
| 437 | #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ | ||
| 438 | |||
| 439 | /* | ||
| 440 | * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see | ||
| 441 | * also DMA_TX/DMA_RX in sb_regs.h). | ||
| 442 | */ | ||
| 443 | #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) | ||
| 444 | |||
| 445 | #define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 446 | #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 447 | #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 448 | #define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 449 | #define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 450 | #define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 451 | #define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 452 | #define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 453 | #define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 454 | #define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) | ||
| 455 | #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) | ||
| 456 | |||
| 457 | |||
| 458 | #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) | ||
| 459 | #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) | ||
| 460 | #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) | ||
| 461 | #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) | ||
| 462 | #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) | ||
| 463 | #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) | ||
| 464 | #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) | ||
| 465 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 466 | #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ | ||
| 467 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 468 | |||
| 469 | #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) | ||
| 470 | #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) | ||
| 471 | #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) | ||
| 472 | #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) | ||
| 473 | |||
| 474 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 475 | #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) | ||
| 476 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 477 | |||
| 478 | /* | ||
| 479 | * MAC Fifo Pointer Registers (Table 9-19) [Debug register] | ||
| 480 | * Register: MAC_FIFO_PTRS_0 | ||
| 481 | * Register: MAC_FIFO_PTRS_1 | ||
| 482 | * Register: MAC_FIFO_PTRS_2 | ||
| 483 | */ | ||
| 484 | |||
| 485 | #define S_MAC_TX_WRPTR _SB_MAKE64(0) | ||
| 486 | #define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) | ||
| 487 | #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) | ||
| 488 | #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) | ||
| 489 | |||
| 490 | #define S_MAC_TX_RDPTR _SB_MAKE64(8) | ||
| 491 | #define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) | ||
| 492 | #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) | ||
| 493 | #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) | ||
| 494 | |||
| 495 | #define S_MAC_RX_WRPTR _SB_MAKE64(16) | ||
| 496 | #define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) | ||
| 497 | #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) | ||
| 498 | #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) | ||
| 499 | |||
| 500 | #define S_MAC_RX_RDPTR _SB_MAKE64(24) | ||
| 501 | #define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) | ||
| 502 | #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) | ||
| 503 | #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) | ||
| 504 | |||
| 505 | /* | ||
| 506 | * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] | ||
| 507 | * Register: MAC_EOPCNT_0 | ||
| 508 | * Register: MAC_EOPCNT_1 | ||
| 509 | * Register: MAC_EOPCNT_2 | ||
| 510 | */ | ||
| 511 | |||
| 512 | #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) | ||
| 513 | #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) | ||
| 514 | #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) | ||
| 515 | #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) | ||
| 516 | |||
| 517 | #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) | ||
| 518 | #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) | ||
| 519 | #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) | ||
| 520 | #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) | ||
| 521 | |||
| 522 | /* | ||
| 523 | * MAC Recieve Address Filter Exact Match Registers (Table 9-21) | ||
| 524 | * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 | ||
| 525 | * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 | ||
| 526 | * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 | ||
| 527 | */ | ||
| 528 | |||
| 529 | /* No bitfields */ | ||
| 530 | |||
| 531 | /* | ||
| 532 | * MAC Receive Address Filter Mask Registers | ||
| 533 | * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 | ||
| 534 | * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 | ||
| 535 | * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 | ||
| 536 | */ | ||
| 537 | |||
| 538 | /* No bitfields */ | ||
| 539 | |||
| 540 | /* | ||
| 541 | * MAC Recieve Address Filter Hash Match Registers (Table 9-22) | ||
| 542 | * Registers: MAC_HASH0_0 through MAC_HASH7_0 | ||
| 543 | * Registers: MAC_HASH0_1 through MAC_HASH7_1 | ||
| 544 | * Registers: MAC_HASH0_2 through MAC_HASH7_2 | ||
| 545 | */ | ||
| 546 | |||
| 547 | /* No bitfields */ | ||
| 548 | |||
| 549 | /* | ||
| 550 | * MAC Transmit Source Address Registers (Table 9-23) | ||
| 551 | * Register: MAC_ETHERNET_ADDR_0 | ||
| 552 | * Register: MAC_ETHERNET_ADDR_1 | ||
| 553 | * Register: MAC_ETHERNET_ADDR_2 | ||
| 554 | */ | ||
| 555 | |||
| 556 | /* No bitfields */ | ||
| 557 | |||
| 558 | /* | ||
| 559 | * MAC Packet Type Configuration Register | ||
| 560 | * Register: MAC_TYPE_CFG_0 | ||
| 561 | * Register: MAC_TYPE_CFG_1 | ||
| 562 | * Register: MAC_TYPE_CFG_2 | ||
| 563 | */ | ||
| 564 | |||
| 565 | #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) | ||
| 566 | |||
| 567 | #define S_TYPECFG_TYPE0 _SB_MAKE64(0) | ||
| 568 | #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) | ||
| 569 | #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) | ||
| 570 | #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) | ||
| 571 | |||
| 572 | #define S_TYPECFG_TYPE1 _SB_MAKE64(0) | ||
| 573 | #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) | ||
| 574 | #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) | ||
| 575 | #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) | ||
| 576 | |||
| 577 | #define S_TYPECFG_TYPE2 _SB_MAKE64(0) | ||
| 578 | #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) | ||
| 579 | #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) | ||
| 580 | #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) | ||
| 581 | |||
| 582 | #define S_TYPECFG_TYPE3 _SB_MAKE64(0) | ||
| 583 | #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) | ||
| 584 | #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) | ||
| 585 | #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) | ||
| 586 | |||
| 587 | /* | ||
| 588 | * MAC Receive Address Filter Control Registers (Table 9-24) | ||
| 589 | * Register: MAC_ADFILTER_CFG_0 | ||
| 590 | * Register: MAC_ADFILTER_CFG_1 | ||
| 591 | * Register: MAC_ADFILTER_CFG_2 | ||
| 592 | */ | ||
| 593 | |||
| 594 | #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) | ||
| 595 | #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) | ||
| 596 | #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) | ||
| 597 | #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) | ||
| 598 | #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) | ||
| 599 | #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) | ||
| 600 | #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) | ||
| 601 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 602 | #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) | ||
| 603 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 604 | |||
| 605 | #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) | ||
| 606 | #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) | ||
| 607 | #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) | ||
| 608 | #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) | ||
| 609 | |||
| 610 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 611 | #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) | ||
| 612 | #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) | ||
| 613 | #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) | ||
| 614 | #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) | ||
| 615 | |||
| 616 | #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) | ||
| 617 | #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) | ||
| 618 | #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) | ||
| 619 | #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) | ||
| 620 | |||
| 621 | #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) | ||
| 622 | #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) | ||
| 623 | |||
| 624 | #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) | ||
| 625 | #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) | ||
| 626 | #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) | ||
| 627 | #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) | ||
| 628 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 629 | |||
| 630 | /* | ||
| 631 | * MAC Receive Channel Select Registers (Table 9-25) | ||
| 632 | */ | ||
| 633 | |||
| 634 | /* no bitfields */ | ||
| 635 | |||
| 636 | /* | ||
| 637 | * MAC MII Management Interface Registers (Table 9-26) | ||
| 638 | * Register: MAC_MDIO_0 | ||
| 639 | * Register: MAC_MDIO_1 | ||
| 640 | * Register: MAC_MDIO_2 | ||
| 641 | */ | ||
| 642 | |||
| 643 | #define S_MAC_MDC 0 | ||
| 644 | #define S_MAC_MDIO_DIR 1 | ||
| 645 | #define S_MAC_MDIO_OUT 2 | ||
| 646 | #define S_MAC_GENC 3 | ||
| 647 | #define S_MAC_MDIO_IN 4 | ||
| 648 | |||
| 649 | #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) | ||
| 650 | #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) | ||
| 651 | #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) | ||
| 652 | #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) | ||
| 653 | #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) | ||
| 654 | #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) | ||
| 655 | |||
| 656 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h new file mode 100644 index 000000000000..1eb1b5a88736 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_mc.h | |||
| @@ -0,0 +1,550 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Memory Controller constants File: sb1250_mc.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * programming the memory controller. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000, 2001, 2002, 2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_MC_H | ||
| 34 | #define _SB1250_MC_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Memory Channel Config Register (table 6-14) | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define S_MC_RESERVED0 0 | ||
| 43 | #define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0) | ||
| 44 | |||
| 45 | #define S_MC_CHANNEL_SEL 8 | ||
| 46 | #define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL) | ||
| 47 | #define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL) | ||
| 48 | #define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL) | ||
| 49 | |||
| 50 | #define S_MC_BANK0_MAP 16 | ||
| 51 | #define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP) | ||
| 52 | #define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP) | ||
| 53 | #define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP) | ||
| 54 | |||
| 55 | #define K_MC_BANK0_MAP_DEFAULT 0x00 | ||
| 56 | #define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT) | ||
| 57 | |||
| 58 | #define S_MC_BANK1_MAP 20 | ||
| 59 | #define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP) | ||
| 60 | #define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP) | ||
| 61 | #define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP) | ||
| 62 | |||
| 63 | #define K_MC_BANK1_MAP_DEFAULT 0x08 | ||
| 64 | #define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT) | ||
| 65 | |||
| 66 | #define S_MC_BANK2_MAP 24 | ||
| 67 | #define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP) | ||
| 68 | #define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP) | ||
| 69 | #define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP) | ||
| 70 | |||
| 71 | #define K_MC_BANK2_MAP_DEFAULT 0x09 | ||
| 72 | #define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT) | ||
| 73 | |||
| 74 | #define S_MC_BANK3_MAP 28 | ||
| 75 | #define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP) | ||
| 76 | #define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP) | ||
| 77 | #define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP) | ||
| 78 | |||
| 79 | #define K_MC_BANK3_MAP_DEFAULT 0x0C | ||
| 80 | #define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT) | ||
| 81 | |||
| 82 | #define M_MC_RESERVED1 _SB_MAKEMASK(8, 32) | ||
| 83 | |||
| 84 | #define S_MC_QUEUE_SIZE 40 | ||
| 85 | #define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE) | ||
| 86 | #define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE) | ||
| 87 | #define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE) | ||
| 88 | #define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A) | ||
| 89 | |||
| 90 | #define S_MC_AGE_LIMIT 44 | ||
| 91 | #define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT) | ||
| 92 | #define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT) | ||
| 93 | #define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT) | ||
| 94 | #define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8) | ||
| 95 | |||
| 96 | #define S_MC_WR_LIMIT 48 | ||
| 97 | #define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT) | ||
| 98 | #define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT) | ||
| 99 | #define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT) | ||
| 100 | #define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5) | ||
| 101 | |||
| 102 | #define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52) | ||
| 103 | |||
| 104 | #define M_MC_RESERVED2 _SB_MAKEMASK(3, 53) | ||
| 105 | |||
| 106 | #define S_MC_CS_MODE 56 | ||
| 107 | #define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE) | ||
| 108 | #define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE) | ||
| 109 | #define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE) | ||
| 110 | |||
| 111 | #define K_MC_CS_MODE_MSB_CS 0 | ||
| 112 | #define K_MC_CS_MODE_INTLV_CS 15 | ||
| 113 | #define K_MC_CS_MODE_MIXED_CS_10 12 | ||
| 114 | #define K_MC_CS_MODE_MIXED_CS_30 6 | ||
| 115 | #define K_MC_CS_MODE_MIXED_CS_32 3 | ||
| 116 | |||
| 117 | #define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS) | ||
| 118 | #define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS) | ||
| 119 | #define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10) | ||
| 120 | #define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30) | ||
| 121 | #define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32) | ||
| 122 | |||
| 123 | #define M_MC_ECC_DISABLE _SB_MAKEMASK1(60) | ||
| 124 | #define M_MC_BERR_DISABLE _SB_MAKEMASK1(61) | ||
| 125 | #define M_MC_FORCE_SEQ _SB_MAKEMASK1(62) | ||
| 126 | #define M_MC_DEBUG _SB_MAKEMASK1(63) | ||
| 127 | |||
| 128 | #define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \ | ||
| 129 | V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \ | ||
| 130 | V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \ | ||
| 131 | M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT | ||
| 132 | |||
| 133 | |||
| 134 | /* | ||
| 135 | * Memory clock config register (Table 6-15) | ||
| 136 | * | ||
| 137 | * Note: this field has been updated to be consistent with the errata to 0.2 | ||
| 138 | */ | ||
| 139 | |||
| 140 | #define S_MC_CLK_RATIO 0 | ||
| 141 | #define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO) | ||
| 142 | #define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO) | ||
| 143 | #define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO) | ||
| 144 | |||
| 145 | #define K_MC_CLK_RATIO_2X 4 | ||
| 146 | #define K_MC_CLK_RATIO_25X 5 | ||
| 147 | #define K_MC_CLK_RATIO_3X 6 | ||
| 148 | #define K_MC_CLK_RATIO_35X 7 | ||
| 149 | #define K_MC_CLK_RATIO_4X 8 | ||
| 150 | #define K_MC_CLK_RATIO_45X 9 | ||
| 151 | |||
| 152 | #define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X) | ||
| 153 | #define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X) | ||
| 154 | #define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X) | ||
| 155 | #define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X) | ||
| 156 | #define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X) | ||
| 157 | #define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X) | ||
| 158 | #define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X | ||
| 159 | |||
| 160 | #define S_MC_REF_RATE 8 | ||
| 161 | #define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE) | ||
| 162 | #define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE) | ||
| 163 | #define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE) | ||
| 164 | |||
| 165 | #define K_MC_REF_RATE_100MHz 0x62 | ||
| 166 | #define K_MC_REF_RATE_133MHz 0x81 | ||
| 167 | #define K_MC_REF_RATE_200MHz 0xC4 | ||
| 168 | |||
| 169 | #define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz) | ||
| 170 | #define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz) | ||
| 171 | #define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz) | ||
| 172 | #define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz | ||
| 173 | |||
| 174 | #define S_MC_CLOCK_DRIVE 16 | ||
| 175 | #define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE) | ||
| 176 | #define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE) | ||
| 177 | #define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE) | ||
| 178 | #define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF) | ||
| 179 | |||
| 180 | #define S_MC_DATA_DRIVE 20 | ||
| 181 | #define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE) | ||
| 182 | #define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE) | ||
| 183 | #define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE) | ||
| 184 | #define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0) | ||
| 185 | |||
| 186 | #define S_MC_ADDR_DRIVE 24 | ||
| 187 | #define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE) | ||
| 188 | #define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE) | ||
| 189 | #define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE) | ||
| 190 | #define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0) | ||
| 191 | |||
| 192 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 193 | #define M_MC_REF_DISABLE _SB_MAKEMASK1(30) | ||
| 194 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 195 | |||
| 196 | #define M_MC_DLL_BYPASS _SB_MAKEMASK1(31) | ||
| 197 | |||
| 198 | #define S_MC_DQI_SKEW 32 | ||
| 199 | #define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW) | ||
| 200 | #define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW) | ||
| 201 | #define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW) | ||
| 202 | #define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0) | ||
| 203 | |||
| 204 | #define S_MC_DQO_SKEW 40 | ||
| 205 | #define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW) | ||
| 206 | #define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW) | ||
| 207 | #define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW) | ||
| 208 | #define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0) | ||
| 209 | |||
| 210 | #define S_MC_ADDR_SKEW 48 | ||
| 211 | #define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW) | ||
| 212 | #define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW) | ||
| 213 | #define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW) | ||
| 214 | #define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F) | ||
| 215 | |||
| 216 | #define S_MC_DLL_DEFAULT 56 | ||
| 217 | #define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT) | ||
| 218 | #define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT) | ||
| 219 | #define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT) | ||
| 220 | #define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10) | ||
| 221 | |||
| 222 | #define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \ | ||
| 223 | V_MC_ADDR_SKEW_DEFAULT | \ | ||
| 224 | V_MC_DQO_SKEW_DEFAULT | \ | ||
| 225 | V_MC_DQI_SKEW_DEFAULT | \ | ||
| 226 | V_MC_ADDR_DRIVE_DEFAULT | \ | ||
| 227 | V_MC_DATA_DRIVE_DEFAULT | \ | ||
| 228 | V_MC_CLOCK_DRIVE_DEFAULT | \ | ||
| 229 | V_MC_REF_RATE_DEFAULT | ||
| 230 | |||
| 231 | |||
| 232 | |||
| 233 | /* | ||
| 234 | * DRAM Command Register (Table 6-13) | ||
| 235 | */ | ||
| 236 | |||
| 237 | #define S_MC_COMMAND 0 | ||
| 238 | #define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND) | ||
| 239 | #define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND) | ||
| 240 | #define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND) | ||
| 241 | |||
| 242 | #define K_MC_COMMAND_EMRS 0 | ||
| 243 | #define K_MC_COMMAND_MRS 1 | ||
| 244 | #define K_MC_COMMAND_PRE 2 | ||
| 245 | #define K_MC_COMMAND_AR 3 | ||
| 246 | #define K_MC_COMMAND_SETRFSH 4 | ||
| 247 | #define K_MC_COMMAND_CLRRFSH 5 | ||
| 248 | #define K_MC_COMMAND_SETPWRDN 6 | ||
| 249 | #define K_MC_COMMAND_CLRPWRDN 7 | ||
| 250 | |||
| 251 | #define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS) | ||
| 252 | #define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS) | ||
| 253 | #define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE) | ||
| 254 | #define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR) | ||
| 255 | #define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH) | ||
| 256 | #define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH) | ||
| 257 | #define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN) | ||
| 258 | #define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN) | ||
| 259 | |||
| 260 | #define M_MC_CS0 _SB_MAKEMASK1(4) | ||
| 261 | #define M_MC_CS1 _SB_MAKEMASK1(5) | ||
| 262 | #define M_MC_CS2 _SB_MAKEMASK1(6) | ||
| 263 | #define M_MC_CS3 _SB_MAKEMASK1(7) | ||
| 264 | |||
| 265 | /* | ||
| 266 | * DRAM Mode Register (Table 6-14) | ||
| 267 | */ | ||
| 268 | |||
| 269 | #define S_MC_EMODE 0 | ||
| 270 | #define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE) | ||
| 271 | #define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE) | ||
| 272 | #define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE) | ||
| 273 | #define V_MC_EMODE_DEFAULT V_MC_EMODE(0) | ||
| 274 | |||
| 275 | #define S_MC_MODE 16 | ||
| 276 | #define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE) | ||
| 277 | #define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE) | ||
| 278 | #define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE) | ||
| 279 | #define V_MC_MODE_DEFAULT V_MC_MODE(0x22) | ||
| 280 | |||
| 281 | #define S_MC_DRAM_TYPE 32 | ||
| 282 | #define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE) | ||
| 283 | #define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE) | ||
| 284 | #define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE) | ||
| 285 | |||
| 286 | #define K_MC_DRAM_TYPE_JEDEC 0 | ||
| 287 | #define K_MC_DRAM_TYPE_FCRAM 1 | ||
| 288 | #define K_MC_DRAM_TYPE_SGRAM 2 | ||
| 289 | |||
| 290 | #define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC) | ||
| 291 | #define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM) | ||
| 292 | #define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM) | ||
| 293 | |||
| 294 | #define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35) | ||
| 295 | |||
| 296 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 297 | #define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36) | ||
| 298 | #define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37) | ||
| 299 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 300 | |||
| 301 | |||
| 302 | |||
| 303 | /* | ||
| 304 | * SDRAM Timing Register (Table 6-15) | ||
| 305 | */ | ||
| 306 | |||
| 307 | #define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60) | ||
| 308 | #define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61) | ||
| 309 | #define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62) | ||
| 310 | |||
| 311 | #define S_MC_tFIFO 56 | ||
| 312 | #define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO) | ||
| 313 | #define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO) | ||
| 314 | #define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO) | ||
| 315 | #define K_MC_tFIFO_DEFAULT 1 | ||
| 316 | #define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | ||
| 317 | |||
| 318 | #define S_MC_tRFC 52 | ||
| 319 | #define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC) | ||
| 320 | #define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC) | ||
| 321 | #define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC) | ||
| 322 | #define K_MC_tRFC_DEFAULT 12 | ||
| 323 | #define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT) | ||
| 324 | |||
| 325 | #if SIBYTE_HDR_FEATURE(1250, PASS3) | ||
| 326 | #define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */ | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #define S_MC_tCwCr 40 | ||
| 330 | #define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr) | ||
| 331 | #define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr) | ||
| 332 | #define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr) | ||
| 333 | #define K_MC_tCwCr_DEFAULT 4 | ||
| 334 | #define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | ||
| 335 | |||
| 336 | #define S_MC_tRCr 28 | ||
| 337 | #define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr) | ||
| 338 | #define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr) | ||
| 339 | #define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr) | ||
| 340 | #define K_MC_tRCr_DEFAULT 9 | ||
| 341 | #define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT) | ||
| 342 | |||
| 343 | #define S_MC_tRCw 24 | ||
| 344 | #define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw) | ||
| 345 | #define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw) | ||
| 346 | #define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw) | ||
| 347 | #define K_MC_tRCw_DEFAULT 10 | ||
| 348 | #define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT) | ||
| 349 | |||
| 350 | #define S_MC_tRRD 20 | ||
| 351 | #define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD) | ||
| 352 | #define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD) | ||
| 353 | #define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD) | ||
| 354 | #define K_MC_tRRD_DEFAULT 2 | ||
| 355 | #define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT) | ||
| 356 | |||
| 357 | #define S_MC_tRP 16 | ||
| 358 | #define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP) | ||
| 359 | #define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP) | ||
| 360 | #define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP) | ||
| 361 | #define K_MC_tRP_DEFAULT 4 | ||
| 362 | #define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT) | ||
| 363 | |||
| 364 | #define S_MC_tCwD 8 | ||
| 365 | #define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD) | ||
| 366 | #define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD) | ||
| 367 | #define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD) | ||
| 368 | #define K_MC_tCwD_DEFAULT 1 | ||
| 369 | #define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT) | ||
| 370 | |||
| 371 | #define M_tCrDh _SB_MAKEMASK1(7) | ||
| 372 | #define M_MC_tCrDh M_tCrDh | ||
| 373 | |||
| 374 | #define S_MC_tCrD 4 | ||
| 375 | #define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD) | ||
| 376 | #define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD) | ||
| 377 | #define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD) | ||
| 378 | #define K_MC_tCrD_DEFAULT 2 | ||
| 379 | #define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT) | ||
| 380 | |||
| 381 | #define S_MC_tRCD 0 | ||
| 382 | #define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD) | ||
| 383 | #define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD) | ||
| 384 | #define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD) | ||
| 385 | #define K_MC_tRCD_DEFAULT 3 | ||
| 386 | #define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT) | ||
| 387 | |||
| 388 | #define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \ | ||
| 389 | V_MC_tRFC(K_MC_tRFC_DEFAULT) | \ | ||
| 390 | V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \ | ||
| 391 | V_MC_tRCr(K_MC_tRCr_DEFAULT) | \ | ||
| 392 | V_MC_tRCw(K_MC_tRCw_DEFAULT) | \ | ||
| 393 | V_MC_tRRD(K_MC_tRRD_DEFAULT) | \ | ||
| 394 | V_MC_tRP(K_MC_tRP_DEFAULT) | \ | ||
| 395 | V_MC_tCwD(K_MC_tCwD_DEFAULT) | \ | ||
| 396 | V_MC_tCrD(K_MC_tCrD_DEFAULT) | \ | ||
| 397 | V_MC_tRCD(K_MC_tRCD_DEFAULT) | \ | ||
| 398 | M_MC_r2rIDLE_TWOCYCLES | ||
| 399 | |||
| 400 | /* | ||
| 401 | * Errata says these are not the default | ||
| 402 | * M_MC_w2rIDLE_TWOCYCLES | \ | ||
| 403 | * M_MC_r2wIDLE_TWOCYCLES | \ | ||
| 404 | */ | ||
| 405 | |||
| 406 | |||
| 407 | /* | ||
| 408 | * Chip Select Start Address Register (Table 6-17) | ||
| 409 | */ | ||
| 410 | |||
| 411 | #define S_MC_CS0_START 0 | ||
| 412 | #define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START) | ||
| 413 | #define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START) | ||
| 414 | #define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START) | ||
| 415 | |||
| 416 | #define S_MC_CS1_START 16 | ||
| 417 | #define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START) | ||
| 418 | #define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START) | ||
| 419 | #define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START) | ||
| 420 | |||
| 421 | #define S_MC_CS2_START 32 | ||
| 422 | #define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START) | ||
| 423 | #define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START) | ||
| 424 | #define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START) | ||
| 425 | |||
| 426 | #define S_MC_CS3_START 48 | ||
| 427 | #define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START) | ||
| 428 | #define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START) | ||
| 429 | #define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START) | ||
| 430 | |||
| 431 | /* | ||
| 432 | * Chip Select End Address Register (Table 6-18) | ||
| 433 | */ | ||
| 434 | |||
| 435 | #define S_MC_CS0_END 0 | ||
| 436 | #define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END) | ||
| 437 | #define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END) | ||
| 438 | #define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END) | ||
| 439 | |||
| 440 | #define S_MC_CS1_END 16 | ||
| 441 | #define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END) | ||
| 442 | #define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END) | ||
| 443 | #define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END) | ||
| 444 | |||
| 445 | #define S_MC_CS2_END 32 | ||
| 446 | #define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END) | ||
| 447 | #define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END) | ||
| 448 | #define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END) | ||
| 449 | |||
| 450 | #define S_MC_CS3_END 48 | ||
| 451 | #define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END) | ||
| 452 | #define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END) | ||
| 453 | #define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END) | ||
| 454 | |||
| 455 | /* | ||
| 456 | * Chip Select Interleave Register (Table 6-19) | ||
| 457 | */ | ||
| 458 | |||
| 459 | #define S_MC_INTLV_RESERVED 0 | ||
| 460 | #define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED) | ||
| 461 | |||
| 462 | #define S_MC_INTERLEAVE 7 | ||
| 463 | #define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE) | ||
| 464 | #define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE) | ||
| 465 | |||
| 466 | #define S_MC_INTLV_MBZ 25 | ||
| 467 | #define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ) | ||
| 468 | |||
| 469 | /* | ||
| 470 | * Row Address Bits Register (Table 6-20) | ||
| 471 | */ | ||
| 472 | |||
| 473 | #define S_MC_RAS_RESERVED 0 | ||
| 474 | #define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED) | ||
| 475 | |||
| 476 | #define S_MC_RAS_SELECT 12 | ||
| 477 | #define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT) | ||
| 478 | #define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT) | ||
| 479 | |||
| 480 | #define S_MC_RAS_MBZ 37 | ||
| 481 | #define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ) | ||
| 482 | |||
| 483 | |||
| 484 | /* | ||
| 485 | * Column Address Bits Register (Table 6-21) | ||
| 486 | */ | ||
| 487 | |||
| 488 | #define S_MC_CAS_RESERVED 0 | ||
| 489 | #define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED) | ||
| 490 | |||
| 491 | #define S_MC_CAS_SELECT 5 | ||
| 492 | #define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT) | ||
| 493 | #define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT) | ||
| 494 | |||
| 495 | #define S_MC_CAS_MBZ 23 | ||
| 496 | #define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ) | ||
| 497 | |||
| 498 | |||
| 499 | /* | ||
| 500 | * Bank Address Address Bits Register (Table 6-22) | ||
| 501 | */ | ||
| 502 | |||
| 503 | #define S_MC_BA_RESERVED 0 | ||
| 504 | #define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED) | ||
| 505 | |||
| 506 | #define S_MC_BA_SELECT 5 | ||
| 507 | #define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT) | ||
| 508 | #define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT) | ||
| 509 | |||
| 510 | #define S_MC_BA_MBZ 25 | ||
| 511 | #define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ) | ||
| 512 | |||
| 513 | /* | ||
| 514 | * Chip Select Attribute Register (Table 6-23) | ||
| 515 | */ | ||
| 516 | |||
| 517 | #define K_MC_CS_ATTR_CLOSED 0 | ||
| 518 | #define K_MC_CS_ATTR_CASCHECK 1 | ||
| 519 | #define K_MC_CS_ATTR_HINT 2 | ||
| 520 | #define K_MC_CS_ATTR_OPEN 3 | ||
| 521 | |||
| 522 | #define S_MC_CS0_PAGE 0 | ||
| 523 | #define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE) | ||
| 524 | #define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE) | ||
| 525 | #define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE) | ||
| 526 | |||
| 527 | #define S_MC_CS1_PAGE 16 | ||
| 528 | #define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE) | ||
| 529 | #define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE) | ||
| 530 | #define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE) | ||
| 531 | |||
| 532 | #define S_MC_CS2_PAGE 32 | ||
| 533 | #define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE) | ||
| 534 | #define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE) | ||
| 535 | #define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE) | ||
| 536 | |||
| 537 | #define S_MC_CS3_PAGE 48 | ||
| 538 | #define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE) | ||
| 539 | #define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE) | ||
| 540 | #define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE) | ||
| 541 | |||
| 542 | /* | ||
| 543 | * ECC Test ECC Register (Table 6-25) | ||
| 544 | */ | ||
| 545 | |||
| 546 | #define S_MC_ECC_INVERT 0 | ||
| 547 | #define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT) | ||
| 548 | |||
| 549 | |||
| 550 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h new file mode 100644 index 000000000000..8f53ec817a5e --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_regs.h | |||
| @@ -0,0 +1,893 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Register Definitions File: sb1250_regs.h | ||
| 5 | * | ||
| 6 | * This module contains the addresses of the on-chip peripherals | ||
| 7 | * on the SB1250. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: 01/02/2002 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_REGS_H | ||
| 34 | #define _SB1250_REGS_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | |||
| 39 | /* ********************************************************************* | ||
| 40 | * Some general notes: | ||
| 41 | * | ||
| 42 | * For the most part, when there is more than one peripheral | ||
| 43 | * of the same type on the SOC, the constants below will be | ||
| 44 | * offsets from the base of each peripheral. For example, | ||
| 45 | * the MAC registers are described as offsets from the first | ||
| 46 | * MAC register, and there will be a MAC_REGISTER() macro | ||
| 47 | * to calculate the base address of a given MAC. | ||
| 48 | * | ||
| 49 | * The information in this file is based on the SB1250 SOC | ||
| 50 | * manual version 0.2, July 2000. | ||
| 51 | ********************************************************************* */ | ||
| 52 | |||
| 53 | |||
| 54 | /* ********************************************************************* | ||
| 55 | * Memory Controller Registers | ||
| 56 | ********************************************************************* */ | ||
| 57 | |||
| 58 | /* | ||
| 59 | * XXX: can't remove MC base 0 if 112x, since it's used by other macros, | ||
| 60 | * since there is one reg there (but it could get its addr/offset constant). | ||
| 61 | */ | ||
| 62 | |||
| 63 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 64 | #define A_MC_BASE_0 0x0010051000 | ||
| 65 | #define A_MC_BASE_1 0x0010052000 | ||
| 66 | #define MC_REGISTER_SPACING 0x1000 | ||
| 67 | |||
| 68 | #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) | ||
| 69 | #define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) | ||
| 70 | |||
| 71 | #define R_MC_CONFIG 0x0000000100 | ||
| 72 | #define R_MC_DRAMCMD 0x0000000120 | ||
| 73 | #define R_MC_DRAMMODE 0x0000000140 | ||
| 74 | #define R_MC_TIMING1 0x0000000160 | ||
| 75 | #define R_MC_TIMING2 0x0000000180 | ||
| 76 | #define R_MC_CS_START 0x00000001A0 | ||
| 77 | #define R_MC_CS_END 0x00000001C0 | ||
| 78 | #define R_MC_CS_INTERLEAVE 0x00000001E0 | ||
| 79 | #define S_MC_CS_STARTEND 16 | ||
| 80 | |||
| 81 | #define R_MC_CSX_BASE 0x0000000200 | ||
| 82 | #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ | ||
| 83 | #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ | ||
| 84 | #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ | ||
| 85 | #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ | ||
| 86 | |||
| 87 | #define R_MC_CS0_ROW 0x0000000200 | ||
| 88 | #define R_MC_CS0_COL 0x0000000220 | ||
| 89 | #define R_MC_CS0_BA 0x0000000240 | ||
| 90 | #define R_MC_CS1_ROW 0x0000000260 | ||
| 91 | #define R_MC_CS1_COL 0x0000000280 | ||
| 92 | #define R_MC_CS1_BA 0x00000002A0 | ||
| 93 | #define R_MC_CS2_ROW 0x00000002C0 | ||
| 94 | #define R_MC_CS2_COL 0x00000002E0 | ||
| 95 | #define R_MC_CS2_BA 0x0000000300 | ||
| 96 | #define R_MC_CS3_ROW 0x0000000320 | ||
| 97 | #define R_MC_CS3_COL 0x0000000340 | ||
| 98 | #define R_MC_CS3_BA 0x0000000360 | ||
| 99 | #define R_MC_CS_ATTR 0x0000000380 | ||
| 100 | #define R_MC_TEST_DATA 0x0000000400 | ||
| 101 | #define R_MC_TEST_ECC 0x0000000420 | ||
| 102 | #define R_MC_MCLK_CFG 0x0000000500 | ||
| 103 | |||
| 104 | #endif /* 1250 & 112x */ | ||
| 105 | |||
| 106 | /* ********************************************************************* | ||
| 107 | * L2 Cache Control Registers | ||
| 108 | ********************************************************************* */ | ||
| 109 | |||
| 110 | #if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ | ||
| 111 | |||
| 112 | #define A_L2_READ_TAG 0x0010040018 | ||
| 113 | #define A_L2_ECC_TAG 0x0010040038 | ||
| 114 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 115 | #define A_L2_READ_MISC 0x0010040058 | ||
| 116 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 117 | #define A_L2_WAY_DISABLE 0x0010041000 | ||
| 118 | #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) | ||
| 119 | #define A_L2_MGMT_TAG_BASE 0x00D0000000 | ||
| 120 | |||
| 121 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 122 | #define A_L2_CACHE_DISABLE 0x0010042000 | ||
| 123 | #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) | ||
| 124 | #define A_L2_MISC_CONFIG 0x0010043000 | ||
| 125 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 126 | |||
| 127 | /* Backward-compatibility definitions. */ | ||
| 128 | /* XXX: discourage people from using these constants. */ | ||
| 129 | #define A_L2_READ_ADDRESS A_L2_READ_TAG | ||
| 130 | #define A_L2_EEC_ADDRESS A_L2_ECC_TAG | ||
| 131 | |||
| 132 | #endif | ||
| 133 | |||
| 134 | |||
| 135 | /* ********************************************************************* | ||
| 136 | * PCI Interface Registers | ||
| 137 | ********************************************************************* */ | ||
| 138 | |||
| 139 | #if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ | ||
| 140 | #define A_PCI_TYPE00_HEADER 0x00DE000000 | ||
| 141 | #define A_PCI_TYPE01_HEADER 0x00DE000800 | ||
| 142 | #endif | ||
| 143 | |||
| 144 | |||
| 145 | /* ********************************************************************* | ||
| 146 | * Ethernet DMA and MACs | ||
| 147 | ********************************************************************* */ | ||
| 148 | |||
| 149 | #define A_MAC_BASE_0 0x0010064000 | ||
| 150 | #define A_MAC_BASE_1 0x0010065000 | ||
| 151 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | ||
| 152 | #define A_MAC_BASE_2 0x0010066000 | ||
| 153 | #endif /* 1250 */ | ||
| 154 | |||
| 155 | #define MAC_SPACING 0x1000 | ||
| 156 | #define MAC_DMA_TXRX_SPACING 0x0400 | ||
| 157 | #define MAC_DMA_CHANNEL_SPACING 0x0100 | ||
| 158 | #define DMA_RX 0 | ||
| 159 | #define DMA_TX 1 | ||
| 160 | #define MAC_NUM_DMACHAN 2 /* channels per direction */ | ||
| 161 | |||
| 162 | /* XXX: not correct; depends on SOC type. */ | ||
| 163 | #define MAC_NUM_PORTS 3 | ||
| 164 | |||
| 165 | #define A_MAC_CHANNEL_BASE(macnum) \ | ||
| 166 | (A_MAC_BASE_0 + \ | ||
| 167 | MAC_SPACING*(macnum)) | ||
| 168 | |||
| 169 | #define A_MAC_REGISTER(macnum,reg) \ | ||
| 170 | (A_MAC_BASE_0 + \ | ||
| 171 | MAC_SPACING*(macnum) + (reg)) | ||
| 172 | |||
| 173 | |||
| 174 | #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ | ||
| 175 | |||
| 176 | #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ | ||
| 177 | ((A_MAC_CHANNEL_BASE(macnum)) + \ | ||
| 178 | R_MAC_DMA_CHANNELS + \ | ||
| 179 | (MAC_DMA_TXRX_SPACING*(txrx)) + \ | ||
| 180 | (MAC_DMA_CHANNEL_SPACING*(chan))) | ||
| 181 | |||
| 182 | #define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ | ||
| 183 | (R_MAC_DMA_CHANNELS + \ | ||
| 184 | (MAC_DMA_TXRX_SPACING*(txrx)) + \ | ||
| 185 | (MAC_DMA_CHANNEL_SPACING*(chan))) | ||
| 186 | |||
| 187 | #define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ | ||
| 188 | (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ | ||
| 189 | (reg)) | ||
| 190 | |||
| 191 | #define R_MAC_DMA_REGISTER(txrx, chan, reg) \ | ||
| 192 | (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ | ||
| 193 | (reg)) | ||
| 194 | |||
| 195 | /* | ||
| 196 | * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE | ||
| 197 | */ | ||
| 198 | |||
| 199 | #define R_MAC_DMA_CONFIG0 0x00000000 | ||
| 200 | #define R_MAC_DMA_CONFIG1 0x00000008 | ||
| 201 | #define R_MAC_DMA_DSCR_BASE 0x00000010 | ||
| 202 | #define R_MAC_DMA_DSCR_CNT 0x00000018 | ||
| 203 | #define R_MAC_DMA_CUR_DSCRA 0x00000020 | ||
| 204 | #define R_MAC_DMA_CUR_DSCRB 0x00000028 | ||
| 205 | #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 | ||
| 206 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 207 | #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ | ||
| 208 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 209 | |||
| 210 | /* | ||
| 211 | * RMON Counters | ||
| 212 | */ | ||
| 213 | |||
| 214 | #define R_MAC_RMON_TX_BYTES 0x00000000 | ||
| 215 | #define R_MAC_RMON_COLLISIONS 0x00000008 | ||
| 216 | #define R_MAC_RMON_LATE_COL 0x00000010 | ||
| 217 | #define R_MAC_RMON_EX_COL 0x00000018 | ||
| 218 | #define R_MAC_RMON_FCS_ERROR 0x00000020 | ||
| 219 | #define R_MAC_RMON_TX_ABORT 0x00000028 | ||
| 220 | /* Counter #6 (0x30) now reserved */ | ||
| 221 | #define R_MAC_RMON_TX_BAD 0x00000038 | ||
| 222 | #define R_MAC_RMON_TX_GOOD 0x00000040 | ||
| 223 | #define R_MAC_RMON_TX_RUNT 0x00000048 | ||
| 224 | #define R_MAC_RMON_TX_OVERSIZE 0x00000050 | ||
| 225 | #define R_MAC_RMON_RX_BYTES 0x00000080 | ||
| 226 | #define R_MAC_RMON_RX_MCAST 0x00000088 | ||
| 227 | #define R_MAC_RMON_RX_BCAST 0x00000090 | ||
| 228 | #define R_MAC_RMON_RX_BAD 0x00000098 | ||
| 229 | #define R_MAC_RMON_RX_GOOD 0x000000A0 | ||
| 230 | #define R_MAC_RMON_RX_RUNT 0x000000A8 | ||
| 231 | #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 | ||
| 232 | #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 | ||
| 233 | #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 | ||
| 234 | #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 | ||
| 235 | #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 | ||
| 236 | |||
| 237 | /* Updated to spec 0.2 */ | ||
| 238 | #define R_MAC_CFG 0x00000100 | ||
| 239 | #define R_MAC_THRSH_CFG 0x00000108 | ||
| 240 | #define R_MAC_VLANTAG 0x00000110 | ||
| 241 | #define R_MAC_FRAMECFG 0x00000118 | ||
| 242 | #define R_MAC_EOPCNT 0x00000120 | ||
| 243 | #define R_MAC_FIFO_PTRS 0x00000128 | ||
| 244 | #define R_MAC_ADFILTER_CFG 0x00000200 | ||
| 245 | #define R_MAC_ETHERNET_ADDR 0x00000208 | ||
| 246 | #define R_MAC_PKT_TYPE 0x00000210 | ||
| 247 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 248 | #define R_MAC_ADMASK0 0x00000218 | ||
| 249 | #define R_MAC_ADMASK1 0x00000220 | ||
| 250 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 251 | #define R_MAC_HASH_BASE 0x00000240 | ||
| 252 | #define R_MAC_ADDR_BASE 0x00000280 | ||
| 253 | #define R_MAC_CHLO0_BASE 0x00000300 | ||
| 254 | #define R_MAC_CHUP0_BASE 0x00000320 | ||
| 255 | #define R_MAC_ENABLE 0x00000400 | ||
| 256 | #define R_MAC_STATUS 0x00000408 | ||
| 257 | #define R_MAC_INT_MASK 0x00000410 | ||
| 258 | #define R_MAC_TXD_CTL 0x00000420 | ||
| 259 | #define R_MAC_MDIO 0x00000428 | ||
| 260 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 261 | #define R_MAC_STATUS1 0x00000430 | ||
| 262 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 263 | #define R_MAC_DEBUG_STATUS 0x00000448 | ||
| 264 | |||
| 265 | #define MAC_HASH_COUNT 8 | ||
| 266 | #define MAC_ADDR_COUNT 8 | ||
| 267 | #define MAC_CHMAP_COUNT 4 | ||
| 268 | |||
| 269 | |||
| 270 | /* ********************************************************************* | ||
| 271 | * DUART Registers | ||
| 272 | ********************************************************************* */ | ||
| 273 | |||
| 274 | |||
| 275 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 276 | #define R_DUART_NUM_PORTS 2 | ||
| 277 | |||
| 278 | #define A_DUART 0x0010060000 | ||
| 279 | |||
| 280 | #define DUART_CHANREG_SPACING 0x100 | ||
| 281 | |||
| 282 | #define A_DUART_CHANREG(chan, reg) \ | ||
| 283 | (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) | ||
| 284 | #endif /* 1250 & 112x */ | ||
| 285 | |||
| 286 | #define R_DUART_MODE_REG_1 0x000 | ||
| 287 | #define R_DUART_MODE_REG_2 0x010 | ||
| 288 | #define R_DUART_STATUS 0x020 | ||
| 289 | #define R_DUART_CLK_SEL 0x030 | ||
| 290 | #define R_DUART_CMD 0x050 | ||
| 291 | #define R_DUART_RX_HOLD 0x060 | ||
| 292 | #define R_DUART_TX_HOLD 0x070 | ||
| 293 | |||
| 294 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 295 | #define R_DUART_FULL_CTL 0x040 | ||
| 296 | #define R_DUART_OPCR_X 0x080 | ||
| 297 | #define R_DUART_AUXCTL_X 0x090 | ||
| 298 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 299 | |||
| 300 | |||
| 301 | /* | ||
| 302 | * The IMR and ISR can't be addressed with A_DUART_CHANREG, | ||
| 303 | * so use these macros instead. | ||
| 304 | */ | ||
| 305 | |||
| 306 | #if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ | ||
| 307 | #define DUART_IMRISR_SPACING 0x20 | ||
| 308 | #define DUART_INCHNG_SPACING 0x10 | ||
| 309 | |||
| 310 | #define A_DUART_CTRLREG(reg) \ | ||
| 311 | (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) | ||
| 312 | |||
| 313 | #define R_DUART_IMRREG(chan) \ | ||
| 314 | (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) | ||
| 315 | #define R_DUART_ISRREG(chan) \ | ||
| 316 | (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) | ||
| 317 | #define R_DUART_INCHREG(chan) \ | ||
| 318 | (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) | ||
| 319 | |||
| 320 | #define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) | ||
| 321 | #define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) | ||
| 322 | #define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) | ||
| 323 | #endif /* 1250 & 112x */ | ||
| 324 | |||
| 325 | #define R_DUART_AUX_CTRL 0x010 | ||
| 326 | #define R_DUART_ISR_A 0x020 | ||
| 327 | #define R_DUART_IMR_A 0x030 | ||
| 328 | #define R_DUART_ISR_B 0x040 | ||
| 329 | #define R_DUART_IMR_B 0x050 | ||
| 330 | #define R_DUART_OUT_PORT 0x060 | ||
| 331 | #define R_DUART_OPCR 0x070 | ||
| 332 | #define R_DUART_IN_PORT 0x080 | ||
| 333 | |||
| 334 | #define R_DUART_SET_OPR 0x0B0 | ||
| 335 | #define R_DUART_CLEAR_OPR 0x0C0 | ||
| 336 | #define R_DUART_IN_CHNG_A 0x0D0 | ||
| 337 | #define R_DUART_IN_CHNG_B 0x0E0 | ||
| 338 | |||
| 339 | |||
| 340 | /* | ||
| 341 | * These constants are the absolute addresses. | ||
| 342 | */ | ||
| 343 | |||
| 344 | #define A_DUART_MODE_REG_1_A 0x0010060100 | ||
| 345 | #define A_DUART_MODE_REG_2_A 0x0010060110 | ||
| 346 | #define A_DUART_STATUS_A 0x0010060120 | ||
| 347 | #define A_DUART_CLK_SEL_A 0x0010060130 | ||
| 348 | #define A_DUART_CMD_A 0x0010060150 | ||
| 349 | #define A_DUART_RX_HOLD_A 0x0010060160 | ||
| 350 | #define A_DUART_TX_HOLD_A 0x0010060170 | ||
| 351 | |||
| 352 | #define A_DUART_MODE_REG_1_B 0x0010060200 | ||
| 353 | #define A_DUART_MODE_REG_2_B 0x0010060210 | ||
| 354 | #define A_DUART_STATUS_B 0x0010060220 | ||
| 355 | #define A_DUART_CLK_SEL_B 0x0010060230 | ||
| 356 | #define A_DUART_CMD_B 0x0010060250 | ||
| 357 | #define A_DUART_RX_HOLD_B 0x0010060260 | ||
| 358 | #define A_DUART_TX_HOLD_B 0x0010060270 | ||
| 359 | |||
| 360 | #define A_DUART_INPORT_CHNG 0x0010060300 | ||
| 361 | #define A_DUART_AUX_CTRL 0x0010060310 | ||
| 362 | #define A_DUART_ISR_A 0x0010060320 | ||
| 363 | #define A_DUART_IMR_A 0x0010060330 | ||
| 364 | #define A_DUART_ISR_B 0x0010060340 | ||
| 365 | #define A_DUART_IMR_B 0x0010060350 | ||
| 366 | #define A_DUART_OUT_PORT 0x0010060360 | ||
| 367 | #define A_DUART_OPCR 0x0010060370 | ||
| 368 | #define A_DUART_IN_PORT 0x0010060380 | ||
| 369 | #define A_DUART_ISR 0x0010060390 | ||
| 370 | #define A_DUART_IMR 0x00100603A0 | ||
| 371 | #define A_DUART_SET_OPR 0x00100603B0 | ||
| 372 | #define A_DUART_CLEAR_OPR 0x00100603C0 | ||
| 373 | #define A_DUART_INPORT_CHNG_A 0x00100603D0 | ||
| 374 | #define A_DUART_INPORT_CHNG_B 0x00100603E0 | ||
| 375 | |||
| 376 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 377 | #define A_DUART_FULL_CTL_A 0x0010060140 | ||
| 378 | #define A_DUART_FULL_CTL_B 0x0010060240 | ||
| 379 | |||
| 380 | #define A_DUART_OPCR_A 0x0010060180 | ||
| 381 | #define A_DUART_OPCR_B 0x0010060280 | ||
| 382 | |||
| 383 | #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 | ||
| 384 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 385 | |||
| 386 | |||
| 387 | /* ********************************************************************* | ||
| 388 | * Synchronous Serial Registers | ||
| 389 | ********************************************************************* */ | ||
| 390 | |||
| 391 | |||
| 392 | #if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ | ||
| 393 | |||
| 394 | #define A_SER_BASE_0 0x0010060400 | ||
| 395 | #define A_SER_BASE_1 0x0010060800 | ||
| 396 | #define SER_SPACING 0x400 | ||
| 397 | |||
| 398 | #define SER_DMA_TXRX_SPACING 0x80 | ||
| 399 | |||
| 400 | #define SER_NUM_PORTS 2 | ||
| 401 | |||
| 402 | #define A_SER_CHANNEL_BASE(sernum) \ | ||
| 403 | (A_SER_BASE_0 + \ | ||
| 404 | SER_SPACING*(sernum)) | ||
| 405 | |||
| 406 | #define A_SER_REGISTER(sernum,reg) \ | ||
| 407 | (A_SER_BASE_0 + \ | ||
| 408 | SER_SPACING*(sernum) + (reg)) | ||
| 409 | |||
| 410 | |||
| 411 | #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ | ||
| 412 | |||
| 413 | #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ | ||
| 414 | ((A_SER_CHANNEL_BASE(sernum)) + \ | ||
| 415 | R_SER_DMA_CHANNELS + \ | ||
| 416 | (SER_DMA_TXRX_SPACING*(txrx))) | ||
| 417 | |||
| 418 | #define A_SER_DMA_REGISTER(sernum, txrx, reg) \ | ||
| 419 | (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ | ||
| 420 | (reg)) | ||
| 421 | |||
| 422 | |||
| 423 | /* | ||
| 424 | * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE | ||
| 425 | */ | ||
| 426 | |||
| 427 | #define R_SER_DMA_CONFIG0 0x00000000 | ||
| 428 | #define R_SER_DMA_CONFIG1 0x00000008 | ||
| 429 | #define R_SER_DMA_DSCR_BASE 0x00000010 | ||
| 430 | #define R_SER_DMA_DSCR_CNT 0x00000018 | ||
| 431 | #define R_SER_DMA_CUR_DSCRA 0x00000020 | ||
| 432 | #define R_SER_DMA_CUR_DSCRB 0x00000028 | ||
| 433 | #define R_SER_DMA_CUR_DSCRADDR 0x00000030 | ||
| 434 | |||
| 435 | #define R_SER_DMA_CONFIG0_RX 0x00000000 | ||
| 436 | #define R_SER_DMA_CONFIG1_RX 0x00000008 | ||
| 437 | #define R_SER_DMA_DSCR_BASE_RX 0x00000010 | ||
| 438 | #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 | ||
| 439 | #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 | ||
| 440 | #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 | ||
| 441 | #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 | ||
| 442 | |||
| 443 | #define R_SER_DMA_CONFIG0_TX 0x00000080 | ||
| 444 | #define R_SER_DMA_CONFIG1_TX 0x00000088 | ||
| 445 | #define R_SER_DMA_DSCR_BASE_TX 0x00000090 | ||
| 446 | #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 | ||
| 447 | #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 | ||
| 448 | #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 | ||
| 449 | #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 | ||
| 450 | |||
| 451 | #define R_SER_MODE 0x00000100 | ||
| 452 | #define R_SER_MINFRM_SZ 0x00000108 | ||
| 453 | #define R_SER_MAXFRM_SZ 0x00000110 | ||
| 454 | #define R_SER_ADDR 0x00000118 | ||
| 455 | #define R_SER_USR0_ADDR 0x00000120 | ||
| 456 | #define R_SER_USR1_ADDR 0x00000128 | ||
| 457 | #define R_SER_USR2_ADDR 0x00000130 | ||
| 458 | #define R_SER_USR3_ADDR 0x00000138 | ||
| 459 | #define R_SER_CMD 0x00000140 | ||
| 460 | #define R_SER_TX_RD_THRSH 0x00000160 | ||
| 461 | #define R_SER_TX_WR_THRSH 0x00000168 | ||
| 462 | #define R_SER_RX_RD_THRSH 0x00000170 | ||
| 463 | #define R_SER_LINE_MODE 0x00000178 | ||
| 464 | #define R_SER_DMA_ENABLE 0x00000180 | ||
| 465 | #define R_SER_INT_MASK 0x00000190 | ||
| 466 | #define R_SER_STATUS 0x00000188 | ||
| 467 | #define R_SER_STATUS_DEBUG 0x000001A8 | ||
| 468 | #define R_SER_RX_TABLE_BASE 0x00000200 | ||
| 469 | #define SER_RX_TABLE_COUNT 16 | ||
| 470 | #define R_SER_TX_TABLE_BASE 0x00000300 | ||
| 471 | #define SER_TX_TABLE_COUNT 16 | ||
| 472 | |||
| 473 | /* RMON Counters */ | ||
| 474 | #define R_SER_RMON_TX_BYTE_LO 0x000001C0 | ||
| 475 | #define R_SER_RMON_TX_BYTE_HI 0x000001C8 | ||
| 476 | #define R_SER_RMON_RX_BYTE_LO 0x000001D0 | ||
| 477 | #define R_SER_RMON_RX_BYTE_HI 0x000001D8 | ||
| 478 | #define R_SER_RMON_TX_UNDERRUN 0x000001E0 | ||
| 479 | #define R_SER_RMON_RX_OVERFLOW 0x000001E8 | ||
| 480 | #define R_SER_RMON_RX_ERRORS 0x000001F0 | ||
| 481 | #define R_SER_RMON_RX_BADADDR 0x000001F8 | ||
| 482 | |||
| 483 | #endif /* 1250/112x */ | ||
| 484 | |||
| 485 | /* ********************************************************************* | ||
| 486 | * Generic Bus Registers | ||
| 487 | ********************************************************************* */ | ||
| 488 | |||
| 489 | #define IO_EXT_CFG_COUNT 8 | ||
| 490 | |||
| 491 | #define A_IO_EXT_BASE 0x0010061000 | ||
| 492 | #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) | ||
| 493 | |||
| 494 | #define A_IO_EXT_CFG_BASE 0x0010061000 | ||
| 495 | #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 | ||
| 496 | #define A_IO_EXT_START_ADDR_BASE 0x0010061200 | ||
| 497 | #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 | ||
| 498 | #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 | ||
| 499 | |||
| 500 | #define IO_EXT_REGISTER_SPACING 8 | ||
| 501 | #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) | ||
| 502 | #define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) | ||
| 503 | |||
| 504 | #define R_IO_EXT_CFG 0x0000 | ||
| 505 | #define R_IO_EXT_MULT_SIZE 0x0100 | ||
| 506 | #define R_IO_EXT_START_ADDR 0x0200 | ||
| 507 | #define R_IO_EXT_TIME_CFG0 0x0600 | ||
| 508 | #define R_IO_EXT_TIME_CFG1 0x0700 | ||
| 509 | |||
| 510 | |||
| 511 | #define A_IO_INTERRUPT_STATUS 0x0010061A00 | ||
| 512 | #define A_IO_INTERRUPT_DATA0 0x0010061A10 | ||
| 513 | #define A_IO_INTERRUPT_DATA1 0x0010061A18 | ||
| 514 | #define A_IO_INTERRUPT_DATA2 0x0010061A20 | ||
| 515 | #define A_IO_INTERRUPT_DATA3 0x0010061A28 | ||
| 516 | #define A_IO_INTERRUPT_ADDR0 0x0010061A30 | ||
| 517 | #define A_IO_INTERRUPT_ADDR1 0x0010061A40 | ||
| 518 | #define A_IO_INTERRUPT_PARITY 0x0010061A50 | ||
| 519 | #define A_IO_PCMCIA_CFG 0x0010061A60 | ||
| 520 | #define A_IO_PCMCIA_STATUS 0x0010061A70 | ||
| 521 | #define A_IO_DRIVE_0 0x0010061300 | ||
| 522 | #define A_IO_DRIVE_1 0x0010061308 | ||
| 523 | #define A_IO_DRIVE_2 0x0010061310 | ||
| 524 | #define A_IO_DRIVE_3 0x0010061318 | ||
| 525 | #define A_IO_DRIVE_BASE A_IO_DRIVE_0 | ||
| 526 | #define IO_DRIVE_REGISTER_SPACING 8 | ||
| 527 | #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) | ||
| 528 | #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) | ||
| 529 | |||
| 530 | #define R_IO_INTERRUPT_STATUS 0x0A00 | ||
| 531 | #define R_IO_INTERRUPT_DATA0 0x0A10 | ||
| 532 | #define R_IO_INTERRUPT_DATA1 0x0A18 | ||
| 533 | #define R_IO_INTERRUPT_DATA2 0x0A20 | ||
| 534 | #define R_IO_INTERRUPT_DATA3 0x0A28 | ||
| 535 | #define R_IO_INTERRUPT_ADDR0 0x0A30 | ||
| 536 | #define R_IO_INTERRUPT_ADDR1 0x0A40 | ||
| 537 | #define R_IO_INTERRUPT_PARITY 0x0A50 | ||
| 538 | #define R_IO_PCMCIA_CFG 0x0A60 | ||
| 539 | #define R_IO_PCMCIA_STATUS 0x0A70 | ||
| 540 | |||
| 541 | /* ********************************************************************* | ||
| 542 | * GPIO Registers | ||
| 543 | ********************************************************************* */ | ||
| 544 | |||
| 545 | #define A_GPIO_CLR_EDGE 0x0010061A80 | ||
| 546 | #define A_GPIO_INT_TYPE 0x0010061A88 | ||
| 547 | #define A_GPIO_INPUT_INVERT 0x0010061A90 | ||
| 548 | #define A_GPIO_GLITCH 0x0010061A98 | ||
| 549 | #define A_GPIO_READ 0x0010061AA0 | ||
| 550 | #define A_GPIO_DIRECTION 0x0010061AA8 | ||
| 551 | #define A_GPIO_PIN_CLR 0x0010061AB0 | ||
| 552 | #define A_GPIO_PIN_SET 0x0010061AB8 | ||
| 553 | |||
| 554 | #define A_GPIO_BASE 0x0010061A80 | ||
| 555 | |||
| 556 | #define R_GPIO_CLR_EDGE 0x00 | ||
| 557 | #define R_GPIO_INT_TYPE 0x08 | ||
| 558 | #define R_GPIO_INPUT_INVERT 0x10 | ||
| 559 | #define R_GPIO_GLITCH 0x18 | ||
| 560 | #define R_GPIO_READ 0x20 | ||
| 561 | #define R_GPIO_DIRECTION 0x28 | ||
| 562 | #define R_GPIO_PIN_CLR 0x30 | ||
| 563 | #define R_GPIO_PIN_SET 0x38 | ||
| 564 | |||
| 565 | /* ********************************************************************* | ||
| 566 | * SMBus Registers | ||
| 567 | ********************************************************************* */ | ||
| 568 | |||
| 569 | #define A_SMB_XTRA_0 0x0010060000 | ||
| 570 | #define A_SMB_XTRA_1 0x0010060008 | ||
| 571 | #define A_SMB_FREQ_0 0x0010060010 | ||
| 572 | #define A_SMB_FREQ_1 0x0010060018 | ||
| 573 | #define A_SMB_STATUS_0 0x0010060020 | ||
| 574 | #define A_SMB_STATUS_1 0x0010060028 | ||
| 575 | #define A_SMB_CMD_0 0x0010060030 | ||
| 576 | #define A_SMB_CMD_1 0x0010060038 | ||
| 577 | #define A_SMB_START_0 0x0010060040 | ||
| 578 | #define A_SMB_START_1 0x0010060048 | ||
| 579 | #define A_SMB_DATA_0 0x0010060050 | ||
| 580 | #define A_SMB_DATA_1 0x0010060058 | ||
| 581 | #define A_SMB_CONTROL_0 0x0010060060 | ||
| 582 | #define A_SMB_CONTROL_1 0x0010060068 | ||
| 583 | #define A_SMB_PEC_0 0x0010060070 | ||
| 584 | #define A_SMB_PEC_1 0x0010060078 | ||
| 585 | |||
| 586 | #define A_SMB_0 0x0010060000 | ||
| 587 | #define A_SMB_1 0x0010060008 | ||
| 588 | #define SMB_REGISTER_SPACING 0x8 | ||
| 589 | #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) | ||
| 590 | #define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) | ||
| 591 | |||
| 592 | #define R_SMB_XTRA 0x0000000000 | ||
| 593 | #define R_SMB_FREQ 0x0000000010 | ||
| 594 | #define R_SMB_STATUS 0x0000000020 | ||
| 595 | #define R_SMB_CMD 0x0000000030 | ||
| 596 | #define R_SMB_START 0x0000000040 | ||
| 597 | #define R_SMB_DATA 0x0000000050 | ||
| 598 | #define R_SMB_CONTROL 0x0000000060 | ||
| 599 | #define R_SMB_PEC 0x0000000070 | ||
| 600 | |||
| 601 | /* ********************************************************************* | ||
| 602 | * Timer Registers | ||
| 603 | ********************************************************************* */ | ||
| 604 | |||
| 605 | /* | ||
| 606 | * Watchdog timers | ||
| 607 | */ | ||
| 608 | |||
| 609 | #define A_SCD_WDOG_0 0x0010020050 | ||
| 610 | #define A_SCD_WDOG_1 0x0010020150 | ||
| 611 | #define SCD_WDOG_SPACING 0x100 | ||
| 612 | #define SCD_NUM_WDOGS 2 | ||
| 613 | #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) | ||
| 614 | #define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) | ||
| 615 | |||
| 616 | #define R_SCD_WDOG_INIT 0x0000000000 | ||
| 617 | #define R_SCD_WDOG_CNT 0x0000000008 | ||
| 618 | #define R_SCD_WDOG_CFG 0x0000000010 | ||
| 619 | |||
| 620 | #define A_SCD_WDOG_INIT_0 0x0010020050 | ||
| 621 | #define A_SCD_WDOG_CNT_0 0x0010020058 | ||
| 622 | #define A_SCD_WDOG_CFG_0 0x0010020060 | ||
| 623 | |||
| 624 | #define A_SCD_WDOG_INIT_1 0x0010020150 | ||
| 625 | #define A_SCD_WDOG_CNT_1 0x0010020158 | ||
| 626 | #define A_SCD_WDOG_CFG_1 0x0010020160 | ||
| 627 | |||
| 628 | /* | ||
| 629 | * Generic timers | ||
| 630 | */ | ||
| 631 | |||
| 632 | #define A_SCD_TIMER_0 0x0010020070 | ||
| 633 | #define A_SCD_TIMER_1 0x0010020078 | ||
| 634 | #define A_SCD_TIMER_2 0x0010020170 | ||
| 635 | #define A_SCD_TIMER_3 0x0010020178 | ||
| 636 | #define SCD_NUM_TIMERS 4 | ||
| 637 | #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) | ||
| 638 | #define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) | ||
| 639 | |||
| 640 | #define R_SCD_TIMER_INIT 0x0000000000 | ||
| 641 | #define R_SCD_TIMER_CNT 0x0000000010 | ||
| 642 | #define R_SCD_TIMER_CFG 0x0000000020 | ||
| 643 | |||
| 644 | #define A_SCD_TIMER_INIT_0 0x0010020070 | ||
| 645 | #define A_SCD_TIMER_CNT_0 0x0010020080 | ||
| 646 | #define A_SCD_TIMER_CFG_0 0x0010020090 | ||
| 647 | |||
| 648 | #define A_SCD_TIMER_INIT_1 0x0010020078 | ||
| 649 | #define A_SCD_TIMER_CNT_1 0x0010020088 | ||
| 650 | #define A_SCD_TIMER_CFG_1 0x0010020098 | ||
| 651 | |||
| 652 | #define A_SCD_TIMER_INIT_2 0x0010020170 | ||
| 653 | #define A_SCD_TIMER_CNT_2 0x0010020180 | ||
| 654 | #define A_SCD_TIMER_CFG_2 0x0010020190 | ||
| 655 | |||
| 656 | #define A_SCD_TIMER_INIT_3 0x0010020178 | ||
| 657 | #define A_SCD_TIMER_CNT_3 0x0010020188 | ||
| 658 | #define A_SCD_TIMER_CFG_3 0x0010020198 | ||
| 659 | |||
| 660 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 661 | #define A_SCD_SCRATCH 0x0010020C10 | ||
| 662 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 663 | |||
| 664 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 665 | #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 | ||
| 666 | #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 | ||
| 667 | #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 | ||
| 668 | #endif | ||
| 669 | |||
| 670 | /* ********************************************************************* | ||
| 671 | * System Control Registers | ||
| 672 | ********************************************************************* */ | ||
| 673 | |||
| 674 | #define A_SCD_SYSTEM_REVISION 0x0010020000 | ||
| 675 | #define A_SCD_SYSTEM_CFG 0x0010020008 | ||
| 676 | #define A_SCD_SYSTEM_MANUF 0x0010038000 | ||
| 677 | |||
| 678 | /* ********************************************************************* | ||
| 679 | * System Address Trap Registers | ||
| 680 | ********************************************************************* */ | ||
| 681 | |||
| 682 | #define A_ADDR_TRAP_INDEX 0x00100200B0 | ||
| 683 | #define A_ADDR_TRAP_REG 0x00100200B8 | ||
| 684 | #define A_ADDR_TRAP_UP_0 0x0010020400 | ||
| 685 | #define A_ADDR_TRAP_UP_1 0x0010020408 | ||
| 686 | #define A_ADDR_TRAP_UP_2 0x0010020410 | ||
| 687 | #define A_ADDR_TRAP_UP_3 0x0010020418 | ||
| 688 | #define A_ADDR_TRAP_DOWN_0 0x0010020420 | ||
| 689 | #define A_ADDR_TRAP_DOWN_1 0x0010020428 | ||
| 690 | #define A_ADDR_TRAP_DOWN_2 0x0010020430 | ||
| 691 | #define A_ADDR_TRAP_DOWN_3 0x0010020438 | ||
| 692 | #define A_ADDR_TRAP_CFG_0 0x0010020440 | ||
| 693 | #define A_ADDR_TRAP_CFG_1 0x0010020448 | ||
| 694 | #define A_ADDR_TRAP_CFG_2 0x0010020450 | ||
| 695 | #define A_ADDR_TRAP_CFG_3 0x0010020458 | ||
| 696 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 697 | #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 | ||
| 698 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 699 | |||
| 700 | #define ADDR_TRAP_SPACING 8 | ||
| 701 | #define NUM_ADDR_TRAP 4 | ||
| 702 | #define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) | ||
| 703 | #define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) | ||
| 704 | #define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) | ||
| 705 | |||
| 706 | |||
| 707 | /* ********************************************************************* | ||
| 708 | * System Interrupt Mapper Registers | ||
| 709 | ********************************************************************* */ | ||
| 710 | |||
| 711 | #define A_IMR_CPU0_BASE 0x0010020000 | ||
| 712 | #define A_IMR_CPU1_BASE 0x0010022000 | ||
| 713 | #define IMR_REGISTER_SPACING 0x2000 | ||
| 714 | #define IMR_REGISTER_SPACING_SHIFT 13 | ||
| 715 | |||
| 716 | #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) | ||
| 717 | #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) | ||
| 718 | |||
| 719 | #define R_IMR_INTERRUPT_DIAG 0x0010 | ||
| 720 | #define R_IMR_INTERRUPT_LDT 0x0018 | ||
| 721 | #define R_IMR_INTERRUPT_MASK 0x0028 | ||
| 722 | #define R_IMR_INTERRUPT_TRACE 0x0038 | ||
| 723 | #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 | ||
| 724 | #define R_IMR_LDT_INTERRUPT_SET 0x0048 | ||
| 725 | #define R_IMR_LDT_INTERRUPT 0x0018 | ||
| 726 | #define R_IMR_LDT_INTERRUPT_CLR 0x0020 | ||
| 727 | #define R_IMR_MAILBOX_CPU 0x00c0 | ||
| 728 | #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 | ||
| 729 | #define R_IMR_MAILBOX_SET_CPU 0x00C8 | ||
| 730 | #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 | ||
| 731 | #define R_IMR_MAILBOX_CLR_CPU 0x00D0 | ||
| 732 | #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 | ||
| 733 | #define R_IMR_INTERRUPT_STATUS_COUNT 7 | ||
| 734 | #define R_IMR_INTERRUPT_MAP_BASE 0x0200 | ||
| 735 | #define R_IMR_INTERRUPT_MAP_COUNT 64 | ||
| 736 | |||
| 737 | /* | ||
| 738 | * these macros work together to build the address of a mailbox | ||
| 739 | * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1) | ||
| 740 | * for mbox_0_set_cpu2 returns 0x00100240C8 | ||
| 741 | */ | ||
| 742 | #define A_MAILBOX_REGISTER(reg,cpu) \ | ||
| 743 | (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) | ||
| 744 | |||
| 745 | /* ********************************************************************* | ||
| 746 | * System Performance Counter Registers | ||
| 747 | ********************************************************************* */ | ||
| 748 | |||
| 749 | #define A_SCD_PERF_CNT_CFG 0x00100204C0 | ||
| 750 | #define A_SCD_PERF_CNT_0 0x00100204D0 | ||
| 751 | #define A_SCD_PERF_CNT_1 0x00100204D8 | ||
| 752 | #define A_SCD_PERF_CNT_2 0x00100204E0 | ||
| 753 | #define A_SCD_PERF_CNT_3 0x00100204E8 | ||
| 754 | |||
| 755 | #define SCD_NUM_PERF_CNT 4 | ||
| 756 | #define SCD_PERF_CNT_SPACING 8 | ||
| 757 | #define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) | ||
| 758 | |||
| 759 | /* ********************************************************************* | ||
| 760 | * System Bus Watcher Registers | ||
| 761 | ********************************************************************* */ | ||
| 762 | |||
| 763 | #define A_SCD_BUS_ERR_STATUS 0x0010020880 | ||
| 764 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 765 | #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 | ||
| 766 | #define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 | ||
| 767 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 768 | #define A_BUS_ERR_DATA_0 0x00100208A0 | ||
| 769 | #define A_BUS_ERR_DATA_1 0x00100208A8 | ||
| 770 | #define A_BUS_ERR_DATA_2 0x00100208B0 | ||
| 771 | #define A_BUS_ERR_DATA_3 0x00100208B8 | ||
| 772 | #define A_BUS_L2_ERRORS 0x00100208C0 | ||
| 773 | #define A_BUS_MEM_IO_ERRORS 0x00100208C8 | ||
| 774 | |||
| 775 | /* ********************************************************************* | ||
| 776 | * System Debug Controller Registers | ||
| 777 | ********************************************************************* */ | ||
| 778 | |||
| 779 | #define A_SCD_JTAG_BASE 0x0010000000 | ||
| 780 | |||
| 781 | /* ********************************************************************* | ||
| 782 | * System Trace Buffer Registers | ||
| 783 | ********************************************************************* */ | ||
| 784 | |||
| 785 | #define A_SCD_TRACE_CFG 0x0010020A00 | ||
| 786 | #define A_SCD_TRACE_READ 0x0010020A08 | ||
| 787 | #define A_SCD_TRACE_EVENT_0 0x0010020A20 | ||
| 788 | #define A_SCD_TRACE_EVENT_1 0x0010020A28 | ||
| 789 | #define A_SCD_TRACE_EVENT_2 0x0010020A30 | ||
| 790 | #define A_SCD_TRACE_EVENT_3 0x0010020A38 | ||
| 791 | #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 | ||
| 792 | #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 | ||
| 793 | #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 | ||
| 794 | #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 | ||
| 795 | #define A_SCD_TRACE_EVENT_4 0x0010020A60 | ||
| 796 | #define A_SCD_TRACE_EVENT_5 0x0010020A68 | ||
| 797 | #define A_SCD_TRACE_EVENT_6 0x0010020A70 | ||
| 798 | #define A_SCD_TRACE_EVENT_7 0x0010020A78 | ||
| 799 | #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 | ||
| 800 | #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 | ||
| 801 | #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 | ||
| 802 | #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 | ||
| 803 | |||
| 804 | #define TRACE_REGISTER_SPACING 8 | ||
| 805 | #define TRACE_NUM_REGISTERS 8 | ||
| 806 | #define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ | ||
| 807 | (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ | ||
| 808 | (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING))) | ||
| 809 | #define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ | ||
| 810 | (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ | ||
| 811 | (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING))) | ||
| 812 | |||
| 813 | /* ********************************************************************* | ||
| 814 | * System Generic DMA Registers | ||
| 815 | ********************************************************************* */ | ||
| 816 | |||
| 817 | #define A_DM_0 0x0010020B00 | ||
| 818 | #define A_DM_1 0x0010020B20 | ||
| 819 | #define A_DM_2 0x0010020B40 | ||
| 820 | #define A_DM_3 0x0010020B60 | ||
| 821 | #define DM_REGISTER_SPACING 0x20 | ||
| 822 | #define DM_NUM_CHANNELS 4 | ||
| 823 | #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) | ||
| 824 | #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) | ||
| 825 | |||
| 826 | #define R_DM_DSCR_BASE 0x0000000000 | ||
| 827 | #define R_DM_DSCR_COUNT 0x0000000008 | ||
| 828 | #define R_DM_CUR_DSCR_ADDR 0x0000000010 | ||
| 829 | #define R_DM_DSCR_BASE_DEBUG 0x0000000018 | ||
| 830 | |||
| 831 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 832 | #define A_DM_PARTIAL_0 0x0010020ba0 | ||
| 833 | #define A_DM_PARTIAL_1 0x0010020ba8 | ||
| 834 | #define A_DM_PARTIAL_2 0x0010020bb0 | ||
| 835 | #define A_DM_PARTIAL_3 0x0010020bb8 | ||
| 836 | #define DM_PARTIAL_REGISTER_SPACING 0x8 | ||
| 837 | #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) | ||
| 838 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 839 | |||
| 840 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 841 | #define A_DM_CRC_0 0x0010020b80 | ||
| 842 | #define A_DM_CRC_1 0x0010020b90 | ||
| 843 | #define DM_CRC_REGISTER_SPACING 0x10 | ||
| 844 | #define DM_CRC_NUM_CHANNELS 2 | ||
| 845 | #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) | ||
| 846 | #define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) | ||
| 847 | |||
| 848 | #define R_CRC_DEF_0 0x00 | ||
| 849 | #define R_CTCP_DEF_0 0x08 | ||
| 850 | #endif /* 1250 PASS3 || 112x PASS1 */ | ||
| 851 | |||
| 852 | /* ********************************************************************* | ||
| 853 | * Physical Address Map | ||
| 854 | ********************************************************************* */ | ||
| 855 | |||
| 856 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 857 | #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) | ||
| 858 | #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) | ||
| 859 | #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) | ||
| 860 | #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) | ||
| 861 | #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) | ||
| 862 | #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) | ||
| 863 | #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) | ||
| 864 | #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) | ||
| 865 | #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) | ||
| 866 | #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) | ||
| 867 | #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) | ||
| 868 | #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) | ||
| 869 | #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) | ||
| 870 | #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) | ||
| 871 | #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) | ||
| 872 | #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) | ||
| 873 | #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) | ||
| 874 | #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) | ||
| 875 | #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) | ||
| 876 | #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) | ||
| 877 | #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) | ||
| 878 | #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) | ||
| 879 | #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) | ||
| 880 | #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) | ||
| 881 | #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) | ||
| 882 | |||
| 883 | #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) | ||
| 884 | #define PHYS_L2CACHE_NUM_WAYS 4 | ||
| 885 | #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) | ||
| 886 | #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) | ||
| 887 | #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) | ||
| 888 | #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) | ||
| 889 | #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) | ||
| 890 | #endif | ||
| 891 | |||
| 892 | |||
| 893 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h new file mode 100644 index 000000000000..e49c3e89b5ee --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_scd.h | |||
| @@ -0,0 +1,654 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * SCD Constants and Macros File: sb1250_scd.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the System Control and Debug module on the 1250. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003,2004,2005 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | #ifndef _SB1250_SCD_H | ||
| 33 | #define _SB1250_SCD_H | ||
| 34 | |||
| 35 | #include "sb1250_defs.h" | ||
| 36 | |||
| 37 | /* ********************************************************************* | ||
| 38 | * System control/debug registers | ||
| 39 | ********************************************************************* */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * System Revision Register (Table 4-1) | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define M_SYS_RESERVED _SB_MAKEMASK(8, 0) | ||
| 46 | |||
| 47 | #define S_SYS_REVISION _SB_MAKE64(8) | ||
| 48 | #define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION) | ||
| 49 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION) | ||
| 50 | #define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION) | ||
| 51 | |||
| 52 | #define K_SYS_REVISION_BCM1250_PASS1 0x01 | ||
| 53 | |||
| 54 | #define K_SYS_REVISION_BCM1250_PASS2 0x03 | ||
| 55 | #define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */ | ||
| 56 | #define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */ | ||
| 57 | #define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */ | ||
| 58 | #define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */ | ||
| 59 | #define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */ | ||
| 60 | #define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */ | ||
| 61 | #define K_SYS_REVISION_BCM1250_A9 0x08 | ||
| 62 | #define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8 | ||
| 63 | |||
| 64 | #define K_SYS_REVISION_BCM1250_PASS2_2 0x10 | ||
| 65 | #define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1 | ||
| 66 | #define K_SYS_REVISION_BCM1250_B1 0x10 | ||
| 67 | #define K_SYS_REVISION_BCM1250_B2 0x11 | ||
| 68 | |||
| 69 | #define K_SYS_REVISION_BCM1250_C0 0x20 | ||
| 70 | #define K_SYS_REVISION_BCM1250_C1 0x21 | ||
| 71 | #define K_SYS_REVISION_BCM1250_C2 0x22 | ||
| 72 | #define K_SYS_REVISION_BCM1250_C3 0x23 | ||
| 73 | |||
| 74 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | ||
| 75 | /* XXX: discourage people from using these constants. */ | ||
| 76 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 | ||
| 77 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 | ||
| 78 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 | ||
| 79 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 | ||
| 80 | #define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0 | ||
| 81 | #endif /* 1250 */ | ||
| 82 | |||
| 83 | #define K_SYS_REVISION_BCM112x_A1 0x20 | ||
| 84 | #define K_SYS_REVISION_BCM112x_A2 0x21 | ||
| 85 | #define K_SYS_REVISION_BCM112x_A3 0x22 | ||
| 86 | #define K_SYS_REVISION_BCM112x_A4 0x23 | ||
| 87 | #define K_SYS_REVISION_BCM112x_B0 0x30 | ||
| 88 | |||
| 89 | #define K_SYS_REVISION_BCM1480_S0 0x01 | ||
| 90 | #define K_SYS_REVISION_BCM1480_A1 0x02 | ||
| 91 | #define K_SYS_REVISION_BCM1480_A2 0x03 | ||
| 92 | #define K_SYS_REVISION_BCM1480_A3 0x04 | ||
| 93 | #define K_SYS_REVISION_BCM1480_B0 0x11 | ||
| 94 | |||
| 95 | /*Cache size - 23:20 of revision register*/ | ||
| 96 | #define S_SYS_L2C_SIZE _SB_MAKE64(20) | ||
| 97 | #define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE) | ||
| 98 | #define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE) | ||
| 99 | #define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE) | ||
| 100 | |||
| 101 | #define K_SYS_L2C_SIZE_1MB 0 | ||
| 102 | #define K_SYS_L2C_SIZE_512KB 5 | ||
| 103 | #define K_SYS_L2C_SIZE_256KB 2 | ||
| 104 | #define K_SYS_L2C_SIZE_128KB 1 | ||
| 105 | |||
| 106 | #define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB | ||
| 107 | #define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB | ||
| 108 | #define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB | ||
| 109 | |||
| 110 | |||
| 111 | /* Number of CPU cores, bits 27:24 of revision register*/ | ||
| 112 | #define S_SYS_NUM_CPUS _SB_MAKE64(24) | ||
| 113 | #define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS) | ||
| 114 | #define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS) | ||
| 115 | #define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS) | ||
| 116 | |||
| 117 | |||
| 118 | /* XXX: discourage people from using these constants. */ | ||
| 119 | #define S_SYS_PART _SB_MAKE64(16) | ||
| 120 | #define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART) | ||
| 121 | #define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART) | ||
| 122 | #define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART) | ||
| 123 | |||
| 124 | /* XXX: discourage people from using these constants. */ | ||
| 125 | #define K_SYS_PART_SB1250 0x1250 | ||
| 126 | #define K_SYS_PART_BCM1120 0x1121 | ||
| 127 | #define K_SYS_PART_BCM1125 0x1123 | ||
| 128 | #define K_SYS_PART_BCM1125H 0x1124 | ||
| 129 | #define K_SYS_PART_BCM1122 0x1113 | ||
| 130 | |||
| 131 | |||
| 132 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ | ||
| 133 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) | ||
| 134 | #define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE) | ||
| 135 | #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE) | ||
| 136 | #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE) | ||
| 137 | |||
| 138 | #define K_SYS_SOC_TYPE_BCM1250 0x0 | ||
| 139 | #define K_SYS_SOC_TYPE_BCM1120 0x1 | ||
| 140 | #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ | ||
| 141 | #define K_SYS_SOC_TYPE_BCM1125 0x3 | ||
| 142 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 | ||
| 143 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ | ||
| 144 | #define K_SYS_SOC_TYPE_BCM1x80 0x6 | ||
| 145 | #define K_SYS_SOC_TYPE_BCM1x55 0x7 | ||
| 146 | |||
| 147 | /* | ||
| 148 | * Calculate correct SOC type given a copy of system revision register. | ||
| 149 | * | ||
| 150 | * (For the assembler version, sysrev and dest may be the same register. | ||
| 151 | * Also, it clobbers AT.) | ||
| 152 | */ | ||
| 153 | #ifdef __ASSEMBLER__ | ||
| 154 | #define SYS_SOC_TYPE(dest, sysrev) \ | ||
| 155 | .set push ; \ | ||
| 156 | .set reorder ; \ | ||
| 157 | dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ | ||
| 158 | andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ | ||
| 159 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ | ||
| 160 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ | ||
| 161 | b 992f ; \ | ||
| 162 | 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ | ||
| 163 | 992: \ | ||
| 164 | .set pop | ||
| 165 | #else | ||
| 166 | #define SYS_SOC_TYPE(sysrev) \ | ||
| 167 | ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ | ||
| 168 | || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ | ||
| 169 | ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) | ||
| 170 | #endif | ||
| 171 | |||
| 172 | #define S_SYS_WID _SB_MAKE64(32) | ||
| 173 | #define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID) | ||
| 174 | #define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID) | ||
| 175 | #define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID) | ||
| 176 | |||
| 177 | /* | ||
| 178 | * System Manufacturing Register | ||
| 179 | * Register: SCD_SYSTEM_MANUF | ||
| 180 | */ | ||
| 181 | |||
| 182 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 183 | /* Wafer ID: bits 31:0 */ | ||
| 184 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) | ||
| 185 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200) | ||
| 186 | #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200) | ||
| 187 | #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200) | ||
| 188 | |||
| 189 | #define S_SYS_BIN _SB_MAKE64(32) | ||
| 190 | #define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN) | ||
| 191 | #define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN) | ||
| 192 | #define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN) | ||
| 193 | |||
| 194 | /* Wafer ID: bits 39:36 */ | ||
| 195 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) | ||
| 196 | #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200) | ||
| 197 | #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200) | ||
| 198 | #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200) | ||
| 199 | |||
| 200 | /* Wafer ID: bits 39:0 */ | ||
| 201 | #define S_SYS_WAFERID_300 _SB_MAKE64(0) | ||
| 202 | #define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300) | ||
| 203 | #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300) | ||
| 204 | #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300) | ||
| 205 | |||
| 206 | #define S_SYS_XPOS _SB_MAKE64(40) | ||
| 207 | #define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS) | ||
| 208 | #define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS) | ||
| 209 | #define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS) | ||
| 210 | |||
| 211 | #define S_SYS_YPOS _SB_MAKE64(46) | ||
| 212 | #define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS) | ||
| 213 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS) | ||
| 214 | #define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS) | ||
| 215 | #endif | ||
| 216 | |||
| 217 | |||
| 218 | /* | ||
| 219 | * System Config Register (Table 4-2) | ||
| 220 | * Register: SCD_SYSTEM_CFG | ||
| 221 | */ | ||
| 222 | |||
| 223 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 224 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) | ||
| 225 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) | ||
| 226 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) | ||
| 227 | #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) | ||
| 228 | |||
| 229 | #define S_SYS_PLL_DIV _SB_MAKE64(7) | ||
| 230 | #define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV) | ||
| 231 | #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV) | ||
| 232 | #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV) | ||
| 233 | |||
| 234 | #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) | ||
| 235 | #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) | ||
| 236 | #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) | ||
| 237 | #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) | ||
| 238 | #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | ||
| 239 | |||
| 240 | #define S_SYS_BOOT_MODE _SB_MAKE64(17) | ||
| 241 | #define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE) | ||
| 242 | #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE) | ||
| 243 | #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE) | ||
| 244 | #define K_SYS_BOOT_MODE_ROM32 0 | ||
| 245 | #define K_SYS_BOOT_MODE_ROM8 1 | ||
| 246 | #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 | ||
| 247 | #define K_SYS_BOOT_MODE_SMBUS_BIG 3 | ||
| 248 | |||
| 249 | #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) | ||
| 250 | #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) | ||
| 251 | #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) | ||
| 252 | #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | ||
| 253 | #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) | ||
| 254 | #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) | ||
| 255 | #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) | ||
| 256 | |||
| 257 | #define S_SYS_CONFIG 26 | ||
| 258 | #define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG) | ||
| 259 | #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG) | ||
| 260 | #define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG) | ||
| 261 | |||
| 262 | /* The following bits are writeable by JTAG only. */ | ||
| 263 | |||
| 264 | #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) | ||
| 265 | #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) | ||
| 266 | |||
| 267 | #define S_SYS_CLKCOUNT 34 | ||
| 268 | #define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT) | ||
| 269 | #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT) | ||
| 270 | #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT) | ||
| 271 | |||
| 272 | #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) | ||
| 273 | |||
| 274 | #define S_SYS_PLL_IREF 43 | ||
| 275 | #define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF) | ||
| 276 | |||
| 277 | #define S_SYS_PLL_VCO 45 | ||
| 278 | #define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO) | ||
| 279 | |||
| 280 | #define S_SYS_PLL_VREG 47 | ||
| 281 | #define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG) | ||
| 282 | |||
| 283 | #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) | ||
| 284 | #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) | ||
| 285 | #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) | ||
| 286 | #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) | ||
| 287 | #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) | ||
| 288 | |||
| 289 | /* End of bits writable by JTAG only. */ | ||
| 290 | |||
| 291 | #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) | ||
| 292 | #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) | ||
| 293 | |||
| 294 | #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) | ||
| 295 | #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) | ||
| 296 | |||
| 297 | #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) | ||
| 298 | #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) | ||
| 299 | #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) | ||
| 300 | |||
| 301 | #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) | ||
| 302 | #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) | ||
| 303 | |||
| 304 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | ||
| 305 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) | ||
| 306 | #endif /* 1250 PASS2 || 112x PASS1 */ | ||
| 307 | |||
| 308 | #endif | ||
| 309 | |||
| 310 | |||
| 311 | /* | ||
| 312 | * Mailbox Registers (Table 4-3) | ||
| 313 | * Registers: SCD_MBOX_CPU_x | ||
| 314 | */ | ||
| 315 | |||
| 316 | #define S_MBOX_INT_3 0 | ||
| 317 | #define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3) | ||
| 318 | #define S_MBOX_INT_2 16 | ||
| 319 | #define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2) | ||
| 320 | #define S_MBOX_INT_1 32 | ||
| 321 | #define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1) | ||
| 322 | #define S_MBOX_INT_0 48 | ||
| 323 | #define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0) | ||
| 324 | |||
| 325 | /* | ||
| 326 | * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) | ||
| 327 | * Registers: SCD_WDOG_INIT_CNT_x | ||
| 328 | */ | ||
| 329 | |||
| 330 | #define V_SCD_WDOG_FREQ 1000000 | ||
| 331 | |||
| 332 | #define S_SCD_WDOG_INIT 0 | ||
| 333 | #define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT) | ||
| 334 | |||
| 335 | #define S_SCD_WDOG_CNT 0 | ||
| 336 | #define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT) | ||
| 337 | |||
| 338 | #define S_SCD_WDOG_ENABLE 0 | ||
| 339 | #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) | ||
| 340 | |||
| 341 | #define S_SCD_WDOG_RESET_TYPE 2 | ||
| 342 | #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE) | ||
| 343 | #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE) | ||
| 344 | #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE) | ||
| 345 | |||
| 346 | #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | ||
| 347 | #define K_SCD_WDOG_RESET_SOFT 1 | ||
| 348 | #define K_SCD_WDOG_RESET_CPU0 3 | ||
| 349 | #define K_SCD_WDOG_RESET_CPU1 5 | ||
| 350 | #define K_SCD_WDOG_RESET_BOTH_CPUS 7 | ||
| 351 | |||
| 352 | /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ | ||
| 353 | #if SIBYTE_HDR_FEATURE(1250, PASS3) | ||
| 354 | #define S_SCD_WDOG_HAS_RESET 8 | ||
| 355 | #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) | ||
| 356 | #endif | ||
| 357 | |||
| 358 | |||
| 359 | /* | ||
| 360 | * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) | ||
| 361 | */ | ||
| 362 | |||
| 363 | #define V_SCD_TIMER_FREQ 1000000 | ||
| 364 | |||
| 365 | #define S_SCD_TIMER_INIT 0 | ||
| 366 | #define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT) | ||
| 367 | #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT) | ||
| 368 | #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT) | ||
| 369 | |||
| 370 | #define V_SCD_TIMER_WIDTH 23 | ||
| 371 | #define S_SCD_TIMER_CNT 0 | ||
| 372 | #define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT) | ||
| 373 | #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT) | ||
| 374 | #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT) | ||
| 375 | |||
| 376 | #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) | ||
| 377 | #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) | ||
| 378 | #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE | ||
| 379 | |||
| 380 | /* | ||
| 381 | * System Performance Counters | ||
| 382 | */ | ||
| 383 | |||
| 384 | #define S_SPC_CFG_SRC0 0 | ||
| 385 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0) | ||
| 386 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0) | ||
| 387 | #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0) | ||
| 388 | |||
| 389 | #define S_SPC_CFG_SRC1 8 | ||
| 390 | #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1) | ||
| 391 | #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1) | ||
| 392 | #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1) | ||
| 393 | |||
| 394 | #define S_SPC_CFG_SRC2 16 | ||
| 395 | #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2) | ||
| 396 | #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2) | ||
| 397 | #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2) | ||
| 398 | |||
| 399 | #define S_SPC_CFG_SRC3 24 | ||
| 400 | #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3) | ||
| 401 | #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3) | ||
| 402 | #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3) | ||
| 403 | |||
| 404 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 405 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) | ||
| 406 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) | ||
| 407 | #endif | ||
| 408 | |||
| 409 | |||
| 410 | /* | ||
| 411 | * Bus Watcher | ||
| 412 | */ | ||
| 413 | |||
| 414 | #define S_SCD_BERR_TID 8 | ||
| 415 | #define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID) | ||
| 416 | #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID) | ||
| 417 | #define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID) | ||
| 418 | |||
| 419 | #define S_SCD_BERR_RID 18 | ||
| 420 | #define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID) | ||
| 421 | #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID) | ||
| 422 | #define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID) | ||
| 423 | |||
| 424 | #define S_SCD_BERR_DCODE 22 | ||
| 425 | #define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE) | ||
| 426 | #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE) | ||
| 427 | #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE) | ||
| 428 | |||
| 429 | #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) | ||
| 430 | |||
| 431 | |||
| 432 | #define S_SCD_L2ECC_CORR_D 0 | ||
| 433 | #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D) | ||
| 434 | #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D) | ||
| 435 | #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D) | ||
| 436 | |||
| 437 | #define S_SCD_L2ECC_BAD_D 8 | ||
| 438 | #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D) | ||
| 439 | #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D) | ||
| 440 | #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D) | ||
| 441 | |||
| 442 | #define S_SCD_L2ECC_CORR_T 16 | ||
| 443 | #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T) | ||
| 444 | #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T) | ||
| 445 | #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T) | ||
| 446 | |||
| 447 | #define S_SCD_L2ECC_BAD_T 24 | ||
| 448 | #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T) | ||
| 449 | #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T) | ||
| 450 | #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T) | ||
| 451 | |||
| 452 | #define S_SCD_MEM_ECC_CORR 0 | ||
| 453 | #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR) | ||
| 454 | #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR) | ||
| 455 | #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR) | ||
| 456 | |||
| 457 | #define S_SCD_MEM_ECC_BAD 8 | ||
| 458 | #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD) | ||
| 459 | #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD) | ||
| 460 | #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD) | ||
| 461 | |||
| 462 | #define S_SCD_MEM_BUSERR 16 | ||
| 463 | #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR) | ||
| 464 | #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR) | ||
| 465 | #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR) | ||
| 466 | |||
| 467 | |||
| 468 | /* | ||
| 469 | * Address Trap Registers | ||
| 470 | */ | ||
| 471 | |||
| 472 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 473 | #define M_ATRAP_INDEX _SB_MAKEMASK(4, 0) | ||
| 474 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) | ||
| 475 | |||
| 476 | #define S_ATRAP_CFG_CNT 0 | ||
| 477 | #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT) | ||
| 478 | #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT) | ||
| 479 | #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT) | ||
| 480 | |||
| 481 | #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | ||
| 482 | #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | ||
| 483 | #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) | ||
| 484 | #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | ||
| 485 | #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | ||
| 486 | |||
| 487 | #define S_ATRAP_CFG_AGENTID 8 | ||
| 488 | #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID) | ||
| 489 | #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID) | ||
| 490 | #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID) | ||
| 491 | |||
| 492 | #define K_BUS_AGENT_CPU0 0 | ||
| 493 | #define K_BUS_AGENT_CPU1 1 | ||
| 494 | #define K_BUS_AGENT_IOB0 2 | ||
| 495 | #define K_BUS_AGENT_IOB1 3 | ||
| 496 | #define K_BUS_AGENT_SCD 4 | ||
| 497 | #define K_BUS_AGENT_L2C 6 | ||
| 498 | #define K_BUS_AGENT_MC 7 | ||
| 499 | |||
| 500 | #define S_ATRAP_CFG_CATTR 12 | ||
| 501 | #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR) | ||
| 502 | #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR) | ||
| 503 | #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR) | ||
| 504 | |||
| 505 | #define K_ATRAP_CFG_CATTR_IGNORE 0 | ||
| 506 | #define K_ATRAP_CFG_CATTR_UNC 1 | ||
| 507 | #define K_ATRAP_CFG_CATTR_CACHEABLE 2 | ||
| 508 | #define K_ATRAP_CFG_CATTR_NONCOH 3 | ||
| 509 | #define K_ATRAP_CFG_CATTR_COHERENT 4 | ||
| 510 | #define K_ATRAP_CFG_CATTR_NOTUNC 5 | ||
| 511 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 | ||
| 512 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 | ||
| 513 | |||
| 514 | #endif /* 1250/112x */ | ||
| 515 | |||
| 516 | /* | ||
| 517 | * Trace Buffer Config register | ||
| 518 | */ | ||
| 519 | |||
| 520 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | ||
| 521 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | ||
| 522 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | ||
| 523 | #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) | ||
| 524 | #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) | ||
| 525 | #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) | ||
| 526 | #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) | ||
| 527 | #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) | ||
| 528 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 529 | #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) | ||
| 530 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 531 | |||
| 532 | /* | ||
| 533 | * This field is the same on the 1250/112x and 1480, just located in | ||
| 534 | * a slightly different place in the register. | ||
| 535 | */ | ||
| 536 | #if SIBYTE_HDR_FEATURE_1250_112x | ||
| 537 | #define S_SCD_TRACE_CFG_CUR_ADDR 10 | ||
| 538 | #else | ||
| 539 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 540 | #define S_SCD_TRACE_CFG_CUR_ADDR 24 | ||
| 541 | #endif /* 1480 */ | ||
| 542 | #endif /* 1250/112x */ | ||
| 543 | |||
| 544 | #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR) | ||
| 545 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR) | ||
| 546 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR) | ||
| 547 | |||
| 548 | /* | ||
| 549 | * Trace Event registers | ||
| 550 | */ | ||
| 551 | |||
| 552 | #define S_SCD_TREVT_ADDR_MATCH 0 | ||
| 553 | #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH) | ||
| 554 | #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH) | ||
| 555 | #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH) | ||
| 556 | |||
| 557 | #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) | ||
| 558 | #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) | ||
| 559 | #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) | ||
| 560 | #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) | ||
| 561 | #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) | ||
| 562 | #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) | ||
| 563 | #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) | ||
| 564 | |||
| 565 | #define S_SCD_TREVT_REQID 12 | ||
| 566 | #define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID) | ||
| 567 | #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID) | ||
| 568 | #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID) | ||
| 569 | |||
| 570 | #define S_SCD_TREVT_RESPID 16 | ||
| 571 | #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID) | ||
| 572 | #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID) | ||
| 573 | #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID) | ||
| 574 | |||
| 575 | #define S_SCD_TREVT_DATAID 20 | ||
| 576 | #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID) | ||
| 577 | #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID) | ||
| 578 | #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID) | ||
| 579 | |||
| 580 | #define S_SCD_TREVT_COUNT 24 | ||
| 581 | #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT) | ||
| 582 | #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT) | ||
| 583 | #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT) | ||
| 584 | |||
| 585 | /* | ||
| 586 | * Trace Sequence registers | ||
| 587 | */ | ||
| 588 | |||
| 589 | #define S_SCD_TRSEQ_EVENT4 0 | ||
| 590 | #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4) | ||
| 591 | #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4) | ||
| 592 | #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4) | ||
| 593 | |||
| 594 | #define S_SCD_TRSEQ_EVENT3 4 | ||
| 595 | #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3) | ||
| 596 | #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3) | ||
| 597 | #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3) | ||
| 598 | |||
| 599 | #define S_SCD_TRSEQ_EVENT2 8 | ||
| 600 | #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2) | ||
| 601 | #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2) | ||
| 602 | #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2) | ||
| 603 | |||
| 604 | #define S_SCD_TRSEQ_EVENT1 12 | ||
| 605 | #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1) | ||
| 606 | #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1) | ||
| 607 | #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1) | ||
| 608 | |||
| 609 | #define K_SCD_TRSEQ_E0 0 | ||
| 610 | #define K_SCD_TRSEQ_E1 1 | ||
| 611 | #define K_SCD_TRSEQ_E2 2 | ||
| 612 | #define K_SCD_TRSEQ_E3 3 | ||
| 613 | #define K_SCD_TRSEQ_E0_E1 4 | ||
| 614 | #define K_SCD_TRSEQ_E1_E2 5 | ||
| 615 | #define K_SCD_TRSEQ_E2_E3 6 | ||
| 616 | #define K_SCD_TRSEQ_E0_E1_E2 7 | ||
| 617 | #define K_SCD_TRSEQ_E0_E1_E2_E3 8 | ||
| 618 | #define K_SCD_TRSEQ_E0E1 9 | ||
| 619 | #define K_SCD_TRSEQ_E0E1E2 10 | ||
| 620 | #define K_SCD_TRSEQ_E0E1E2E3 11 | ||
| 621 | #define K_SCD_TRSEQ_E0E1_E2 12 | ||
| 622 | #define K_SCD_TRSEQ_E0E1_E2E3 13 | ||
| 623 | #define K_SCD_TRSEQ_E0E1_E2_E3 14 | ||
| 624 | #define K_SCD_TRSEQ_IGNORED 15 | ||
| 625 | |||
| 626 | #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ | ||
| 627 | V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ | ||
| 628 | V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ | ||
| 629 | V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) | ||
| 630 | |||
| 631 | #define S_SCD_TRSEQ_FUNCTION 16 | ||
| 632 | #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION) | ||
| 633 | #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION) | ||
| 634 | #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION) | ||
| 635 | |||
| 636 | #define K_SCD_TRSEQ_FUNC_NOP 0 | ||
| 637 | #define K_SCD_TRSEQ_FUNC_START 1 | ||
| 638 | #define K_SCD_TRSEQ_FUNC_STOP 2 | ||
| 639 | #define K_SCD_TRSEQ_FUNC_FREEZE 3 | ||
| 640 | |||
| 641 | #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) | ||
| 642 | #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) | ||
| 643 | #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) | ||
| 644 | #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) | ||
| 645 | |||
| 646 | #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) | ||
| 647 | #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) | ||
| 648 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) | ||
| 649 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) | ||
| 650 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) | ||
| 651 | #define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23) | ||
| 652 | #define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24) | ||
| 653 | |||
| 654 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h new file mode 100644 index 000000000000..04769923cf1e --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * SMBUS Constants File: sb1250_smbus.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the SB1250's SMbus devices. | ||
| 8 | * | ||
| 9 | * SB1250 specification level: 10/21/02 | ||
| 10 | * BCM1280 specification level: 11/24/03 | ||
| 11 | * | ||
| 12 | ********************************************************************* | ||
| 13 | * | ||
| 14 | * Copyright 2000,2001,2002,2003 | ||
| 15 | * Broadcom Corporation. All rights reserved. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or | ||
| 18 | * modify it under the terms of the GNU General Public License as | ||
| 19 | * published by the Free Software Foundation; either version 2 of | ||
| 20 | * the License, or (at your option) any later version. | ||
| 21 | * | ||
| 22 | * This program is distributed in the hope that it will be useful, | ||
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 25 | * GNU General Public License for more details. | ||
| 26 | * | ||
| 27 | * You should have received a copy of the GNU General Public License | ||
| 28 | * along with this program; if not, write to the Free Software | ||
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 30 | * MA 02111-1307 USA | ||
| 31 | ********************************************************************* */ | ||
| 32 | |||
| 33 | |||
| 34 | #ifndef _SB1250_SMBUS_H | ||
| 35 | #define _SB1250_SMBUS_H | ||
| 36 | |||
| 37 | #include "sb1250_defs.h" | ||
| 38 | |||
| 39 | /* | ||
| 40 | * SMBus Clock Frequency Register (Table 14-2) | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define S_SMB_FREQ_DIV 0 | ||
| 44 | #define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV) | ||
| 45 | #define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV) | ||
| 46 | |||
| 47 | #define K_SMB_FREQ_400KHZ 0x1F | ||
| 48 | #define K_SMB_FREQ_100KHZ 0x7D | ||
| 49 | #define K_SMB_FREQ_10KHZ 1250 | ||
| 50 | |||
| 51 | #define S_SMB_CMD 0 | ||
| 52 | #define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD) | ||
| 53 | #define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD) | ||
| 54 | |||
| 55 | /* | ||
| 56 | * SMBus control register (Table 14-4) | ||
| 57 | */ | ||
| 58 | |||
| 59 | #define M_SMB_ERR_INTR _SB_MAKEMASK1(0) | ||
| 60 | #define M_SMB_FINISH_INTR _SB_MAKEMASK1(1) | ||
| 61 | |||
| 62 | #define S_SMB_DATA_OUT 4 | ||
| 63 | #define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT) | ||
| 64 | #define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT) | ||
| 65 | |||
| 66 | #define M_SMB_DATA_DIR _SB_MAKEMASK1(5) | ||
| 67 | #define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR | ||
| 68 | #define M_SMB_CLK_OUT _SB_MAKEMASK1(6) | ||
| 69 | #define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * SMBus status registers (Table 14-5) | ||
| 73 | */ | ||
| 74 | |||
| 75 | #define M_SMB_BUSY _SB_MAKEMASK1(0) | ||
| 76 | #define M_SMB_ERROR _SB_MAKEMASK1(1) | ||
| 77 | #define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2) | ||
| 78 | |||
| 79 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 80 | #define S_SMB_SCL_IN 5 | ||
| 81 | #define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN) | ||
| 82 | #define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN) | ||
| 83 | #define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN) | ||
| 84 | #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ | ||
| 85 | |||
| 86 | #define S_SMB_REF 6 | ||
| 87 | #define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF) | ||
| 88 | #define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF) | ||
| 89 | #define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF) | ||
| 90 | |||
| 91 | #define S_SMB_DATA_IN 7 | ||
| 92 | #define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN) | ||
| 93 | #define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN) | ||
| 94 | #define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN) | ||
| 95 | |||
| 96 | /* | ||
| 97 | * SMBus Start/Command registers (Table 14-9) | ||
| 98 | */ | ||
| 99 | |||
| 100 | #define S_SMB_ADDR 0 | ||
| 101 | #define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR) | ||
| 102 | #define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR) | ||
| 103 | #define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR) | ||
| 104 | |||
| 105 | #define M_SMB_QDATA _SB_MAKEMASK1(7) | ||
| 106 | |||
| 107 | #define S_SMB_TT 8 | ||
| 108 | #define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT) | ||
| 109 | #define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT) | ||
| 110 | #define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT) | ||
| 111 | |||
| 112 | #define K_SMB_TT_WR1BYTE 0 | ||
| 113 | #define K_SMB_TT_WR2BYTE 1 | ||
| 114 | #define K_SMB_TT_WR3BYTE 2 | ||
| 115 | #define K_SMB_TT_CMD_RD1BYTE 3 | ||
| 116 | #define K_SMB_TT_CMD_RD2BYTE 4 | ||
| 117 | #define K_SMB_TT_RD1BYTE 5 | ||
| 118 | #define K_SMB_TT_QUICKCMD 6 | ||
| 119 | #define K_SMB_TT_EEPROMREAD 7 | ||
| 120 | |||
| 121 | #define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE) | ||
| 122 | #define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE) | ||
| 123 | #define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE) | ||
| 124 | #define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE) | ||
| 125 | #define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE) | ||
| 126 | #define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE) | ||
| 127 | #define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD) | ||
| 128 | #define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD) | ||
| 129 | |||
| 130 | #define M_SMB_PEC _SB_MAKEMASK1(15) | ||
| 131 | |||
| 132 | /* | ||
| 133 | * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7) | ||
| 134 | */ | ||
| 135 | |||
| 136 | #define S_SMB_LB 0 | ||
| 137 | #define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB) | ||
| 138 | #define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB) | ||
| 139 | |||
| 140 | #define S_SMB_MB 8 | ||
| 141 | #define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB) | ||
| 142 | #define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB) | ||
| 143 | |||
| 144 | |||
| 145 | /* | ||
| 146 | * SMBus Packet Error Check register (Table 14-8) | ||
| 147 | */ | ||
| 148 | |||
| 149 | #define S_SPEC_PEC 0 | ||
| 150 | #define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC) | ||
| 151 | #define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC) | ||
| 152 | |||
| 153 | |||
| 154 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 155 | |||
| 156 | #define S_SMB_CMDH 8 | ||
| 157 | #define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH) | ||
| 158 | #define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH) | ||
| 159 | |||
| 160 | #define M_SMB_EXTEND _SB_MAKEMASK1(14) | ||
| 161 | |||
| 162 | #define S_SMB_DFMT 8 | ||
| 163 | #define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT) | ||
| 164 | #define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT) | ||
| 165 | #define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT) | ||
| 166 | |||
| 167 | #define K_SMB_DFMT_1BYTE 0 | ||
| 168 | #define K_SMB_DFMT_2BYTE 1 | ||
| 169 | #define K_SMB_DFMT_3BYTE 2 | ||
| 170 | #define K_SMB_DFMT_4BYTE 3 | ||
| 171 | #define K_SMB_DFMT_NODATA 4 | ||
| 172 | #define K_SMB_DFMT_CMD4BYTE 5 | ||
| 173 | #define K_SMB_DFMT_CMD5BYTE 6 | ||
| 174 | #define K_SMB_DFMT_RESERVED 7 | ||
| 175 | |||
| 176 | #define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE) | ||
| 177 | #define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE) | ||
| 178 | #define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE) | ||
| 179 | #define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE) | ||
| 180 | #define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA) | ||
| 181 | #define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE) | ||
| 182 | #define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE) | ||
| 183 | #define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED) | ||
| 184 | |||
| 185 | #define S_SMB_AFMT 11 | ||
| 186 | #define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT) | ||
| 187 | #define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT) | ||
| 188 | #define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT) | ||
| 189 | |||
| 190 | #define K_SMB_AFMT_NONE 0 | ||
| 191 | #define K_SMB_AFMT_ADDR 1 | ||
| 192 | #define K_SMB_AFMT_ADDR_CMD1BYTE 2 | ||
| 193 | #define K_SMB_AFMT_ADDR_CMD2BYTE 3 | ||
| 194 | |||
| 195 | #define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE) | ||
| 196 | #define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR) | ||
| 197 | #define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE) | ||
| 198 | #define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE) | ||
| 199 | |||
| 200 | #define M_SMB_DIR _SB_MAKEMASK1(13) | ||
| 201 | |||
| 202 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 203 | |||
| 204 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h new file mode 100644 index 000000000000..d4b8558e0bf1 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * Synchronous Serial Constants File: sb1250_syncser.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the SB1250's Synchronous Serial | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_SYNCSER_H | ||
| 34 | #define _SB1250_SYNCSER_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* | ||
| 39 | * Serial Mode Configuration Register | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0) | ||
| 43 | #define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1) | ||
| 44 | |||
| 45 | #define S_SYNCSER_FLAG_NUM 2 | ||
| 46 | #define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM) | ||
| 47 | #define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM) | ||
| 48 | |||
| 49 | #define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6) | ||
| 50 | #define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7) | ||
| 51 | #define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8) | ||
| 52 | #define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9) | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Serial Clock Source and Line Interface Mode Register | ||
| 56 | */ | ||
| 57 | |||
| 58 | #define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0) | ||
| 59 | #define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1) | ||
| 60 | |||
| 61 | #define S_SYNCSER_RXSYNC_DLY 2 | ||
| 62 | #define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY) | ||
| 63 | #define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY) | ||
| 64 | |||
| 65 | #define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4) | ||
| 66 | #define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5) | ||
| 67 | |||
| 68 | #define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6) | ||
| 69 | #define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7) | ||
| 70 | |||
| 71 | #define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8) | ||
| 72 | #define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9) | ||
| 73 | |||
| 74 | #define S_SYNCSER_TXSYNC_DLY 10 | ||
| 75 | #define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY) | ||
| 76 | #define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY) | ||
| 77 | |||
| 78 | #define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12) | ||
| 79 | #define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13) | ||
| 80 | |||
| 81 | #define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14) | ||
| 82 | #define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15) | ||
| 83 | |||
| 84 | /* | ||
| 85 | * Serial Command Register | ||
| 86 | */ | ||
| 87 | |||
| 88 | #define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0) | ||
| 89 | #define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1) | ||
| 90 | #define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2) | ||
| 91 | #define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3) | ||
| 92 | #define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5) | ||
| 93 | |||
| 94 | /* | ||
| 95 | * Serial DMA Enable Register | ||
| 96 | */ | ||
| 97 | |||
| 98 | #define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0) | ||
| 99 | #define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4) | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Serial Status Register | ||
| 103 | */ | ||
| 104 | |||
| 105 | #define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0) | ||
| 106 | #define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1) | ||
| 107 | #define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2) | ||
| 108 | #define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3) | ||
| 109 | #define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4) | ||
| 110 | #define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5) | ||
| 111 | #define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6) | ||
| 112 | #define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8) | ||
| 113 | #define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9) | ||
| 114 | #define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10) | ||
| 115 | #define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11) | ||
| 116 | #define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16) | ||
| 117 | #define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17) | ||
| 118 | #define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18) | ||
| 119 | #define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19) | ||
| 120 | #define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20) | ||
| 121 | #define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21) | ||
| 122 | #define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22) | ||
| 123 | #define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24) | ||
| 124 | #define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25) | ||
| 125 | #define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26) | ||
| 126 | #define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27) | ||
| 127 | #define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28) | ||
| 128 | #define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29) | ||
| 129 | #define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30) | ||
| 130 | #define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31) | ||
| 131 | |||
| 132 | /* | ||
| 133 | * Sequencer Table Entry format | ||
| 134 | */ | ||
| 135 | |||
| 136 | #define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0) | ||
| 137 | #define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1) | ||
| 138 | |||
| 139 | #define S_SYNCSER_SEQ_COUNT 2 | ||
| 140 | #define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT) | ||
| 141 | #define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT) | ||
| 142 | |||
| 143 | #define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6) | ||
| 144 | #define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7) | ||
| 145 | |||
| 146 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h new file mode 100644 index 000000000000..d835bf280140 --- /dev/null +++ b/arch/mips/include/asm/sibyte/sb1250_uart.h | |||
| @@ -0,0 +1,362 @@ | |||
| 1 | /* ********************************************************************* | ||
| 2 | * SB1250 Board Support Package | ||
| 3 | * | ||
| 4 | * UART Constants File: sb1250_uart.h | ||
| 5 | * | ||
| 6 | * This module contains constants and macros useful for | ||
| 7 | * manipulating the SB1250's UARTs | ||
| 8 | * | ||
| 9 | * SB1250 specification level: User's manual 1/02/02 | ||
| 10 | * | ||
| 11 | ********************************************************************* | ||
| 12 | * | ||
| 13 | * Copyright 2000,2001,2002,2003 | ||
| 14 | * Broadcom Corporation. All rights reserved. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or | ||
| 17 | * modify it under the terms of the GNU General Public License as | ||
| 18 | * published by the Free Software Foundation; either version 2 of | ||
| 19 | * the License, or (at your option) any later version. | ||
| 20 | * | ||
| 21 | * This program is distributed in the hope that it will be useful, | ||
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 24 | * GNU General Public License for more details. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License | ||
| 27 | * along with this program; if not, write to the Free Software | ||
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
| 29 | * MA 02111-1307 USA | ||
| 30 | ********************************************************************* */ | ||
| 31 | |||
| 32 | |||
| 33 | #ifndef _SB1250_UART_H | ||
| 34 | #define _SB1250_UART_H | ||
| 35 | |||
| 36 | #include "sb1250_defs.h" | ||
| 37 | |||
| 38 | /* ********************************************************************** | ||
| 39 | * DUART Registers | ||
| 40 | ********************************************************************** */ | ||
| 41 | |||
| 42 | /* | ||
| 43 | * DUART Mode Register #1 (Table 10-3) | ||
| 44 | * Register: DUART_MODE_REG_1_A | ||
| 45 | * Register: DUART_MODE_REG_1_B | ||
| 46 | */ | ||
| 47 | |||
| 48 | #define S_DUART_BITS_PER_CHAR 0 | ||
| 49 | #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR) | ||
| 50 | #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR) | ||
| 51 | |||
| 52 | #define K_DUART_BITS_PER_CHAR_RSV0 0 | ||
| 53 | #define K_DUART_BITS_PER_CHAR_RSV1 1 | ||
| 54 | #define K_DUART_BITS_PER_CHAR_7 2 | ||
| 55 | #define K_DUART_BITS_PER_CHAR_8 3 | ||
| 56 | |||
| 57 | #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) | ||
| 58 | #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) | ||
| 59 | #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) | ||
| 60 | #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) | ||
| 61 | |||
| 62 | |||
| 63 | #define M_DUART_PARITY_TYPE_EVEN 0x00 | ||
| 64 | #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) | ||
| 65 | |||
| 66 | #define S_DUART_PARITY_MODE 3 | ||
| 67 | #define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE) | ||
| 68 | #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE) | ||
| 69 | |||
| 70 | #define K_DUART_PARITY_MODE_ADD 0 | ||
| 71 | #define K_DUART_PARITY_MODE_ADD_FIXED 1 | ||
| 72 | #define K_DUART_PARITY_MODE_NONE 2 | ||
| 73 | |||
| 74 | #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) | ||
| 75 | #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) | ||
| 76 | #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) | ||
| 77 | |||
| 78 | #define M_DUART_TX_IRQ_SEL_TXRDY 0 | ||
| 79 | #define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5) | ||
| 80 | |||
| 81 | #define M_DUART_RX_IRQ_SEL_RXRDY 0 | ||
| 82 | #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) | ||
| 83 | |||
| 84 | #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) | ||
| 85 | |||
| 86 | /* | ||
| 87 | * DUART Mode Register #2 (Table 10-4) | ||
| 88 | * Register: DUART_MODE_REG_2_A | ||
| 89 | * Register: DUART_MODE_REG_2_B | ||
| 90 | */ | ||
| 91 | |||
| 92 | #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */ | ||
| 93 | |||
| 94 | #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) | ||
| 95 | #define M_DUART_STOP_BIT_LEN_1 0 | ||
| 96 | |||
| 97 | #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) | ||
| 98 | |||
| 99 | |||
| 100 | #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ | ||
| 101 | |||
| 102 | #define S_DUART_CHAN_MODE 6 | ||
| 103 | #define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE) | ||
| 104 | #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE) | ||
| 105 | |||
| 106 | #define K_DUART_CHAN_MODE_NORMAL 0 | ||
| 107 | #define K_DUART_CHAN_MODE_LCL_LOOP 2 | ||
| 108 | #define K_DUART_CHAN_MODE_REM_LOOP 3 | ||
| 109 | |||
| 110 | #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) | ||
| 111 | #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) | ||
| 112 | #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) | ||
| 113 | |||
| 114 | /* | ||
| 115 | * DUART Command Register (Table 10-5) | ||
| 116 | * Register: DUART_CMD_A | ||
| 117 | * Register: DUART_CMD_B | ||
| 118 | */ | ||
| 119 | |||
| 120 | #define M_DUART_RX_EN _SB_MAKEMASK1(0) | ||
| 121 | #define M_DUART_RX_DIS _SB_MAKEMASK1(1) | ||
| 122 | #define M_DUART_TX_EN _SB_MAKEMASK1(2) | ||
| 123 | #define M_DUART_TX_DIS _SB_MAKEMASK1(3) | ||
| 124 | |||
| 125 | #define S_DUART_MISC_CMD 4 | ||
| 126 | #define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD) | ||
| 127 | #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD) | ||
| 128 | |||
| 129 | #define K_DUART_MISC_CMD_NOACTION0 0 | ||
| 130 | #define K_DUART_MISC_CMD_NOACTION1 1 | ||
| 131 | #define K_DUART_MISC_CMD_RESET_RX 2 | ||
| 132 | #define K_DUART_MISC_CMD_RESET_TX 3 | ||
| 133 | #define K_DUART_MISC_CMD_NOACTION4 4 | ||
| 134 | #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 | ||
| 135 | #define K_DUART_MISC_CMD_START_BREAK 6 | ||
| 136 | #define K_DUART_MISC_CMD_STOP_BREAK 7 | ||
| 137 | |||
| 138 | #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) | ||
| 139 | #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) | ||
| 140 | #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) | ||
| 141 | #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) | ||
| 142 | #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) | ||
| 143 | #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) | ||
| 144 | #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) | ||
| 145 | #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) | ||
| 146 | |||
| 147 | #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) | ||
| 148 | |||
| 149 | /* | ||
| 150 | * DUART Status Register (Table 10-6) | ||
| 151 | * Register: DUART_STATUS_A | ||
| 152 | * Register: DUART_STATUS_B | ||
| 153 | * READ-ONLY | ||
| 154 | */ | ||
| 155 | |||
| 156 | #define M_DUART_RX_RDY _SB_MAKEMASK1(0) | ||
| 157 | #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) | ||
| 158 | #define M_DUART_TX_RDY _SB_MAKEMASK1(2) | ||
| 159 | #define M_DUART_TX_EMT _SB_MAKEMASK1(3) | ||
| 160 | #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) | ||
| 161 | #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) | ||
| 162 | #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) | ||
| 163 | #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) | ||
| 164 | |||
| 165 | /* | ||
| 166 | * DUART Baud Rate Register (Table 10-7) | ||
| 167 | * Register: DUART_CLK_SEL_A | ||
| 168 | * Register: DUART_CLK_SEL_B | ||
| 169 | */ | ||
| 170 | |||
| 171 | #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0) | ||
| 172 | #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) | ||
| 173 | |||
| 174 | /* | ||
| 175 | * DUART Data Registers (Table 10-8 and 10-9) | ||
| 176 | * Register: DUART_RX_HOLD_A | ||
| 177 | * Register: DUART_RX_HOLD_B | ||
| 178 | * Register: DUART_TX_HOLD_A | ||
| 179 | * Register: DUART_TX_HOLD_B | ||
| 180 | */ | ||
| 181 | |||
| 182 | #define M_DUART_RX_DATA _SB_MAKEMASK(8, 0) | ||
| 183 | #define M_DUART_TX_DATA _SB_MAKEMASK(8, 0) | ||
| 184 | |||
| 185 | /* | ||
| 186 | * DUART Input Port Register (Table 10-10) | ||
| 187 | * Register: DUART_IN_PORT | ||
| 188 | */ | ||
| 189 | |||
| 190 | #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) | ||
| 191 | #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) | ||
| 192 | #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) | ||
| 193 | #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) | ||
| 194 | #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) | ||
| 195 | #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) | ||
| 196 | #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) | ||
| 197 | #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) | ||
| 198 | |||
| 199 | /* | ||
| 200 | * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) | ||
| 201 | * Register: DUART_INPORT_CHNG | ||
| 202 | */ | ||
| 203 | |||
| 204 | #define S_DUART_IN_PIN_VAL 0 | ||
| 205 | #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL) | ||
| 206 | |||
| 207 | #define S_DUART_IN_PIN_CHNG 4 | ||
| 208 | #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG) | ||
| 209 | |||
| 210 | |||
| 211 | /* | ||
| 212 | * DUART Output port control register (Table 10-14) | ||
| 213 | * Register: DUART_OPCR | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ | ||
| 217 | #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) | ||
| 218 | #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ | ||
| 219 | #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) | ||
| 220 | #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */ | ||
| 221 | |||
| 222 | /* | ||
| 223 | * DUART Aux Control Register (Table 10-15) | ||
| 224 | * Register: DUART_AUX_CTRL | ||
| 225 | */ | ||
| 226 | |||
| 227 | #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) | ||
| 228 | #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) | ||
| 229 | #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) | ||
| 230 | #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) | ||
| 231 | #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 232 | |||
| 233 | #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) | ||
| 234 | #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) | ||
| 235 | |||
| 236 | /* | ||
| 237 | * DUART Interrupt Status Register (Table 10-16) | ||
| 238 | * Register: DUART_ISR | ||
| 239 | */ | ||
| 240 | |||
| 241 | #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) | ||
| 242 | |||
| 243 | #define S_DUART_ISR_RX_A 1 | ||
| 244 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A) | ||
| 245 | #define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A) | ||
| 246 | #define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A) | ||
| 247 | |||
| 248 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) | ||
| 249 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) | ||
| 250 | #define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0) | ||
| 251 | |||
| 252 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) | ||
| 253 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) | ||
| 254 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) | ||
| 255 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) | ||
| 256 | #define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4) | ||
| 257 | |||
| 258 | /* | ||
| 259 | * DUART Channel A Interrupt Status Register (Table 10-17) | ||
| 260 | * DUART Channel B Interrupt Status Register (Table 10-18) | ||
| 261 | * Register: DUART_ISR_A | ||
| 262 | * Register: DUART_ISR_B | ||
| 263 | */ | ||
| 264 | |||
| 265 | #define M_DUART_ISR_TX _SB_MAKEMASK1(0) | ||
| 266 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) | ||
| 267 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) | ||
| 268 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) | ||
| 269 | #define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0) | ||
| 270 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 271 | |||
| 272 | /* | ||
| 273 | * DUART Interrupt Mask Register (Table 10-19) | ||
| 274 | * Register: DUART_IMR | ||
| 275 | */ | ||
| 276 | |||
| 277 | #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) | ||
| 278 | #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) | ||
| 279 | #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) | ||
| 280 | #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) | ||
| 281 | #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0) | ||
| 282 | |||
| 283 | #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) | ||
| 284 | #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) | ||
| 285 | #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) | ||
| 286 | #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) | ||
| 287 | #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4) | ||
| 288 | |||
| 289 | /* | ||
| 290 | * DUART Channel A Interrupt Mask Register (Table 10-20) | ||
| 291 | * DUART Channel B Interrupt Mask Register (Table 10-21) | ||
| 292 | * Register: DUART_IMR_A | ||
| 293 | * Register: DUART_IMR_B | ||
| 294 | */ | ||
| 295 | |||
| 296 | #define M_DUART_IMR_TX _SB_MAKEMASK1(0) | ||
| 297 | #define M_DUART_IMR_RX _SB_MAKEMASK1(1) | ||
| 298 | #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) | ||
| 299 | #define M_DUART_IMR_IN _SB_MAKEMASK1(3) | ||
| 300 | #define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0) | ||
| 301 | #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 302 | |||
| 303 | |||
| 304 | /* | ||
| 305 | * DUART Output Port Set Register (Table 10-22) | ||
| 306 | * Register: DUART_SET_OPR | ||
| 307 | */ | ||
| 308 | |||
| 309 | #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) | ||
| 310 | #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) | ||
| 311 | #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) | ||
| 312 | #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) | ||
| 313 | #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 314 | |||
| 315 | /* | ||
| 316 | * DUART Output Port Clear Register (Table 10-23) | ||
| 317 | * Register: DUART_CLEAR_OPR | ||
| 318 | */ | ||
| 319 | |||
| 320 | #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) | ||
| 321 | #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) | ||
| 322 | #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) | ||
| 323 | #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) | ||
| 324 | #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 325 | |||
| 326 | /* | ||
| 327 | * DUART Output Port RTS Register (Table 10-24) | ||
| 328 | * Register: DUART_OUT_PORT | ||
| 329 | */ | ||
| 330 | |||
| 331 | #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) | ||
| 332 | #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) | ||
| 333 | #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) | ||
| 334 | #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) | ||
| 335 | #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4) | ||
| 336 | |||
| 337 | #define M_DUART_OUT_PIN_SET(chan) \ | ||
| 338 | (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) | ||
| 339 | #define M_DUART_OUT_PIN_CLR(chan) \ | ||
| 340 | (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) | ||
| 341 | |||
| 342 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) | ||
| 343 | /* | ||
| 344 | * Full Interrupt Control Register | ||
| 345 | */ | ||
| 346 | |||
| 347 | #define S_DUART_SIG_FULL _SB_MAKE64(0) | ||
| 348 | #define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL) | ||
| 349 | #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL) | ||
| 350 | #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL) | ||
| 351 | |||
| 352 | #define S_DUART_INT_TIME _SB_MAKE64(4) | ||
| 353 | #define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME) | ||
| 354 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME) | ||
| 355 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME) | ||
| 356 | #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ | ||
| 357 | |||
| 358 | |||
| 359 | /* ********************************************************************** */ | ||
| 360 | |||
| 361 | |||
| 362 | #endif | ||
diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h new file mode 100644 index 000000000000..64c47874f32d --- /dev/null +++ b/arch/mips/include/asm/sibyte/sentosa.h | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000, 2001 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | #ifndef __ASM_SIBYTE_SENTOSA_H | ||
| 19 | #define __ASM_SIBYTE_SENTOSA_H | ||
| 20 | |||
| 21 | #include <asm/sibyte/sb1250.h> | ||
| 22 | #include <asm/sibyte/sb1250_int.h> | ||
| 23 | |||
| 24 | #ifdef CONFIG_SIBYTE_SENTOSA | ||
| 25 | #define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)" | ||
| 26 | #endif | ||
| 27 | #ifdef CONFIG_SIBYTE_RHONE | ||
| 28 | #define SIBYTE_BOARD_NAME "BCM91125E (Rhone)" | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* Generic bus chip selects */ | ||
| 32 | #ifdef CONFIG_SIBYTE_RHONE | ||
| 33 | #define LEDS_CS 6 | ||
| 34 | #define LEDS_PHYS 0x1d0a0000 | ||
| 35 | #endif | ||
| 36 | |||
| 37 | /* GPIOs */ | ||
| 38 | #define K_GPIO_DBG_LED 0 | ||
| 39 | |||
| 40 | #endif /* __ASM_SIBYTE_SENTOSA_H */ | ||
diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h new file mode 100644 index 000000000000..114d9d29ca9d --- /dev/null +++ b/arch/mips/include/asm/sibyte/swarm.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | */ | ||
| 18 | #ifndef __ASM_SIBYTE_SWARM_H | ||
| 19 | #define __ASM_SIBYTE_SWARM_H | ||
| 20 | |||
| 21 | #include <asm/sibyte/sb1250.h> | ||
| 22 | #include <asm/sibyte/sb1250_int.h> | ||
| 23 | |||
| 24 | #ifdef CONFIG_SIBYTE_SWARM | ||
| 25 | #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" | ||
| 26 | #define SIBYTE_HAVE_PCMCIA 1 | ||
| 27 | #define SIBYTE_HAVE_IDE 1 | ||
| 28 | #endif | ||
| 29 | #ifdef CONFIG_SIBYTE_LITTLESUR | ||
| 30 | #define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)" | ||
| 31 | #define SIBYTE_HAVE_PCMCIA 0 | ||
| 32 | #define SIBYTE_HAVE_IDE 1 | ||
| 33 | #define SIBYTE_DEFAULT_CONSOLE "cfe0" | ||
| 34 | #endif | ||
| 35 | #ifdef CONFIG_SIBYTE_CRHONE | ||
| 36 | #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" | ||
| 37 | #define SIBYTE_HAVE_PCMCIA 0 | ||
| 38 | #define SIBYTE_HAVE_IDE 0 | ||
| 39 | #endif | ||
| 40 | #ifdef CONFIG_SIBYTE_CRHINE | ||
| 41 | #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" | ||
| 42 | #define SIBYTE_HAVE_PCMCIA 0 | ||
| 43 | #define SIBYTE_HAVE_IDE 0 | ||
| 44 | #endif | ||
| 45 | |||
| 46 | /* Generic bus chip selects */ | ||
| 47 | #define LEDS_CS 3 | ||
| 48 | #define LEDS_PHYS 0x100a0000 | ||
| 49 | |||
| 50 | #ifdef SIBYTE_HAVE_IDE | ||
| 51 | #define IDE_CS 4 | ||
| 52 | #define IDE_PHYS 0x100b0000 | ||
| 53 | #define K_GPIO_GB_IDE 4 | ||
| 54 | #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #ifdef SIBYTE_HAVE_PCMCIA | ||
| 58 | #define PCMCIA_CS 6 | ||
| 59 | #define PCMCIA_PHYS 0x11000000 | ||
| 60 | #define K_GPIO_PC_READY 9 | ||
| 61 | #define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) | ||
| 62 | #endif | ||
| 63 | |||
| 64 | #endif /* __ASM_SIBYTE_SWARM_H */ | ||