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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-14 17:39:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-14 17:39:05 -0400
commita5ef3f7dcba17e79c21afec38188c4c6a0baf995 (patch)
tree1961e2e8c2d30dd7a21b93fa7e70dc62f892651d /arch/mips/include/asm/ptrace.h
parentd25282d1c9b9bc4cda7f9d3c0205108e99aa7a9d (diff)
parent35bafbee4b4732a2820bbd0ef141c8192ff29731 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle: "Cleanups and fixes for breakage that occured earlier during this merge phase. Also a few patches that didn't make the first pull request. Of those is the Alchemy work that merges code for many of the SOCs and evaluation boards thus among other code shrinkage, reduces the number of MIPS defconfigs by 5." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (22 commits) MIPS: SNI: Switch RM400 serial to SCCNXP driver MIPS: Remove unused empty_bad_pmd_table[] declaration. MIPS: MT: Remove kspd. MIPS: Malta: Fix section mismatch. MIPS: asm-offset.c: Delete unused irq_cpustat_t struct offsets. MIPS: Alchemy: Merge PB1100/1500 support into DB1000 code. MIPS: Alchemy: merge PB1550 support into DB1550 code MIPS: Alchemy: Single kernel for DB1200/1300/1550 MIPS: Optimize TLB refill for RI/XI configurations. MIPS: proc: Cleanup printing of ASEs. MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required. MIPS: Add detection of DSP ASE Revision 2. MIPS: Optimize pgd_init and pmd_init MIPS: perf: Add perf functionality for BMIPS5000 MIPS: perf: Split the Kconfig option CONFIG_MIPS_MT_SMP MIPS: perf: Remove unnecessary #ifdef MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) MIPS: perf: Change the "mips_perf_event" table unsupported indicator. MIPS: Align swapper_pg_dir to 64K for better TLB Refill code. vmlinux.lds.h: Allow architectures to add sections to the front of .bss ...
Diffstat (limited to 'arch/mips/include/asm/ptrace.h')
-rw-r--r--arch/mips/include/asm/ptrace.h107
1 files changed, 1 insertions, 106 deletions
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 4b7f5252d2fd..4f5da948a777 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -9,115 +9,12 @@
9#ifndef _ASM_PTRACE_H 9#ifndef _ASM_PTRACE_H
10#define _ASM_PTRACE_H 10#define _ASM_PTRACE_H
11 11
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32
14#define PC 64
15#define CAUSE 65
16#define BADVADDR 66
17#define MMHI 67
18#define MMLO 68
19#define FPC_CSR 69
20#define FPC_EIR 70
21#define DSP_BASE 71 /* 3 more hi / lo register pairs */
22#define DSP_CONTROL 77
23#define ACX 78
24
25/*
26 * This struct defines the way the registers are stored on the stack during a
27 * system call/exception. As usual the registers k0/k1 aren't being saved.
28 */
29struct pt_regs {
30#ifdef CONFIG_32BIT
31 /* Pad bytes for argument save space on the stack. */
32 unsigned long pad0[6];
33#endif
34
35 /* Saved main processor registers. */
36 unsigned long regs[32];
37
38 /* Saved special registers. */
39 unsigned long cp0_status;
40 unsigned long hi;
41 unsigned long lo;
42#ifdef CONFIG_CPU_HAS_SMARTMIPS
43 unsigned long acx;
44#endif
45 unsigned long cp0_badvaddr;
46 unsigned long cp0_cause;
47 unsigned long cp0_epc;
48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
54#endif
55} __attribute__ ((aligned (8)));
56
57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
58#define PTRACE_GETREGS 12
59#define PTRACE_SETREGS 13
60#define PTRACE_GETFPREGS 14
61#define PTRACE_SETFPREGS 15
62/* #define PTRACE_GETFPXREGS 18 */
63/* #define PTRACE_SETFPXREGS 19 */
64
65#define PTRACE_OLDSETOPTIONS 21
66
67#define PTRACE_GET_THREAD_AREA 25
68#define PTRACE_SET_THREAD_AREA 26
69
70/* Calls to trace a 64bit program from a 32bit program. */
71#define PTRACE_PEEKTEXT_3264 0xc0
72#define PTRACE_PEEKDATA_3264 0xc1
73#define PTRACE_POKETEXT_3264 0xc2
74#define PTRACE_POKEDATA_3264 0xc3
75#define PTRACE_GET_THREAD_AREA_3264 0xc4
76
77/* Read and write watchpoint registers. */
78enum pt_watch_style {
79 pt_watch_style_mips32,
80 pt_watch_style_mips64
81};
82struct mips32_watch_regs {
83 unsigned int watchlo[8];
84 /* Lower 16 bits of watchhi. */
85 unsigned short watchhi[8];
86 /* Valid mask and I R W bits.
87 * bit 0 -- 1 if W bit is usable.
88 * bit 1 -- 1 if R bit is usable.
89 * bit 2 -- 1 if I bit is usable.
90 * bits 3 - 11 -- Valid watchhi mask bits.
91 */
92 unsigned short watch_masks[8];
93 /* The number of valid watch register pairs. */
94 unsigned int num_valid;
95} __attribute__((aligned(8)));
96
97struct mips64_watch_regs {
98 unsigned long long watchlo[8];
99 unsigned short watchhi[8];
100 unsigned short watch_masks[8];
101 unsigned int num_valid;
102} __attribute__((aligned(8)));
103
104struct pt_watch_regs {
105 enum pt_watch_style style;
106 union {
107 struct mips32_watch_regs mips32;
108 struct mips64_watch_regs mips64;
109 };
110};
111
112#define PTRACE_GET_WATCH_REGS 0xd0
113#define PTRACE_SET_WATCH_REGS 0xd1
114
115#ifdef __KERNEL__
116 12
117#include <linux/compiler.h> 13#include <linux/compiler.h>
118#include <linux/linkage.h> 14#include <linux/linkage.h>
119#include <linux/types.h> 15#include <linux/types.h>
120#include <asm/isadep.h> 16#include <asm/isadep.h>
17#include <uapi/asm/ptrace.h>
121 18
122struct task_struct; 19struct task_struct;
123 20
@@ -164,6 +61,4 @@ static inline void die_if_kernel(const char *str, struct pt_regs *regs)
164 die(str, regs); 61 die(str, regs);
165} 62}
166 63
167#endif
168
169#endif /* _ASM_PTRACE_H */ 64#endif /* _ASM_PTRACE_H */