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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/pmc-sierra
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/pmc-sierra')
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h46
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h151
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h43
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h205
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h176
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h236
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h663
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h141
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/war.h28
9 files changed, 1689 insertions, 0 deletions
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
new file mode 100644
index 000000000000..ebdbab973e41
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/gpio.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-mips/pmc-sierra/msp71xx/gpio.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * @author Patrick Glass <patrickglass@gmail.com>
9 */
10
11#ifndef __PMC_MSP71XX_GPIO_H
12#define __PMC_MSP71XX_GPIO_H
13
14/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
15#define ARCH_NR_GPIOS (28 + (3 * 8))
16
17/* new generic GPIO API - see Documentation/gpio.txt */
18#include <asm-generic/gpio.h>
19
20#define gpio_get_value __gpio_get_value
21#define gpio_set_value __gpio_set_value
22#define gpio_cansleep __gpio_cansleep
23
24/* Setup calls for the gpio and gpio extended */
25extern void msp71xx_init_gpio(void);
26extern void msp71xx_init_gpio_extended(void);
27extern int msp71xx_set_output_drive(unsigned gpio, int value);
28
29/* Custom output drive functionss */
30static inline int gpio_set_output_drive(unsigned gpio, int value)
31{
32 return msp71xx_set_output_drive(gpio, value);
33}
34
35/* IRQ's are not supported for gpio lines */
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(unsigned irq)
42{
43 return -EINVAL;
44}
45
46#endif /* __PMC_MSP71XX_GPIO_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
new file mode 100644
index 000000000000..c84bcf9570b1
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
@@ -0,0 +1,151 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_CIC_INT_H
26#define _MSP_CIC_INT_H
27
28/*
29 * The PMC-Sierra CIC interrupts are all centrally managed by the
30 * CIC sub-system.
31 * We attempt to keep the interrupt numbers as consistent as possible
32 * across all of the MSP devices, but some differences will creep in ...
33 * The interrupts which are directly forwarded to the MIPS core interrupts
34 * are assigned interrupts in the range 0-7, interrupts cascaded through
35 * the CIC are assigned interrupts 8-39. The cascade occurs on C_IRQ4
36 * (MSP_INT_CIC). Currently we don't really distinguish between VPE1
37 * and VPE0 (or thread contexts for that matter). Will have to fix.
38 * The PER interrupts are assigned interrupts in the range 40-71.
39*/
40
41
42/*
43 * IRQs directly forwarded to the CPU
44 */
45#define MSP_MIPS_INTBASE 0
46#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
47#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
48#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
49#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
50#define MSP_INT_USB 4 /* IRQ for USB, C_IRQ2 */
51#define MSP_INT_SAR 5 /* IRQ for ADSL2+ SAR, C_IRQ3 */
52#define MSP_INT_CIC 6 /* IRQ for CIC block, C_IRQ4 */
53#define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
54
55/*
56 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
57 * These defines should be tied to the register definitions for the CIC
58 * interrupt routine. For now, just use hard-coded values.
59 */
60#define MSP_CIC_INTBASE (MSP_MIPS_INTBASE + 8)
61#define MSP_INT_EXT0 (MSP_CIC_INTBASE + 0)
62 /* External interrupt 0 */
63#define MSP_INT_EXT1 (MSP_CIC_INTBASE + 1)
64 /* External interrupt 1 */
65#define MSP_INT_EXT2 (MSP_CIC_INTBASE + 2)
66 /* External interrupt 2 */
67#define MSP_INT_EXT3 (MSP_CIC_INTBASE + 3)
68 /* External interrupt 3 */
69#define MSP_INT_CPUIF (MSP_CIC_INTBASE + 4)
70 /* CPU interface interrupt */
71#define MSP_INT_EXT4 (MSP_CIC_INTBASE + 5)
72 /* External interrupt 4 */
73#define MSP_INT_CIC_USB (MSP_CIC_INTBASE + 6)
74 /* Cascaded IRQ for USB */
75#define MSP_INT_MBOX (MSP_CIC_INTBASE + 7)
76 /* Sec engine mailbox IRQ */
77#define MSP_INT_EXT5 (MSP_CIC_INTBASE + 8)
78 /* External interrupt 5 */
79#define MSP_INT_TDM (MSP_CIC_INTBASE + 9)
80 /* TDM interrupt */
81#define MSP_INT_CIC_MAC0 (MSP_CIC_INTBASE + 10)
82 /* Cascaded IRQ for MAC 0 */
83#define MSP_INT_CIC_MAC1 (MSP_CIC_INTBASE + 11)
84 /* Cascaded IRQ for MAC 1 */
85#define MSP_INT_CIC_SEC (MSP_CIC_INTBASE + 12)
86 /* Cascaded IRQ for sec engine */
87#define MSP_INT_PER (MSP_CIC_INTBASE + 13)
88 /* Peripheral interrupt */
89#define MSP_INT_TIMER0 (MSP_CIC_INTBASE + 14)
90 /* SLP timer 0 */
91#define MSP_INT_TIMER1 (MSP_CIC_INTBASE + 15)
92 /* SLP timer 1 */
93#define MSP_INT_TIMER2 (MSP_CIC_INTBASE + 16)
94 /* SLP timer 2 */
95#define MSP_INT_VPE0_TIMER (MSP_CIC_INTBASE + 17)
96 /* VPE0 MIPS timer */
97#define MSP_INT_BLKCP (MSP_CIC_INTBASE + 18)
98 /* Block Copy */
99#define MSP_INT_UART0 (MSP_CIC_INTBASE + 19)
100 /* UART 0 */
101#define MSP_INT_PCI (MSP_CIC_INTBASE + 20)
102 /* PCI subsystem */
103#define MSP_INT_EXT6 (MSP_CIC_INTBASE + 21)
104 /* External interrupt 5 */
105#define MSP_INT_PCI_MSI (MSP_CIC_INTBASE + 22)
106 /* PCI Message Signal */
107#define MSP_INT_CIC_SAR (MSP_CIC_INTBASE + 23)
108 /* Cascaded ADSL2+ SAR IRQ */
109#define MSP_INT_DSL (MSP_CIC_INTBASE + 24)
110 /* ADSL2+ IRQ */
111#define MSP_INT_CIC_ERR (MSP_CIC_INTBASE + 25)
112 /* SLP error condition */
113#define MSP_INT_VPE1_TIMER (MSP_CIC_INTBASE + 26)
114 /* VPE1 MIPS timer */
115#define MSP_INT_VPE0_PC (MSP_CIC_INTBASE + 27)
116 /* VPE0 Performance counter */
117#define MSP_INT_VPE1_PC (MSP_CIC_INTBASE + 28)
118 /* VPE1 Performance counter */
119#define MSP_INT_EXT7 (MSP_CIC_INTBASE + 29)
120 /* External interrupt 5 */
121#define MSP_INT_VPE0_SW (MSP_CIC_INTBASE + 30)
122 /* VPE0 Software interrupt */
123#define MSP_INT_VPE1_SW (MSP_CIC_INTBASE + 31)
124 /* VPE0 Software interrupt */
125
126/*
127 * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
128 */
129#define MSP_PER_INTBASE (MSP_CIC_INTBASE + 32)
130/* Reserved 0-1 */
131#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
132 /* UART 1 */
133/* Reserved 3-5 */
134#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
135 /* 2-wire */
136#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
137 /* Peripheral timer block out 0 */
138#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
139 /* Peripheral timer block out 1 */
140/* Reserved 9 */
141#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
142 /* SPI RX complete */
143#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
144 /* SPI TX complete */
145#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
146 /* GPIO */
147#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
148 /* Peripheral error */
149/* Reserved 14-31 */
150
151#endif /* !_MSP_CIC_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
new file mode 100644
index 000000000000..1d9f05474820
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
@@ -0,0 +1,43 @@
1/*
2 * Defines for the MSP interrupt handlers.
3 *
4 * Copyright (C) 2005, PMC-Sierra, Inc. All rights reserved.
5 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_INT_H
26#define _MSP_INT_H
27
28/*
29 * The PMC-Sierra MSP product line has at least two different interrupt
30 * controllers, the SLP register based scheme and the CIC interrupt
31 * controller block mechanism. This file distinguishes between them
32 * so that devices see a uniform interface.
33 */
34
35#if defined(CONFIG_IRQ_MSP_SLP)
36 #include "msp_slp_int.h"
37#elif defined(CONFIG_IRQ_MSP_CIC)
38 #include "msp_cic_int.h"
39#else
40 #error "What sort of interrupt controller does *your* MSP have?"
41#endif
42
43#endif /* !_MSP_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
new file mode 100644
index 000000000000..415606903617
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2000-2006 PMC-Sierra INC.
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 *
21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
23 * SOFTWARE.
24 */
25
26#ifndef _MSP_PCI_H_
27#define _MSP_PCI_H_
28
29#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
30
31/*
32 * It is convenient to program the OATRAN register so that
33 * Athena virtual address space and PCI address space are
34 * the same. This is not a requirement, just a convenience.
35 *
36 * The only hard restrictions on the value of OATRAN is that
37 * OATRAN must not be programmed to allow translated memory
38 * addresses to fall within the lowest 512MB of
39 * PCI address space. This region is hardcoded
40 * for use as Athena PCI Host Controller target
41 * access memory space to the Athena's SDRAM.
42 *
43 * Note that OATRAN applies only to memory accesses, not
44 * to I/O accesses.
45 *
46 * To program OATRAN to make Athena virtual address space
47 * and PCI address space have the same values, OATRAN
48 * is to be programmed to 0xB8000000. The top seven
49 * bits of the value mimic the seven bits clipped off
50 * by the PCI Host controller.
51 *
52 * With OATRAN at the said value, when the CPU does
53 * an access to its virtual address at, say 0xB900_5000,
54 * the address appearing on the PCI bus will be
55 * 0xB900_5000.
56 * - Michael Penner
57 */
58#define MSP_PCI_OATRAN 0xB8000000UL
59
60#define MSP_PCI_SPACE_BASE (MSP_PCI_OATRAN + 0x1002000UL)
61#define MSP_PCI_SPACE_SIZE (0x3000000UL - 0x2000)
62#define MSP_PCI_SPACE_END \
63 (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
64#define MSP_PCI_IOSPACE_BASE (MSP_PCI_OATRAN + 0x1001000UL)
65#define MSP_PCI_IOSPACE_SIZE 0x1000
66#define MSP_PCI_IOSPACE_END \
67 (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
68
69/* IRQ for PCI status interrupts */
70#define PCI_STAT_IRQ 20
71
72#define QFLUSH_REG_1 0xB7F40000
73
74typedef volatile unsigned int pcireg;
75typedef void * volatile ppcireg;
76
77struct pci_block_copy
78{
79 pcireg unused1; /* +0x00 */
80 pcireg unused2; /* +0x04 */
81 ppcireg unused3; /* +0x08 */
82 ppcireg unused4; /* +0x0C */
83 pcireg unused5; /* +0x10 */
84 pcireg unused6; /* +0x14 */
85 pcireg unused7; /* +0x18 */
86 ppcireg unused8; /* +0x1C */
87 ppcireg unused9; /* +0x20 */
88 pcireg unusedA; /* +0x24 */
89 ppcireg unusedB; /* +0x28 */
90 ppcireg unusedC; /* +0x2C */
91};
92
93enum
94{
95 config_device_vendor, /* 0 */
96 config_status_command, /* 1 */
97 config_class_revision, /* 2 */
98 config_BIST_header_latency_cache, /* 3 */
99 config_BAR0, /* 4 */
100 config_BAR1, /* 5 */
101 config_BAR2, /* 6 */
102 config_not_used7, /* 7 */
103 config_not_used8, /* 8 */
104 config_not_used9, /* 9 */
105 config_CIS, /* 10 */
106 config_subsystem, /* 11 */
107 config_not_used12, /* 12 */
108 config_capabilities, /* 13 */
109 config_not_used14, /* 14 */
110 config_lat_grant_irq, /* 15 */
111 config_message_control,/* 16 */
112 config_message_addr, /* 17 */
113 config_message_data, /* 18 */
114 config_VPD_addr, /* 19 */
115 config_VPD_data, /* 20 */
116 config_maxregs /* 21 - number of registers */
117};
118
119struct msp_pci_regs
120{
121 pcireg hop_unused_00; /* +0x00 */
122 pcireg hop_unused_04; /* +0x04 */
123 pcireg hop_unused_08; /* +0x08 */
124 pcireg hop_unused_0C; /* +0x0C */
125 pcireg hop_unused_10; /* +0x10 */
126 pcireg hop_unused_14; /* +0x14 */
127 pcireg hop_unused_18; /* +0x18 */
128 pcireg hop_unused_1C; /* +0x1C */
129 pcireg hop_unused_20; /* +0x20 */
130 pcireg hop_unused_24; /* +0x24 */
131 pcireg hop_unused_28; /* +0x28 */
132 pcireg hop_unused_2C; /* +0x2C */
133 pcireg hop_unused_30; /* +0x30 */
134 pcireg hop_unused_34; /* +0x34 */
135 pcireg if_control; /* +0x38 */
136 pcireg oatran; /* +0x3C */
137 pcireg reset_ctl; /* +0x40 */
138 pcireg config_addr; /* +0x44 */
139 pcireg hop_unused_48; /* +0x48 */
140 pcireg msg_signaled_int_status; /* +0x4C */
141 pcireg msg_signaled_int_mask; /* +0x50 */
142 pcireg if_status; /* +0x54 */
143 pcireg if_mask; /* +0x58 */
144 pcireg hop_unused_5C; /* +0x5C */
145 pcireg hop_unused_60; /* +0x60 */
146 pcireg hop_unused_64; /* +0x64 */
147 pcireg hop_unused_68; /* +0x68 */
148 pcireg hop_unused_6C; /* +0x6C */
149 pcireg hop_unused_70; /* +0x70 */
150
151 struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
152
153 pcireg error_hdr1; /* +0xE0 */
154 pcireg error_hdr2; /* +0xE4 */
155
156 pcireg config[config_maxregs] __attribute__((aligned(256)));
157
158};
159
160#define BPCI_CFGADDR_BUSNUM_SHF 16
161#define BPCI_CFGADDR_FUNCTNUM_SHF 8
162#define BPCI_CFGADDR_REGNUM_SHF 2
163#define BPCI_CFGADDR_ENABLE (1<<31)
164
165#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
166#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
167#define BPCI_IFCONTROL_CTO_SHF 12 /* Shift count for CTO bits */
168#define BPCI_IFCONTROL_SE (1<<5) /* Enable exceptions on errors */
169#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
170#define BPCI_IFCONTROL_CAP (1<<3) /* Enable capabilities */
171#define BPCI_IFCONTROL_MMC_SHF 0 /* Shift count for MMC bits */
172
173#define BPCI_IFSTATUS_MGT (1<<8) /* Master Grant timeout */
174#define BPCI_IFSTATUS_MTT (1<<9) /* Master TRDY timeout */
175#define BPCI_IFSTATUS_MRT (1<<10) /* Master retry timeout */
176#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
177#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
178#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
179#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
180#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
181#define BPCI_IFSTATUS_RTO (1<<18) /* Retry time out */
182#define BPCI_IFSTATUS_SER (1<<19) /* System error */
183#define BPCI_IFSTATUS_PER (1<<20) /* Parity error */
184#define BPCI_IFSTATUS_LCA (1<<21) /* Local CPU abort */
185#define BPCI_IFSTATUS_MEM (1<<22) /* Memory prot. violation */
186#define BPCI_IFSTATUS_ARB (1<<23) /* Arbiter timed out */
187#define BPCI_IFSTATUS_STA (1<<27) /* Signaled target abort */
188#define BPCI_IFSTATUS_TA (1<<28) /* Target abort */
189#define BPCI_IFSTATUS_MA (1<<29) /* Master abort */
190#define BPCI_IFSTATUS_PEI (1<<30) /* Parity error as initiator */
191#define BPCI_IFSTATUS_PET (1<<31) /* Parity error as target */
192
193#define BPCI_RESETCTL_PR (1<<0) /* True if reset asserted */
194#define BPCI_RESETCTL_RT (1<<4) /* Release time */
195#define BPCI_RESETCTL_CT (1<<8) /* Config time */
196#define BPCI_RESETCTL_PE (1<<12) /* PCI enabled */
197#define BPCI_RESETCTL_HM (1<<13) /* PCI host mode */
198#define BPCI_RESETCTL_RI (1<<14) /* PCI reset in */
199
200extern struct msp_pci_regs msp_pci_regs
201 __attribute__((section(".register")));
202extern unsigned long msp_pci_config_space
203 __attribute__((section(".register")));
204
205#endif /* !_MSP_PCI_H_ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
new file mode 100644
index 000000000000..14ca7dc382a8
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -0,0 +1,176 @@
1/*
2 * MIPS boards bootprom interface for the Linux kernel.
3 *
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _ASM_MSP_PROM_H
26#define _ASM_MSP_PROM_H
27
28#include <linux/types.h>
29
30#define DEVICEID "deviceid"
31#define FEATURES "features"
32#define PROM_ENV "prom_env"
33#define PROM_ENV_FILE "/proc/"PROM_ENV
34#define PROM_ENV_SIZE 256
35
36#define CPU_DEVID_FAMILY 0x0000ff00
37#define CPU_DEVID_REVISION 0x000000ff
38
39#define FPGA_IS_POLO(revision) \
40 (((revision >= 0xb0) && (revision < 0xd0)))
41#define FPGA_IS_5000(revision) \
42 ((revision >= 0x80) && (revision <= 0x90))
43#define FPGA_IS_ZEUS(revision) ((revision < 0x7f))
44#define FPGA_IS_DUET(revision) \
45 (((revision >= 0xa0) && (revision < 0xb0)))
46#define FPGA_IS_MSP4200(revision) ((revision >= 0xd0))
47#define FPGA_IS_MSP7100(revision) ((revision >= 0xd0))
48
49#define MACHINE_TYPE_POLO "POLO"
50#define MACHINE_TYPE_DUET "DUET"
51#define MACHINE_TYPE_ZEUS "ZEUS"
52#define MACHINE_TYPE_MSP2000REVB "MSP2000REVB"
53#define MACHINE_TYPE_MSP5000 "MSP5000"
54#define MACHINE_TYPE_MSP4200 "MSP4200"
55#define MACHINE_TYPE_MSP7120 "MSP7120"
56#define MACHINE_TYPE_MSP7130 "MSP7130"
57#define MACHINE_TYPE_OTHER "OTHER"
58
59#define MACHINE_TYPE_POLO_FPGA "POLO-FPGA"
60#define MACHINE_TYPE_DUET_FPGA "DUET-FPGA"
61#define MACHINE_TYPE_ZEUS_FPGA "ZEUS_FPGA"
62#define MACHINE_TYPE_MSP2000REVB_FPGA "MSP2000REVB-FPGA"
63#define MACHINE_TYPE_MSP5000_FPGA "MSP5000-FPGA"
64#define MACHINE_TYPE_MSP4200_FPGA "MSP4200-FPGA"
65#define MACHINE_TYPE_MSP7100_FPGA "MSP7100-FPGA"
66#define MACHINE_TYPE_OTHER_FPGA "OTHER-FPGA"
67
68/* Device Family definitions */
69#define FAMILY_FPGA 0x0000
70#define FAMILY_ZEUS 0x1000
71#define FAMILY_POLO 0x2000
72#define FAMILY_DUET 0x4000
73#define FAMILY_TRIAD 0x5000
74#define FAMILY_MSP4200 0x4200
75#define FAMILY_MSP4200_FPGA 0x4f00
76#define FAMILY_MSP7100 0x7100
77#define FAMILY_MSP7100_FPGA 0x7f00
78
79/* Device Type definitions */
80#define TYPE_MSP7120 0x7120
81#define TYPE_MSP7130 0x7130
82
83#define ENET_KEY 'E'
84#define ENETTXD_KEY 'e'
85#define PCI_KEY 'P'
86#define PCIMUX_KEY 'p'
87#define SEC_KEY 'S'
88#define SPAD_KEY 'D'
89#define TDM_KEY 'T'
90#define ZSP_KEY 'Z'
91
92#define FEATURE_NOEXIST '-'
93#define FEATURE_EXIST '+'
94
95#define ENET_MII 'M'
96#define ENET_RMII 'R'
97
98#define ENETTXD_FALLING 'F'
99#define ENETTXD_RISING 'R'
100
101#define PCI_HOST 'H'
102#define PCI_PERIPHERAL 'P'
103
104#define PCIMUX_FULL 'F'
105#define PCIMUX_SINGLE 'S'
106
107#define SEC_DUET 'D'
108#define SEC_POLO 'P'
109#define SEC_SLOW 'S'
110#define SEC_TRIAD 'T'
111
112#define SPAD_POLO 'P'
113
114#define TDM_DUET 'D' /* DUET TDMs might exist */
115#define TDM_POLO 'P' /* POLO TDMs might exist */
116#define TDM_TRIAD 'T' /* TRIAD TDMs might exist */
117
118#define ZSP_DUET 'D' /* one DUET zsp engine */
119#define ZSP_TRIAD 'T' /* two TRIAD zsp engines */
120
121extern char *prom_getcmdline(void);
122extern char *prom_getenv(char *name);
123extern void prom_init_cmdline(void);
124extern void prom_meminit(void);
125extern void prom_fixup_mem_map(unsigned long start_mem,
126 unsigned long end_mem);
127
128#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
129extern bool get_ramroot(void **start, unsigned long *size);
130#endif
131
132extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
133extern unsigned long get_deviceid(void);
134extern char identify_enet(unsigned long interface_num);
135extern char identify_enetTxD(unsigned long interface_num);
136extern char identify_pci(void);
137extern char identify_sec(void);
138extern char identify_spad(void);
139extern char identify_sec(void);
140extern char identify_tdm(void);
141extern char identify_zsp(void);
142extern unsigned long identify_family(void);
143extern unsigned long identify_revision(void);
144
145/*
146 * The following macro calls prom_printf and puts the format string
147 * into an init section so it can be reclaimed.
148 */
149#define ppfinit(f, x...) \
150 do { \
151 static char _f[] __initdata = KERN_INFO f; \
152 printk(_f, ## x); \
153 } while (0)
154
155/* Memory descriptor management. */
156#define PROM_MAX_PMEMBLOCKS 7 /* 6 used */
157
158enum yamon_memtypes {
159 yamon_dontuse,
160 yamon_prom,
161 yamon_free,
162};
163
164struct prom_pmemblock {
165 unsigned long base; /* Within KSEG0. */
166 unsigned int size; /* In bytes. */
167 unsigned int type; /* free or prom memory */
168};
169
170extern int prom_argc;
171extern char **prom_argv;
172extern char **prom_envp;
173extern int *prom_vec;
174extern struct prom_pmemblock *prom_getmdesc(void);
175
176#endif /* !_ASM_MSP_PROM_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
new file mode 100644
index 000000000000..60a5a38dd5b2
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -0,0 +1,236 @@
1/*
2 * SMP/VPE-safe functions to access "registers" (see note).
3 *
4 * NOTES:
5* - These macros use ll/sc instructions, so it is your responsibility to
6 * ensure these are available on your platform before including this file.
7 * - The MIPS32 spec states that ll/sc results are undefined for uncached
8 * accesses. This means they can't be used on HW registers accessed
9 * through kseg1. Code which requires these macros for this purpose must
10 * front-end the registers with cached memory "registers" and have a single
11 * thread update the actual HW registers.
12 * - A maximum of 2k of code can be inserted between ll and sc. Every
13 * memory accesses between the instructions will increase the chance of
14 * sc failing and having to loop.
15 * - When using custom_read_reg32/custom_write_reg32 only perform the
16 * necessary logical operations on the register value in between these
17 * two calls. All other logic should be performed before the first call.
18 * - There is a bug on the R10000 chips which has a workaround. If you
19 * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
20 * to be non-zero. If you are using this header from within linux, you may
21 * include <asm/war.h> before including this file to have this defined
22 * appropriately for you.
23 *
24 * Copyright 2005-2007 PMC-Sierra, Inc.
25 *
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License as published by the
28 * Free Software Foundation; either version 2 of the License, or (at your
29 * option) any later version.
30 *
31 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
32 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
33 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
34 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * You should have received a copy of the GNU General Public License along
43 * with this program; if not, write to the Free Software Foundation, Inc., 675
44 * Mass Ave, Cambridge, MA 02139, USA.
45 */
46
47#ifndef __ASM_REGOPS_H__
48#define __ASM_REGOPS_H__
49
50#include <linux/types.h>
51
52#include <asm/war.h>
53
54#ifndef R10000_LLSC_WAR
55#define R10000_LLSC_WAR 0
56#endif
57
58#if R10000_LLSC_WAR == 1
59#define __beqz "beqzl "
60#else
61#define __beqz "beqz "
62#endif
63
64#ifndef _LINUX_TYPES_H
65typedef unsigned int u32;
66#endif
67
68/*
69 * Sets all the masked bits to the corresponding value bits
70 */
71static inline void set_value_reg32(volatile u32 *const addr,
72 u32 const mask,
73 u32 const value)
74{
75 u32 temp;
76
77 __asm__ __volatile__(
78 " .set push \n"
79 " .set mips3 \n"
80 "1: ll %0, %1 # set_value_reg32 \n"
81 " and %0, %2 \n"
82 " or %0, %3 \n"
83 " sc %0, %1 \n"
84 " "__beqz"%0, 1b \n"
85 " nop \n"
86 " .set pop \n"
87 : "=&r" (temp), "=m" (*addr)
88 : "ir" (~mask), "ir" (value), "m" (*addr));
89}
90
91/*
92 * Sets all the masked bits to '1'
93 */
94static inline void set_reg32(volatile u32 *const addr,
95 u32 const mask)
96{
97 u32 temp;
98
99 __asm__ __volatile__(
100 " .set push \n"
101 " .set mips3 \n"
102 "1: ll %0, %1 # set_reg32 \n"
103 " or %0, %2 \n"
104 " sc %0, %1 \n"
105 " "__beqz"%0, 1b \n"
106 " nop \n"
107 " .set pop \n"
108 : "=&r" (temp), "=m" (*addr)
109 : "ir" (mask), "m" (*addr));
110}
111
112/*
113 * Sets all the masked bits to '0'
114 */
115static inline void clear_reg32(volatile u32 *const addr,
116 u32 const mask)
117{
118 u32 temp;
119
120 __asm__ __volatile__(
121 " .set push \n"
122 " .set mips3 \n"
123 "1: ll %0, %1 # clear_reg32 \n"
124 " and %0, %2 \n"
125 " sc %0, %1 \n"
126 " "__beqz"%0, 1b \n"
127 " nop \n"
128 " .set pop \n"
129 : "=&r" (temp), "=m" (*addr)
130 : "ir" (~mask), "m" (*addr));
131}
132
133/*
134 * Toggles all masked bits from '0' to '1' and '1' to '0'
135 */
136static inline void toggle_reg32(volatile u32 *const addr,
137 u32 const mask)
138{
139 u32 temp;
140
141 __asm__ __volatile__(
142 " .set push \n"
143 " .set mips3 \n"
144 "1: ll %0, %1 # toggle_reg32 \n"
145 " xor %0, %2 \n"
146 " sc %0, %1 \n"
147 " "__beqz"%0, 1b \n"
148 " nop \n"
149 " .set pop \n"
150 : "=&r" (temp), "=m" (*addr)
151 : "ir" (mask), "m" (*addr));
152}
153
154/*
155 * Read all masked bits others are returned as '0'
156 */
157static inline u32 read_reg32(volatile u32 *const addr,
158 u32 const mask)
159{
160 u32 temp;
161
162 __asm__ __volatile__(
163 " .set push \n"
164 " .set noreorder \n"
165 " lw %0, %1 # read \n"
166 " and %0, %2 # mask \n"
167 " .set pop \n"
168 : "=&r" (temp)
169 : "m" (*addr), "ir" (mask));
170
171 return temp;
172}
173
174/*
175 * blocking_read_reg32 - Read address with blocking load
176 *
177 * Uncached writes need to be read back to ensure they reach RAM.
178 * The returned value must be 'used' to prevent from becoming a
179 * non-blocking load.
180 */
181static inline u32 blocking_read_reg32(volatile u32 *const addr)
182{
183 u32 temp;
184
185 __asm__ __volatile__(
186 " .set push \n"
187 " .set noreorder \n"
188 " lw %0, %1 # read \n"
189 " move %0, %0 # block \n"
190 " .set pop \n"
191 : "=&r" (temp)
192 : "m" (*addr));
193
194 return temp;
195}
196
197/*
198 * For special strange cases only:
199 *
200 * If you need custom processing within a ll/sc loop, use the following macros
201 * VERY CAREFULLY:
202 *
203 * u32 tmp; <-- Define a variable to hold the data
204 *
205 * custom_read_reg32(address, tmp); <-- Reads the address and put the value
206 * in the 'tmp' variable given
207 *
208 * From here on out, you are (basicly) atomic, so don't do anything too
209 * fancy!
210 * Also, this code may loop if the end of this block fails to write
211 * everything back safely due do the other CPU, so do NOT do anything
212 * with side-effects!
213 *
214 * custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
215 */
216#define custom_read_reg32(address, tmp) \
217 __asm__ __volatile__( \
218 " .set push \n" \
219 " .set mips3 \n" \
220 "1: ll %0, %1 #custom_read_reg32 \n" \
221 " .set pop \n" \
222 : "=r" (tmp), "=m" (*address) \
223 : "m" (*address))
224
225#define custom_write_reg32(address, tmp) \
226 __asm__ __volatile__( \
227 " .set push \n" \
228 " .set mips3 \n" \
229 " sc %0, %1 #custom_write_reg32 \n" \
230 " "__beqz"%0, 1b \n" \
231 " nop \n" \
232 " .set pop \n" \
233 : "=&r" (tmp), "=m" (*address) \
234 : "0" (tmp), "m" (*address))
235
236#endif /* __ASM_REGOPS_H__ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
new file mode 100644
index 000000000000..603eb737b4a8
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
@@ -0,0 +1,663 @@
1/*
2 * Defines for the address space, registers and register configuration
3 * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
4 * This file contains addess maps for all the devices in the line of
5 * products but only has register definitions and configuration masks for
6 * registers which aren't definitely associated with any device. Things
7 * like clock settings, reset access, the ELB etc. Individual device
8 * drivers will reference the appropriate XXX_BASE value defined here
9 * and have individual registers offset from that.
10 *
11 * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved.
12 * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
13 *
14 * ########################################################################
15 *
16 * This program is free software; you can distribute it and/or modify it
17 * under the terms of the GNU General Public License (Version 2) as
18 * published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope it will be useful, but WITHOUT
21 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 * for more details.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
28 *
29 * ########################################################################
30 */
31
32#include <asm/addrspace.h>
33#include <linux/types.h>
34
35#ifndef _ASM_MSP_REGS_H
36#define _ASM_MSP_REGS_H
37
38/*
39 ########################################################################
40 # Address space and device base definitions #
41 ########################################################################
42 */
43
44/*
45 ***************************************************************************
46 * System Logic and Peripherals (ELB, UART0, etc) device address space *
47 ***************************************************************************
48 */
49#define MSP_SLP_BASE 0x1c000000
50 /* System Logic and Peripherals */
51#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
52 /* System reset register base */
53#define MSP_RST_SIZE 0x0C /* System reset register space */
54
55#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
56 /* watchdog timer base */
57#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
58 /* internal timer base */
59#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
60 /* UART0 controller base */
61#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
62 /* Block Copy controller base */
63#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
64 /* Block Copy descriptor base */
65
66/*
67 ***************************************************************************
68 * PCI address space *
69 ***************************************************************************
70 */
71#define MSP_PCI_BASE 0x19000000
72
73/*
74 ***************************************************************************
75 * MSbus device address space *
76 ***************************************************************************
77 */
78#define MSP_MSB_BASE 0x18000000
79 /* MSbus address start */
80#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)
81 /* Peripheral device registers */
82#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)
83 /* MAC A device registers */
84#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)
85 /* MAC B device registers */
86#define MSP_MAC_SIZE 0xE0 /* MAC register space */
87
88#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)
89 /* Security Engine registers */
90#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)
91 /* MAC C device registers */
92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
93 /* ADSL2 device registers */
94#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000)
95 /* USB device registers */
96#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100)
97 /* USB device registers */
98#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
99 /* USB device registers */
100#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
101 /* CPU interface registers */
102
103/* Devices within the MSbus peripheral block */
104#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)
105 /* UART1 controller base */
106#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)
107 /* SPI/MPI control registers */
108#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)
109 /* Two-wire control registers */
110#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)
111 /* Programmable timer control */
112
113/*
114 ***************************************************************************
115 * Physical Memory configuration address space *
116 ***************************************************************************
117 */
118#define MSP_MEM_CFG_BASE 0x17f00000
119
120#define MSP_MEM_INDIRECT_CTL_10 0x10
121
122/*
123 * Notes:
124 * 1) The SPI registers are split into two blocks, one offset from the
125 * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
126 * 0x68. The SPI driver definitions for the register must be aware
127 * of this.
128 * 2) The block copy engine register are divided into two regions, one
129 * for the control/configuration of the engine proper and one for the
130 * values of the descriptors used in the copy process. These have
131 * different base defines (CTRL_BASE vs DESC_BASE)
132 * 3) These constants are for physical addresses which means that they
133 * work correctly with "ioremap" and friends. This means that device
134 * drivers will need to remap these addresses using ioremap and perhaps
135 * the readw/writew macros. Or they could use the regptr() macro
136 * defined below, but the readw/writew calls are the correct thing.
137 * 4) The UARTs have an additional status register offset from the base
138 * address. This register isn't used in the standard 8250 driver but
139 * may be used in other software. Consult the hardware datasheet for
140 * offset details.
141 * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers
142 * start at an offset of 0x84 from the base address but the block of
143 * registers before this is reserved for the security engine. The
144 * driver will have to be aware of this but it makes the register
145 * definitions line up better with the documentation.
146 */
147
148/*
149 ########################################################################
150 # System register definitions. Not associated with a specific device #
151 ########################################################################
152 */
153
154/*
155 * This macro maps the physical register number into uncached space
156 * and (for C code) casts it into a u32 pointer so it can be dereferenced
157 * Normally these would be accessed with ioremap and readX/writeX, but
158 * these are convenient for a lot of internal kernel code.
159 */
160#ifdef __ASSEMBLER__
161 #define regptr(addr) (KSEG1ADDR(addr))
162#else
163 #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
164#endif
165
166/*
167 ***************************************************************************
168 * System Logic and Peripherals (RESET, ELB, etc) registers *
169 ***************************************************************************
170 */
171
172/* System Control register definitions */
173#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
174 /* Device-ID RO */
175#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
176 /* Firmware-ID Register RW */
177#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
178 /* System-ID Register-0 RW */
179#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
180 /* System-ID Register-1 RW */
181
182/* System Reset register definitions */
183#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
184 /* System Reset Status RO */
185#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
186 /* System Set Reset WO */
187#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
188 /* System Clear Reset WO */
189
190/* System Clock Registers */
191#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
192 /* PCI clock generator RW */
193#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
194 /* UART clock generator RW */
195/* reserved (MSP_SLP_BASE + 0x24) */
196/* reserved (MSP_SLP_BASE + 0x28) */
197#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
198 /* PLL1 clock generator RW */
199#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
200 /* PLL0 clock generator RW */
201#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
202 /* MIPS clock generator RW */
203#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
204 /* Voice Eng clock generator RW */
205/* reserved (MSP_SLP_BASE + 0x3C) */
206#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
207 /* MS-Bus clock generator RW */
208#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
209 /* Sec & MAC clock generator RW */
210#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
211 /* Per & TDM clock generator RW */
212
213/* Interrupt Controller Registers */
214#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
215 /* Interrupt status register RW */
216#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
217 /* Interrupt enable/mask RW */
218#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
219 /* Security Engine mailbox RW */
220#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
221 /* Voice Engine mailbox RW */
222
223/* ELB Controller Registers */
224#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
225 /* ELB CS0 Configuration Reg */
226#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
227 /* ELB CS0 Base Address Reg */
228#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
229 /* ELB CS0 Mask Register */
230#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
231 /* ELB CS0 access register */
232
233#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
234 /* ELB CS1 Configuration Reg */
235#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
236 /* ELB CS1 Base Address Reg */
237#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
238 /* ELB CS1 Mask Register */
239#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
240 /* ELB CS1 access register */
241
242#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
243 /* ELB CS2 Configuration Reg */
244#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
245 /* ELB CS2 Base Address Reg */
246#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
247 /* ELB CS2 Mask Register */
248#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
249 /* ELB CS2 access register */
250
251#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
252 /* ELB CS3 Configuration Reg */
253#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
254 /* ELB CS3 Base Address Reg */
255#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
256 /* ELB CS3 Mask Register */
257#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
258 /* ELB CS3 access register */
259
260#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
261 /* ELB CS4 Configuration Reg */
262#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
263 /* ELB CS4 Base Address Reg */
264#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
265 /* ELB CS4 Mask Register */
266#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
267 /* ELB CS4 access register */
268
269#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
270 /* ELB CS5 Configuration Reg */
271#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
272 /* ELB CS5 Base Address Reg */
273#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
274 /* ELB CS5 Mask Register */
275#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
276 /* ELB CS5 access register */
277
278/* reserved 0xE0 - 0xE8 */
279#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
280 /* ELB single PC card detect */
281
282/* reserved 0xF0 - 0xF8 */
283#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
284 /* SDRAM read/ELB timing Reg */
285
286/* Extended UART status registers */
287#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)
288 /* UART Status Register 0 */
289#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)
290 /* UART Status Register 1 */
291
292/* Performance monitoring registers */
293#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
294 /* Performance monitor control */
295#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
296 /* Performance monitor clear */
297#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
298 /* Perf monitor counter high */
299#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
300 /* Perf monitor counter low */
301
302/* System control registers */
303#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
304 /* System control register */
305#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
306 /* System Error status 1 */
307#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
308 /* System Error status 2 */
309#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
310 /* System Interrupt config */
311
312/* Voice Engine Memory configuration */
313#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
314 /* Voice engine memory config */
315
316/* CPU/SLP Error Status registers */
317#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
318 /* CPU/SLP Error status 1 */
319#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
320 /* CPU/SLP Error status 1 */
321
322#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188)
323 /* Extended GPIO register */
324
325/* System Error registers */
326#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
327 /* Int status for SLP errors */
328#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
329 /* Int mask for SLP errors */
330#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
331 /* External ELB reset */
332#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
333 /* Boot Status */
334
335/* Extended ELB addressing */
336#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
337 /* CS0 Extended address */
338#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
339 /* CS1 Extended address */
340#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
341 /* CS2 Extended address */
342#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
343 /* CS3 Extended address */
344/* reserved 0x1B0 */
345#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
346 /* CS5 Extended address */
347
348/* PLL Adjustment registers */
349#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
350 /* PLL0 lock status */
351#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
352 /* PLL Analog reset status */
353#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
354 /* PLL0 Adjustment value */
355#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
356 /* PLL1 Adjustment value */
357
358/*
359 ***************************************************************************
360 * Peripheral Register definitions *
361 ***************************************************************************
362 */
363
364/* Peripheral status */
365#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)
366 /* Peripheral control register */
367#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)
368 /* Peripheral status register */
369
370/* SPI/MPI Registers */
371#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)
372 /* SPI/MPI Tx Size register */
373#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)
374 /* SPI/MPI Rx Size register */
375#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)
376 /* SPI/MPI Control register */
377#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)
378 /* SPI/MPI Chip Select reg */
379#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)
380 /* SPI/MPI Core Data reg */
381#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)
382 /* SPI/MPI Core Control reg */
383#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)
384 /* SPI/MPI Core Status reg */
385#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)
386 /* SPI/MPI Core Ssel reg */
387#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)
388 /* SPI/MPI Data FIFO reg */
389
390/* Peripheral Block Error Registers */
391#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)
392 /* Error Bit Status Register */
393#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)
394 /* Error Bit Mask Register */
395#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)
396 /* Error Header 1 Register */
397#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)
398 /* Error Header 2 Register */
399
400/* Peripheral Block Interrupt Registers */
401#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)
402 /* Interrupt status register */
403#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)
404 /* Interrupt Mask Register */
405#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)
406 /* GPIO interrupt status reg */
407#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)
408 /* GPIO interrupt MASK Reg */
409
410/* POLO GPIO registers */
411#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)
412 /* Polo GPIO[8:0] data reg */
413#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)
414 /* Polo GPIO[7:0] config reg */
415#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)
416 /* Polo GPIO[15:8] config reg */
417#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)
418 /* Polo GPIO[31:0] output drive */
419#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)
420 /* Polo GPIO[23:16] config reg */
421#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)
422 /* Polo GPIO[15:9] data reg */
423#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)
424 /* Polo GPIO[23:16] data reg */
425#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)
426 /* Polo GPIO[31:24] data reg */
427#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)
428 /* Polo GPIO[39:32] data reg */
429#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)
430 /* Polo GPIO[47:40] data reg */
431#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)
432 /* Polo GPIO[54:48] data reg */
433#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
434 /* Polo GPIO[31:24] config reg */
435#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)
436 /* Polo GPIO[39:32] config reg */
437#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)
438 /* Polo GPIO[47:40] config reg */
439#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)
440 /* Polo GPIO[54:48] config reg */
441#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)
442 /* Polo GPIO[54:32] output drive */
443
444/* Generic GPIO registers */
445#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)
446 /* GPIO[1:0] data register */
447#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)
448 /* GPIO[5:2] data register */
449#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)
450 /* GPIO[9:6] data register */
451#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)
452 /* GPIO[15:10] data register */
453#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)
454 /* GPIO[1:0] config register */
455#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)
456 /* GPIO[5:2] config register */
457#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)
458 /* GPIO[9:6] config register */
459#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)
460 /* GPIO[15:10] config register */
461#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)
462 /* GPIO[15:0] output drive */
463
464/*
465 ***************************************************************************
466 * CPU Interface register definitions *
467 ***************************************************************************
468 */
469#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)
470 /* PCI-SDRAM queue flush trigger */
471#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)
472 /* OCP Error Attribute 1 */
473#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)
474 /* OCP Error Attribute 2 */
475#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)
476 /* OCP Error Status */
477#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)
478 /* CPU policy configuration */
479#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)
480 /* Misc configuration options */
481
482/* Central Interrupt Controller Registers */
483#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)
484 /* Central Interrupt registers */
485#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)
486 /* External interrupt config */
487#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)
488 /* CIC Interrupt Status */
489#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)
490 /* VPE0 Interrupt Mask */
491#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)
492 /* VPE1 Interrupt Mask */
493#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)
494 /* Thread Context 0 Int Mask */
495#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)
496 /* Thread Context 1 Int Mask */
497#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)
498 /* Thread Context 2 Int Mask */
499#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)
500 /* Thread Context 3 Int Mask */
501#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)
502 /* Thread Context 4 Int Mask */
503#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)
504#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)
505#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)
506#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)
507
508
509/*
510 ***************************************************************************
511 * Memory controller registers *
512 ***************************************************************************
513 */
514#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)
515#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)
516#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)
517#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)
518
519/*
520 ***************************************************************************
521 * PCI controller registers *
522 ***************************************************************************
523 */
524#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)
525#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)
526#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)
527
528/*
529 ########################################################################
530 # Register content & macro definitions #
531 ########################################################################
532 */
533
534/*
535 ***************************************************************************
536 * DEV_ID defines *
537 ***************************************************************************
538 */
539#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */
540#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */
541#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */
542#define DEV_ID_FAMILY (0xff << 8) /* family ID code */
543#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */
544
545#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */
546#define MSP5000_ID (0x50 << 8)
547#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */
548#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */
549#define MSP4200_ID (0x42 << 8)
550#define MSP4000_ID (0x40 << 8)
551#define MSP2XXX_ID (0x20 << 8)
552#define MSPZEUS_ID (0x10 << 8)
553
554#define MSP2004_SUB_ID (0x0 << 16)
555#define MSP2005_SUB_ID (0x1 << 16)
556#define MSP2006_SUB_ID (0x1 << 16)
557#define MSP2007_SUB_ID (0x2 << 16)
558#define MSP2010_SUB_ID (0x3 << 16)
559#define MSP2015_SUB_ID (0x4 << 16)
560#define MSP2020_SUB_ID (0x5 << 16)
561#define MSP2100_SUB_ID (0x6 << 16)
562
563/*
564 ***************************************************************************
565 * RESET defines *
566 ***************************************************************************
567 */
568#define MSP_GR_RST (0x01 << 0) /* Global reset bit */
569#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */
570#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */
571#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */
572/* reserved */
573#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */
574#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */
575#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */
576#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */
577#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */
578#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */
579#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */
580#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */
581#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */
582
583/*
584 ***************************************************************************
585 * UART defines *
586 ***************************************************************************
587 */
588#define MSP_BASE_BAUD 25000000
589#define MSP_UART_REG_LEN 0x20
590
591/*
592 ***************************************************************************
593 * ELB defines *
594 ***************************************************************************
595 */
596#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */
597#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */
598
599/*
600 ***************************************************************************
601 * CIC defines *
602 ***************************************************************************
603 */
604
605/* CIC_EXT_CFG_REG */
606#define EXT_INT_POL(eirq) (1 << (eirq + 8))
607#define EXT_INT_EDGE(eirq) (1 << eirq)
608
609#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))
610#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq))
611#define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq))
612#define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))
613#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI
614#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO
615
616#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
617 ((reg & EXT_INT_EDGE(eirq)) == 0)
618#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))
619#define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))
620#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
621 ((reg & EXT_INT_POL(eirq)) == 0)
622#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI
623#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO
624
625/*
626 ***************************************************************************
627 * Memory Controller defines *
628 ***************************************************************************
629 */
630
631/* Indirect memory controller registers */
632#define DDRC_CFG(n) (n)
633#define DDRC_DEBUG(n) (0x04 + n)
634#define DDRC_CTL(n) (0x40 + n)
635
636/* Macro to perform DDRC indirect write */
637#define DDRC_INDIRECT_WRITE(reg, mask, value) \
638({ \
639 *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
640 *MEM_SS_DATA = (value); \
641 *MEM_SS_WRITE = 1; \
642})
643
644/*
645 ***************************************************************************
646 * SPI/MPI Mode *
647 ***************************************************************************
648 */
649#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */
650#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */
651#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */
652#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */
653
654/*
655 ***************************************************************************
656 * SPI/MPI Control Register *
657 ***************************************************************************
658 */
659#define SPI_MPI_RX_START 0x00000004 /* Start receive command */
660#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */
661#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */
662
663#endif /* !_ASM_MSP_REGS_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
new file mode 100644
index 000000000000..96d4c8ce8c83
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
@@ -0,0 +1,141 @@
1/*
2 * Defines for the MSP interrupt controller.
3 *
4 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
5 * Author: Carsten Langgaard, carstenl@mips.com
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 */
24
25#ifndef _MSP_SLP_INT_H
26#define _MSP_SLP_INT_H
27
28/*
29 * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
30 * hierarchical system. The first level are the direct MIPS interrupts
31 * and are assigned the interrupt range 0-7. The second level is the SLM
32 * interrupt controller and is assigned the range 8-39. The third level
33 * comprises the Peripherial block, the PCI block, the PCI MSI block and
34 * the SLP. The PCI interrupts and the SLP errors are handled by the
35 * relevant subsystems so the core interrupt code needs only concern
36 * itself with the Peripheral block. These are assigned interrupts in
37 * the range 40-71.
38 */
39
40/*
41 * IRQs directly connected to CPU
42 */
43#define MSP_MIPS_INTBASE 0
44#define MSP_INT_SW0 0 /* IRQ for swint0, C_SW0 */
45#define MSP_INT_SW1 1 /* IRQ for swint1, C_SW1 */
46#define MSP_INT_MAC0 2 /* IRQ for MAC 0, C_IRQ0 */
47#define MSP_INT_MAC1 3 /* IRQ for MAC 1, C_IRQ1 */
48#define MSP_INT_C_IRQ2 4 /* Wired off, C_IRQ2 */
49#define MSP_INT_VE 5 /* IRQ for Voice Engine, C_IRQ3 */
50#define MSP_INT_SLP 6 /* IRQ for SLM block, C_IRQ4 */
51#define MSP_INT_TIMER 7 /* IRQ for the MIPS timer, C_IRQ5 */
52
53/*
54 * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
55 * These defines should be tied to the register definition for the SLM
56 * interrupt routine. For now, just use hard-coded values.
57 */
58#define MSP_SLP_INTBASE (MSP_MIPS_INTBASE + 8)
59#define MSP_INT_EXT0 (MSP_SLP_INTBASE + 0)
60 /* External interrupt 0 */
61#define MSP_INT_EXT1 (MSP_SLP_INTBASE + 1)
62 /* External interrupt 1 */
63#define MSP_INT_EXT2 (MSP_SLP_INTBASE + 2)
64 /* External interrupt 2 */
65#define MSP_INT_EXT3 (MSP_SLP_INTBASE + 3)
66 /* External interrupt 3 */
67/* Reserved 4-7 */
68
69/*
70 *************************************************************************
71 * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
72 * Some MSP produces have this interrupt labelled as Voice and some are *
73 * SEC mbox ... *
74 *************************************************************************
75 */
76#define MSP_INT_SLP_VE (MSP_SLP_INTBASE + 8)
77 /* Cascaded IRQ for Voice Engine*/
78#define MSP_INT_SLP_TDM (MSP_SLP_INTBASE + 9)
79 /* TDM interrupt */
80#define MSP_INT_SLP_MAC0 (MSP_SLP_INTBASE + 10)
81 /* Cascaded IRQ for MAC 0 */
82#define MSP_INT_SLP_MAC1 (MSP_SLP_INTBASE + 11)
83 /* Cascaded IRQ for MAC 1 */
84#define MSP_INT_SEC (MSP_SLP_INTBASE + 12)
85 /* IRQ for security engine */
86#define MSP_INT_PER (MSP_SLP_INTBASE + 13)
87 /* Peripheral interrupt */
88#define MSP_INT_TIMER0 (MSP_SLP_INTBASE + 14)
89 /* SLP timer 0 */
90#define MSP_INT_TIMER1 (MSP_SLP_INTBASE + 15)
91 /* SLP timer 1 */
92#define MSP_INT_TIMER2 (MSP_SLP_INTBASE + 16)
93 /* SLP timer 2 */
94#define MSP_INT_SLP_TIMER (MSP_SLP_INTBASE + 17)
95 /* Cascaded MIPS timer */
96#define MSP_INT_BLKCP (MSP_SLP_INTBASE + 18)
97 /* Block Copy */
98#define MSP_INT_UART0 (MSP_SLP_INTBASE + 19)
99 /* UART 0 */
100#define MSP_INT_PCI (MSP_SLP_INTBASE + 20)
101 /* PCI subsystem */
102#define MSP_INT_PCI_DBELL (MSP_SLP_INTBASE + 21)
103 /* PCI doorbell */
104#define MSP_INT_PCI_MSI (MSP_SLP_INTBASE + 22)
105 /* PCI Message Signal */
106#define MSP_INT_PCI_BC0 (MSP_SLP_INTBASE + 23)
107 /* PCI Block Copy 0 */
108#define MSP_INT_PCI_BC1 (MSP_SLP_INTBASE + 24)
109 /* PCI Block Copy 1 */
110#define MSP_INT_SLP_ERR (MSP_SLP_INTBASE + 25)
111 /* SLP error condition */
112#define MSP_INT_MAC2 (MSP_SLP_INTBASE + 26)
113 /* IRQ for MAC2 */
114/* Reserved 26-31 */
115
116/*
117 * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
118 */
119#define MSP_PER_INTBASE (MSP_SLP_INTBASE + 32)
120/* Reserved 0-1 */
121#define MSP_INT_UART1 (MSP_PER_INTBASE + 2)
122 /* UART 1 */
123/* Reserved 3-5 */
124#define MSP_INT_2WIRE (MSP_PER_INTBASE + 6)
125 /* 2-wire */
126#define MSP_INT_TM0 (MSP_PER_INTBASE + 7)
127 /* Peripheral timer block out 0 */
128#define MSP_INT_TM1 (MSP_PER_INTBASE + 8)
129 /* Peripheral timer block out 1 */
130/* Reserved 9 */
131#define MSP_INT_SPRX (MSP_PER_INTBASE + 10)
132 /* SPI RX complete */
133#define MSP_INT_SPTX (MSP_PER_INTBASE + 11)
134 /* SPI TX complete */
135#define MSP_INT_GPIO (MSP_PER_INTBASE + 12)
136 /* GPIO */
137#define MSP_INT_PER_ERR (MSP_PER_INTBASE + 13)
138 /* Peripheral error */
139/* Reserved 14-31 */
140
141#endif /* !_MSP_SLP_INT_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
new file mode 100644
index 000000000000..0bf48fc1892b
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -0,0 +1,28 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
9#define __ASM_MIPS_PMC_SIERRA_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
24 defined(CONFIG_PMC_MSP7120_FPGA)
25#define MIPS34K_MISSED_ITLB_WAR 1
26#endif
27
28#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 15:05:30 -0400