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authorRalf Baechle <ralf@linux-mips.org>2014-11-21 18:16:48 -0500
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 16:46:44 -0500
commit34adb28d500e644cc260da4ceb66ba6dc0beaf93 (patch)
treed47596d498c031e9140f7fca3a5bc8b4a393a08d /arch/mips/include/asm/pgtable-bits.h
parentf98614072c5d43421a2cfa6f9b911a071e6e6d5f (diff)
MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/pgtable-bits.h')
-rw-r--r--arch/mips/include/asm/pgtable-bits.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e747bfa0be7e..29ba35954e2e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -32,7 +32,7 @@
32 * unpredictable things. The code (when it is written) to deal with 32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k. 33 * this problem will be in the update_mmu_cache() code for the r4k.
34 */ 34 */
35#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 35#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
36 36
37/* 37/*
38 * The following bits are directly used by the TLB hardware 38 * The following bits are directly used by the TLB hardware
@@ -172,7 +172,7 @@
172 172
173#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 173#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
174 174
175#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ 175#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
176 176
177#ifndef _PFN_SHIFT 177#ifndef _PFN_SHIFT
178#define _PFN_SHIFT PAGE_SHIFT 178#define _PFN_SHIFT PAGE_SHIFT