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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/netlogic
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/netlogic')
-rw-r--r--arch/mips/include/asm/netlogic/common.h16
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h2
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h48
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h46
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h106
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h160
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlr/fmn.h242
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h88
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h18
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h10
13 files changed, 374 insertions, 374 deletions
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index 42bfd5f1eeec..aef560a51a7e 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -38,11 +38,11 @@
38/* 38/*
39 * Common SMP definitions 39 * Common SMP definitions
40 */ 40 */
41#define RESET_VEC_PHYS 0x1fc00000 41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) 42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
43#define BOOT_THREAD_MODE 0 43#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4 44#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8 45#define BOOT_NMI_HANDLER 8
46 46
47#ifndef __ASSEMBLY__ 47#ifndef __ASSEMBLY__
48#include <linux/cpumask.h> 48#include <linux/cpumask.h>
@@ -80,7 +80,7 @@ extern unsigned int nlm_threads_per_core;
80extern cpumask_t nlm_cpumask; 80extern cpumask_t nlm_cpumask;
81 81
82struct nlm_soc_info { 82struct nlm_soc_info {
83 unsigned long coremask; /* cores enabled on the soc */ 83 unsigned long coremask; /* cores enabled on the soc */
84 unsigned long ebase; 84 unsigned long ebase;
85 uint64_t irqmask; 85 uint64_t irqmask;
86 uint64_t sysbase; /* only for XLP */ 86 uint64_t sysbase; /* only for XLP */
@@ -88,9 +88,9 @@ struct nlm_soc_info {
88 spinlock_t piclock; 88 spinlock_t piclock;
89}; 89};
90 90
91#define nlm_get_node(i) (&nlm_nodes[i]) 91#define nlm_get_node(i) (&nlm_nodes[i])
92#ifdef CONFIG_CPU_XLR 92#ifdef CONFIG_CPU_XLR
93#define nlm_current_node() (&nlm_nodes[0]) 93#define nlm_current_node() (&nlm_nodes[0])
94#else 94#else
95#define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) 95#define nlm_current_node() (&nlm_nodes[nlm_nodeid()])
96#endif 96#endif
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
index 72a0c788b472..419d8aef8569 100644
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -48,7 +48,7 @@
48 * access 64 bit addresses or data. 48 * access 64 bit addresses or data.
49 * 49 *
50 * We need to disable interrupts because we save just the lower 32 bits of 50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while 51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose. 52 * using the upper 32 bits of a register, we lose.
53 */ 53 */
54static inline uint32_t nlm_save_flags_kx(void) 54static inline uint32_t nlm_save_flags_kx(void)
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 32ba6d95d47c..8ffae43107e6 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -49,7 +49,7 @@
49 */ 49 */
50#define write_c0_eimr(val) \ 50#define write_c0_eimr(val) \
51do { \ 51do { \
52 if (sizeof(unsigned long) == 4) { \ 52 if (sizeof(unsigned long) == 4) { \
53 unsigned long __flags; \ 53 unsigned long __flags; \
54 \ 54 \
55 local_irq_save(__flags); \ 55 local_irq_save(__flags); \
@@ -208,7 +208,7 @@ do { \
208 ".set\tmips0\n\t" \ 208 ".set\tmips0\n\t" \
209 : : "Jr" (value)); \ 209 : : "Jr" (value)); \
210 else \ 210 else \
211 __asm__ __volatile__( \ 211 __asm__ __volatile__( \
212 ".set\tmips32\n\t" \ 212 ".set\tmips32\n\t" \
213 "mtc2\t%z0, " #reg ", " #sel "\n\t" \ 213 "mtc2\t%z0, " #reg ", " #sel "\n\t" \
214 ".set\tmips0\n\t" \ 214 ".set\tmips0\n\t" \
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index ca95133f1ad1..790f0f1e55c6 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -178,9 +178,9 @@
178 178
179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
181#define nlm_get_bridge_pcibase(node) \ 181#define nlm_get_bridge_pcibase(node) \
182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
183#define nlm_get_bridge_regbase(node) \ 183#define nlm_get_bridge_regbase(node) \
184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
185 185
186#endif /* __ASSEMBLY__ */ 186#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 2c63f9754640..9fac46fb7913 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -35,12 +35,12 @@
35#ifndef __NLM_HAL_IOMAP_H__ 35#ifndef __NLM_HAL_IOMAP_H__
36#define __NLM_HAL_IOMAP_H__ 36#define __NLM_HAL_IOMAP_H__
37 37
38#define XLP_DEFAULT_IO_BASE 0x18000000 38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE 39#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
40#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 40#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
41 41
42#define NMI_BASE 0xbfc00000 42#define NMI_BASE 0xbfc00000
43#define XLP_IO_CLK 133333333 43#define XLP_IO_CLK 133333333
44 44
45#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ 45#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
46#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) 46#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
@@ -96,8 +96,8 @@
96#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) 96#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
97#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) 97#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
98/* SD flash */ 98/* SD flash */
99#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) 99#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
100#define XLP_IO_MMC_OFFSET(node, slot) \ 100#define XLP_IO_MMC_OFFSET(node, slot) \
101 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 101 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
102 102
103/* PCI config header register id's */ 103/* PCI config header register id's */
@@ -125,26 +125,26 @@
125#define XLP_PCI_SBB_WT_REG 0x3f 125#define XLP_PCI_SBB_WT_REG 0x3f
126 126
127/* PCI IDs for SoC device */ 127/* PCI IDs for SoC device */
128#define PCI_VENDOR_NETLOGIC 0x184e 128#define PCI_VENDOR_NETLOGIC 0x184e
129 129
130#define PCI_DEVICE_ID_NLM_ROOT 0x1001 130#define PCI_DEVICE_ID_NLM_ROOT 0x1001
131#define PCI_DEVICE_ID_NLM_ICI 0x1002 131#define PCI_DEVICE_ID_NLM_ICI 0x1002
132#define PCI_DEVICE_ID_NLM_PIC 0x1003 132#define PCI_DEVICE_ID_NLM_PIC 0x1003
133#define PCI_DEVICE_ID_NLM_PCIE 0x1004 133#define PCI_DEVICE_ID_NLM_PCIE 0x1004
134#define PCI_DEVICE_ID_NLM_EHCI 0x1007 134#define PCI_DEVICE_ID_NLM_EHCI 0x1007
135#define PCI_DEVICE_ID_NLM_OHCI 0x1008 135#define PCI_DEVICE_ID_NLM_OHCI 0x1008
136#define PCI_DEVICE_ID_NLM_NAE 0x1009 136#define PCI_DEVICE_ID_NLM_NAE 0x1009
137#define PCI_DEVICE_ID_NLM_POE 0x100A 137#define PCI_DEVICE_ID_NLM_POE 0x100A
138#define PCI_DEVICE_ID_NLM_FMN 0x100B 138#define PCI_DEVICE_ID_NLM_FMN 0x100B
139#define PCI_DEVICE_ID_NLM_RAID 0x100D 139#define PCI_DEVICE_ID_NLM_RAID 0x100D
140#define PCI_DEVICE_ID_NLM_SAE 0x100D 140#define PCI_DEVICE_ID_NLM_SAE 0x100D
141#define PCI_DEVICE_ID_NLM_RSA 0x100E 141#define PCI_DEVICE_ID_NLM_RSA 0x100E
142#define PCI_DEVICE_ID_NLM_CMP 0x100F 142#define PCI_DEVICE_ID_NLM_CMP 0x100F
143#define PCI_DEVICE_ID_NLM_UART 0x1010 143#define PCI_DEVICE_ID_NLM_UART 0x1010
144#define PCI_DEVICE_ID_NLM_I2C 0x1011 144#define PCI_DEVICE_ID_NLM_I2C 0x1011
145#define PCI_DEVICE_ID_NLM_NOR 0x1015 145#define PCI_DEVICE_ID_NLM_NOR 0x1015
146#define PCI_DEVICE_ID_NLM_NAND 0x1016 146#define PCI_DEVICE_ID_NLM_NAND 0x1016
147#define PCI_DEVICE_ID_NLM_MMC 0x1018 147#define PCI_DEVICE_ID_NLM_MMC 0x1018
148 148
149#ifndef __ASSEMBLY__ 149#ifndef __ASSEMBLY__
150 150
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index 66c323d1bd7d..b559cb9f56ea 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -33,42 +33,42 @@
33 */ 33 */
34 34
35#ifndef __NLM_HAL_PCIBUS_H__ 35#ifndef __NLM_HAL_PCIBUS_H__
36#define __NLM_HAL_PCIBUS_H__ 36#define __NLM_HAL_PCIBUS_H__
37 37
38/* PCIE Memory and IO regions */ 38/* PCIE Memory and IO regions */
39#define PCIE_MEM_BASE 0xd0000000ULL 39#define PCIE_MEM_BASE 0xd0000000ULL
40#define PCIE_MEM_LIMIT 0xdfffffffULL 40#define PCIE_MEM_LIMIT 0xdfffffffULL
41#define PCIE_IO_BASE 0x14000000ULL 41#define PCIE_IO_BASE 0x14000000ULL
42#define PCIE_IO_LIMIT 0x15ffffffULL 42#define PCIE_IO_LIMIT 0x15ffffffULL
43 43
44#define PCIE_BRIDGE_CMD 0x1 44#define PCIE_BRIDGE_CMD 0x1
45#define PCIE_BRIDGE_MSI_CAP 0x14 45#define PCIE_BRIDGE_MSI_CAP 0x14
46#define PCIE_BRIDGE_MSI_ADDRL 0x15 46#define PCIE_BRIDGE_MSI_ADDRL 0x15
47#define PCIE_BRIDGE_MSI_ADDRH 0x16 47#define PCIE_BRIDGE_MSI_ADDRH 0x16
48#define PCIE_BRIDGE_MSI_DATA 0x17 48#define PCIE_BRIDGE_MSI_DATA 0x17
49 49
50/* XLP Global PCIE configuration space registers */ 50/* XLP Global PCIE configuration space registers */
51#define PCIE_BYTE_SWAP_MEM_BASE 0x247 51#define PCIE_BYTE_SWAP_MEM_BASE 0x247
52#define PCIE_BYTE_SWAP_MEM_LIM 0x248 52#define PCIE_BYTE_SWAP_MEM_LIM 0x248
53#define PCIE_BYTE_SWAP_IO_BASE 0x249 53#define PCIE_BYTE_SWAP_IO_BASE 0x249
54#define PCIE_BYTE_SWAP_IO_LIM 0x24A 54#define PCIE_BYTE_SWAP_IO_LIM 0x24A
55#define PCIE_MSI_STATUS 0x25A 55#define PCIE_MSI_STATUS 0x25A
56#define PCIE_MSI_EN 0x25B 56#define PCIE_MSI_EN 0x25B
57#define PCIE_INT_EN0 0x261 57#define PCIE_INT_EN0 0x261
58 58
59/* PCIE_MSI_EN */ 59/* PCIE_MSI_EN */
60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF 60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
61 61
62/* PCIE_INT_EN0 */ 62/* PCIE_INT_EN0 */
63#define PCIE_MSI_INT_EN (1 << 9) 63#define PCIE_MSI_INT_EN (1 << 9)
64 64
65#ifndef __ASSEMBLY__ 65#ifndef __ASSEMBLY__
66 66
67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69#define nlm_get_pcie_base(node, inst) \ 69#define nlm_get_pcie_base(node, inst) \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) 70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
71#define nlm_get_pcie_regbase(node, inst) \ 71#define nlm_get_pcie_regbase(node, inst) \
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) 72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
73 73
74int xlp_pcie_link_irt(int link); 74int xlp_pcie_link_irt(int link);
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index b2e53a5383ab..46ace0ca26d8 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -36,7 +36,7 @@
36#define _NLM_HAL_PIC_H 36#define _NLM_HAL_PIC_H
37 37
38/* PIC Specific registers */ 38/* PIC Specific registers */
39#define PIC_CTRL 0x00 39#define PIC_CTRL 0x00
40 40
41/* PIC control register defines */ 41/* PIC control register defines */
42#define PIC_CTRL_ITV 32 /* interrupt timeout value */ 42#define PIC_CTRL_ITV 32 /* interrupt timeout value */
@@ -71,41 +71,41 @@
71#define PIC_IRT_DB 16 /* Destination base */ 71#define PIC_IRT_DB 16 /* Destination base */
72#define PIC_IRT_DTE 0 /* Destination thread enables */ 72#define PIC_IRT_DTE 0 /* Destination thread enables */
73 73
74#define PIC_BYTESWAP 0x02 74#define PIC_BYTESWAP 0x02
75#define PIC_STATUS 0x04 75#define PIC_STATUS 0x04
76#define PIC_INTR_TIMEOUT 0x06 76#define PIC_INTR_TIMEOUT 0x06
77#define PIC_ICI0_INTR_TIMEOUT 0x08 77#define PIC_ICI0_INTR_TIMEOUT 0x08
78#define PIC_ICI1_INTR_TIMEOUT 0x0a 78#define PIC_ICI1_INTR_TIMEOUT 0x0a
79#define PIC_ICI2_INTR_TIMEOUT 0x0c 79#define PIC_ICI2_INTR_TIMEOUT 0x0c
80#define PIC_IPI_CTL 0x0e 80#define PIC_IPI_CTL 0x0e
81#define PIC_INT_ACK 0x10 81#define PIC_INT_ACK 0x10
82#define PIC_INT_PENDING0 0x12 82#define PIC_INT_PENDING0 0x12
83#define PIC_INT_PENDING1 0x14 83#define PIC_INT_PENDING1 0x14
84#define PIC_INT_PENDING2 0x16 84#define PIC_INT_PENDING2 0x16
85 85
86#define PIC_WDOG0_MAXVAL 0x18 86#define PIC_WDOG0_MAXVAL 0x18
87#define PIC_WDOG0_COUNT 0x1a 87#define PIC_WDOG0_COUNT 0x1a
88#define PIC_WDOG0_ENABLE0 0x1c 88#define PIC_WDOG0_ENABLE0 0x1c
89#define PIC_WDOG0_ENABLE1 0x1e 89#define PIC_WDOG0_ENABLE1 0x1e
90#define PIC_WDOG0_BEATCMD 0x20 90#define PIC_WDOG0_BEATCMD 0x20
91#define PIC_WDOG0_BEAT0 0x22 91#define PIC_WDOG0_BEAT0 0x22
92#define PIC_WDOG0_BEAT1 0x24 92#define PIC_WDOG0_BEAT1 0x24
93 93
94#define PIC_WDOG1_MAXVAL 0x26 94#define PIC_WDOG1_MAXVAL 0x26
95#define PIC_WDOG1_COUNT 0x28 95#define PIC_WDOG1_COUNT 0x28
96#define PIC_WDOG1_ENABLE0 0x2a 96#define PIC_WDOG1_ENABLE0 0x2a
97#define PIC_WDOG1_ENABLE1 0x2c 97#define PIC_WDOG1_ENABLE1 0x2c
98#define PIC_WDOG1_BEATCMD 0x2e 98#define PIC_WDOG1_BEATCMD 0x2e
99#define PIC_WDOG1_BEAT0 0x30 99#define PIC_WDOG1_BEAT0 0x30
100#define PIC_WDOG1_BEAT1 0x32 100#define PIC_WDOG1_BEAT1 0x32
101 101
102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) 102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) 103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) 104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) 105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) 106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) 107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) 108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109 109
110#define PIC_TIMER0_MAXVAL 0x34 110#define PIC_TIMER0_MAXVAL 0x34
111#define PIC_TIMER1_MAXVAL 0x36 111#define PIC_TIMER1_MAXVAL 0x36
@@ -127,28 +127,28 @@
127#define PIC_TIMER7_COUNT 0x52 127#define PIC_TIMER7_COUNT 0x52
128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) 128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129 129
130#define PIC_ITE0_N0_N1 0x54 130#define PIC_ITE0_N0_N1 0x54
131#define PIC_ITE1_N0_N1 0x58 131#define PIC_ITE1_N0_N1 0x58
132#define PIC_ITE2_N0_N1 0x5c 132#define PIC_ITE2_N0_N1 0x5c
133#define PIC_ITE3_N0_N1 0x60 133#define PIC_ITE3_N0_N1 0x60
134#define PIC_ITE4_N0_N1 0x64 134#define PIC_ITE4_N0_N1 0x64
135#define PIC_ITE5_N0_N1 0x68 135#define PIC_ITE5_N0_N1 0x68
136#define PIC_ITE6_N0_N1 0x6c 136#define PIC_ITE6_N0_N1 0x6c
137#define PIC_ITE7_N0_N1 0x70 137#define PIC_ITE7_N0_N1 0x70
138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) 138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139 139
140#define PIC_ITE0_N2_N3 0x56 140#define PIC_ITE0_N2_N3 0x56
141#define PIC_ITE1_N2_N3 0x5a 141#define PIC_ITE1_N2_N3 0x5a
142#define PIC_ITE2_N2_N3 0x5e 142#define PIC_ITE2_N2_N3 0x5e
143#define PIC_ITE3_N2_N3 0x62 143#define PIC_ITE3_N2_N3 0x62
144#define PIC_ITE4_N2_N3 0x66 144#define PIC_ITE4_N2_N3 0x66
145#define PIC_ITE5_N2_N3 0x6a 145#define PIC_ITE5_N2_N3 0x6a
146#define PIC_ITE6_N2_N3 0x6e 146#define PIC_ITE6_N2_N3 0x6e
147#define PIC_ITE7_N2_N3 0x72 147#define PIC_ITE7_N2_N3 0x72
148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) 148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149 149
150#define PIC_IRT0 0x74 150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152 152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
154 154
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 258e8cc00e99..470e52bfc061 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -40,89 +40,89 @@
40* @author Netlogic Microsystems 40* @author Netlogic Microsystems
41* @brief HAL for System configuration registers 41* @brief HAL for System configuration registers
42*/ 42*/
43#define SYS_CHIP_RESET 0x00 43#define SYS_CHIP_RESET 0x00
44#define SYS_POWER_ON_RESET_CFG 0x01 44#define SYS_POWER_ON_RESET_CFG 0x01
45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
48#define SYS_EFUSE_DEVICE_CFG3 0x05 48#define SYS_EFUSE_DEVICE_CFG3 0x05
49#define SYS_EFUSE_DEVICE_CFG4 0x06 49#define SYS_EFUSE_DEVICE_CFG4 0x06
50#define SYS_EFUSE_DEVICE_CFG5 0x07 50#define SYS_EFUSE_DEVICE_CFG5 0x07
51#define SYS_EFUSE_DEVICE_CFG6 0x08 51#define SYS_EFUSE_DEVICE_CFG6 0x08
52#define SYS_EFUSE_DEVICE_CFG7 0x09 52#define SYS_EFUSE_DEVICE_CFG7 0x09
53#define SYS_PLL_CTRL 0x0a 53#define SYS_PLL_CTRL 0x0a
54#define SYS_CPU_RESET 0x0b 54#define SYS_CPU_RESET 0x0b
55#define SYS_CPU_NONCOHERENT_MODE 0x0d 55#define SYS_CPU_NONCOHERENT_MODE 0x0d
56#define SYS_CORE_DFS_DIS_CTRL 0x0e 56#define SYS_CORE_DFS_DIS_CTRL 0x0e
57#define SYS_CORE_DFS_RST_CTRL 0x0f 57#define SYS_CORE_DFS_RST_CTRL 0x0f
58#define SYS_CORE_DFS_BYP_CTRL 0x10 58#define SYS_CORE_DFS_BYP_CTRL 0x10
59#define SYS_CORE_DFS_PHA_CTRL 0x11 59#define SYS_CORE_DFS_PHA_CTRL 0x11
60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
62#define SYS_CORE_DFS_DIV_VALUE 0x14 62#define SYS_CORE_DFS_DIV_VALUE 0x14
63#define SYS_RESET 0x15 63#define SYS_RESET 0x15
64#define SYS_DFS_DIS_CTRL 0x16 64#define SYS_DFS_DIS_CTRL 0x16
65#define SYS_DFS_RST_CTRL 0x17 65#define SYS_DFS_RST_CTRL 0x17
66#define SYS_DFS_BYP_CTRL 0x18 66#define SYS_DFS_BYP_CTRL 0x18
67#define SYS_DFS_DIV_INC_CTRL 0x19 67#define SYS_DFS_DIV_INC_CTRL 0x19
68#define SYS_DFS_DIV_DEC_CTRL 0x1a 68#define SYS_DFS_DIV_DEC_CTRL 0x1a
69#define SYS_DFS_DIV_VALUE0 0x1b 69#define SYS_DFS_DIV_VALUE0 0x1b
70#define SYS_DFS_DIV_VALUE1 0x1c 70#define SYS_DFS_DIV_VALUE1 0x1c
71#define SYS_SENSE_AMP_DLY 0x1d 71#define SYS_SENSE_AMP_DLY 0x1d
72#define SYS_SOC_SENSE_AMP_DLY 0x1e 72#define SYS_SOC_SENSE_AMP_DLY 0x1e
73#define SYS_CTRL0 0x1f 73#define SYS_CTRL0 0x1f
74#define SYS_CTRL1 0x20 74#define SYS_CTRL1 0x20
75#define SYS_TIMEOUT_BS1 0x21 75#define SYS_TIMEOUT_BS1 0x21
76#define SYS_BYTE_SWAP 0x22 76#define SYS_BYTE_SWAP 0x22
77#define SYS_VRM_VID 0x23 77#define SYS_VRM_VID 0x23
78#define SYS_PWR_RAM_CMD 0x24 78#define SYS_PWR_RAM_CMD 0x24
79#define SYS_PWR_RAM_ADDR 0x25 79#define SYS_PWR_RAM_ADDR 0x25
80#define SYS_PWR_RAM_DATA0 0x26 80#define SYS_PWR_RAM_DATA0 0x26
81#define SYS_PWR_RAM_DATA1 0x27 81#define SYS_PWR_RAM_DATA1 0x27
82#define SYS_PWR_RAM_DATA2 0x28 82#define SYS_PWR_RAM_DATA2 0x28
83#define SYS_PWR_UCODE 0x29 83#define SYS_PWR_UCODE 0x29
84#define SYS_CPU0_PWR_STATUS 0x2a 84#define SYS_CPU0_PWR_STATUS 0x2a
85#define SYS_CPU1_PWR_STATUS 0x2b 85#define SYS_CPU1_PWR_STATUS 0x2b
86#define SYS_CPU2_PWR_STATUS 0x2c 86#define SYS_CPU2_PWR_STATUS 0x2c
87#define SYS_CPU3_PWR_STATUS 0x2d 87#define SYS_CPU3_PWR_STATUS 0x2d
88#define SYS_CPU4_PWR_STATUS 0x2e 88#define SYS_CPU4_PWR_STATUS 0x2e
89#define SYS_CPU5_PWR_STATUS 0x2f 89#define SYS_CPU5_PWR_STATUS 0x2f
90#define SYS_CPU6_PWR_STATUS 0x30 90#define SYS_CPU6_PWR_STATUS 0x30
91#define SYS_CPU7_PWR_STATUS 0x31 91#define SYS_CPU7_PWR_STATUS 0x31
92#define SYS_STATUS 0x32 92#define SYS_STATUS 0x32
93#define SYS_INT_POL 0x33 93#define SYS_INT_POL 0x33
94#define SYS_INT_TYPE 0x34 94#define SYS_INT_TYPE 0x34
95#define SYS_INT_STATUS 0x35 95#define SYS_INT_STATUS 0x35
96#define SYS_INT_MASK0 0x36 96#define SYS_INT_MASK0 0x36
97#define SYS_INT_MASK1 0x37 97#define SYS_INT_MASK1 0x37
98#define SYS_UCO_S_ECC 0x38 98#define SYS_UCO_S_ECC 0x38
99#define SYS_UCO_M_ECC 0x39 99#define SYS_UCO_M_ECC 0x39
100#define SYS_UCO_ADDR 0x3a 100#define SYS_UCO_ADDR 0x3a
101#define SYS_UCO_INSTR 0x3b 101#define SYS_UCO_INSTR 0x3b
102#define SYS_MEM_BIST0 0x3c 102#define SYS_MEM_BIST0 0x3c
103#define SYS_MEM_BIST1 0x3d 103#define SYS_MEM_BIST1 0x3d
104#define SYS_MEM_BIST2 0x3e 104#define SYS_MEM_BIST2 0x3e
105#define SYS_MEM_BIST3 0x3f 105#define SYS_MEM_BIST3 0x3f
106#define SYS_MEM_BIST4 0x40 106#define SYS_MEM_BIST4 0x40
107#define SYS_MEM_BIST5 0x41 107#define SYS_MEM_BIST5 0x41
108#define SYS_MEM_BIST6 0x42 108#define SYS_MEM_BIST6 0x42
109#define SYS_MEM_BIST7 0x43 109#define SYS_MEM_BIST7 0x43
110#define SYS_MEM_BIST8 0x44 110#define SYS_MEM_BIST8 0x44
111#define SYS_MEM_BIST9 0x45 111#define SYS_MEM_BIST9 0x45
112#define SYS_MEM_BIST10 0x46 112#define SYS_MEM_BIST10 0x46
113#define SYS_MEM_BIST11 0x47 113#define SYS_MEM_BIST11 0x47
114#define SYS_MEM_BIST12 0x48 114#define SYS_MEM_BIST12 0x48
115#define SYS_SCRTCH0 0x49 115#define SYS_SCRTCH0 0x49
116#define SYS_SCRTCH1 0x4a 116#define SYS_SCRTCH1 0x4a
117#define SYS_SCRTCH2 0x4b 117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c 118#define SYS_SCRTCH3 0x4c
119 119
120#ifndef __ASSEMBLY__ 120#ifndef __ASSEMBLY__
121 121
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126 126
127#endif 127#endif
128#endif 128#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 6a7046ca094d..86d16e1e6072 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -91,8 +91,8 @@
91 91
92#if !defined(LOCORE) && !defined(__ASSEMBLY__) 92#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93 93
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) 94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) 95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \ 96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) 97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \ 98#define nlm_get_uart_regbase(node, inst) \
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
index 68d5167c86bb..2a78929cef73 100644
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -38,108 +38,108 @@
38#include <asm/netlogic/mips-extns.h> /* for COP2 access */ 38#include <asm/netlogic/mips-extns.h> /* for COP2 access */
39 39
40/* Station IDs */ 40/* Station IDs */
41#define FMN_STNID_CPU0 0x00 41#define FMN_STNID_CPU0 0x00
42#define FMN_STNID_CPU1 0x08 42#define FMN_STNID_CPU1 0x08
43#define FMN_STNID_CPU2 0x10 43#define FMN_STNID_CPU2 0x10
44#define FMN_STNID_CPU3 0x18 44#define FMN_STNID_CPU3 0x18
45#define FMN_STNID_CPU4 0x20 45#define FMN_STNID_CPU4 0x20
46#define FMN_STNID_CPU5 0x28 46#define FMN_STNID_CPU5 0x28
47#define FMN_STNID_CPU6 0x30 47#define FMN_STNID_CPU6 0x30
48#define FMN_STNID_CPU7 0x38 48#define FMN_STNID_CPU7 0x38
49 49
50#define FMN_STNID_XGS0_TX 64 50#define FMN_STNID_XGS0_TX 64
51#define FMN_STNID_XMAC0_00_TX 64 51#define FMN_STNID_XMAC0_00_TX 64
52#define FMN_STNID_XMAC0_01_TX 65 52#define FMN_STNID_XMAC0_01_TX 65
53#define FMN_STNID_XMAC0_02_TX 66 53#define FMN_STNID_XMAC0_02_TX 66
54#define FMN_STNID_XMAC0_03_TX 67 54#define FMN_STNID_XMAC0_03_TX 67
55#define FMN_STNID_XMAC0_04_TX 68 55#define FMN_STNID_XMAC0_04_TX 68
56#define FMN_STNID_XMAC0_05_TX 69 56#define FMN_STNID_XMAC0_05_TX 69
57#define FMN_STNID_XMAC0_06_TX 70 57#define FMN_STNID_XMAC0_06_TX 70
58#define FMN_STNID_XMAC0_07_TX 71 58#define FMN_STNID_XMAC0_07_TX 71
59#define FMN_STNID_XMAC0_08_TX 72 59#define FMN_STNID_XMAC0_08_TX 72
60#define FMN_STNID_XMAC0_09_TX 73 60#define FMN_STNID_XMAC0_09_TX 73
61#define FMN_STNID_XMAC0_10_TX 74 61#define FMN_STNID_XMAC0_10_TX 74
62#define FMN_STNID_XMAC0_11_TX 75 62#define FMN_STNID_XMAC0_11_TX 75
63#define FMN_STNID_XMAC0_12_TX 76 63#define FMN_STNID_XMAC0_12_TX 76
64#define FMN_STNID_XMAC0_13_TX 77 64#define FMN_STNID_XMAC0_13_TX 77
65#define FMN_STNID_XMAC0_14_TX 78 65#define FMN_STNID_XMAC0_14_TX 78
66#define FMN_STNID_XMAC0_15_TX 79 66#define FMN_STNID_XMAC0_15_TX 79
67 67
68#define FMN_STNID_XGS1_TX 80 68#define FMN_STNID_XGS1_TX 80
69#define FMN_STNID_XMAC1_00_TX 80 69#define FMN_STNID_XMAC1_00_TX 80
70#define FMN_STNID_XMAC1_01_TX 81 70#define FMN_STNID_XMAC1_01_TX 81
71#define FMN_STNID_XMAC1_02_TX 82 71#define FMN_STNID_XMAC1_02_TX 82
72#define FMN_STNID_XMAC1_03_TX 83 72#define FMN_STNID_XMAC1_03_TX 83
73#define FMN_STNID_XMAC1_04_TX 84 73#define FMN_STNID_XMAC1_04_TX 84
74#define FMN_STNID_XMAC1_05_TX 85 74#define FMN_STNID_XMAC1_05_TX 85
75#define FMN_STNID_XMAC1_06_TX 86 75#define FMN_STNID_XMAC1_06_TX 86
76#define FMN_STNID_XMAC1_07_TX 87 76#define FMN_STNID_XMAC1_07_TX 87
77#define FMN_STNID_XMAC1_08_TX 88 77#define FMN_STNID_XMAC1_08_TX 88
78#define FMN_STNID_XMAC1_09_TX 89 78#define FMN_STNID_XMAC1_09_TX 89
79#define FMN_STNID_XMAC1_10_TX 90 79#define FMN_STNID_XMAC1_10_TX 90
80#define FMN_STNID_XMAC1_11_TX 91 80#define FMN_STNID_XMAC1_11_TX 91
81#define FMN_STNID_XMAC1_12_TX 92 81#define FMN_STNID_XMAC1_12_TX 92
82#define FMN_STNID_XMAC1_13_TX 93 82#define FMN_STNID_XMAC1_13_TX 93
83#define FMN_STNID_XMAC1_14_TX 94 83#define FMN_STNID_XMAC1_14_TX 94
84#define FMN_STNID_XMAC1_15_TX 95 84#define FMN_STNID_XMAC1_15_TX 95
85 85
86#define FMN_STNID_GMAC 96 86#define FMN_STNID_GMAC 96
87#define FMN_STNID_GMACJFR_0 96 87#define FMN_STNID_GMACJFR_0 96
88#define FMN_STNID_GMACRFR_0 97 88#define FMN_STNID_GMACRFR_0 97
89#define FMN_STNID_GMACTX0 98 89#define FMN_STNID_GMACTX0 98
90#define FMN_STNID_GMACTX1 99 90#define FMN_STNID_GMACTX1 99
91#define FMN_STNID_GMACTX2 100 91#define FMN_STNID_GMACTX2 100
92#define FMN_STNID_GMACTX3 101 92#define FMN_STNID_GMACTX3 101
93#define FMN_STNID_GMACJFR_1 102 93#define FMN_STNID_GMACJFR_1 102
94#define FMN_STNID_GMACRFR_1 103 94#define FMN_STNID_GMACRFR_1 103
95 95
96#define FMN_STNID_DMA 104 96#define FMN_STNID_DMA 104
97#define FMN_STNID_DMA_0 104 97#define FMN_STNID_DMA_0 104
98#define FMN_STNID_DMA_1 105 98#define FMN_STNID_DMA_1 105
99#define FMN_STNID_DMA_2 106 99#define FMN_STNID_DMA_2 106
100#define FMN_STNID_DMA_3 107 100#define FMN_STNID_DMA_3 107
101 101
102#define FMN_STNID_XGS0FR 112 102#define FMN_STNID_XGS0FR 112
103#define FMN_STNID_XMAC0JFR 112 103#define FMN_STNID_XMAC0JFR 112
104#define FMN_STNID_XMAC0RFR 113 104#define FMN_STNID_XMAC0RFR 113
105 105
106#define FMN_STNID_XGS1FR 114 106#define FMN_STNID_XGS1FR 114
107#define FMN_STNID_XMAC1JFR 114 107#define FMN_STNID_XMAC1JFR 114
108#define FMN_STNID_XMAC1RFR 115 108#define FMN_STNID_XMAC1RFR 115
109#define FMN_STNID_SEC 120 109#define FMN_STNID_SEC 120
110#define FMN_STNID_SEC0 120 110#define FMN_STNID_SEC0 120
111#define FMN_STNID_SEC1 121 111#define FMN_STNID_SEC1 121
112#define FMN_STNID_SEC2 122 112#define FMN_STNID_SEC2 122
113#define FMN_STNID_SEC3 123 113#define FMN_STNID_SEC3 123
114#define FMN_STNID_PK0 124 114#define FMN_STNID_PK0 124
115#define FMN_STNID_SEC_RSA 124 115#define FMN_STNID_SEC_RSA 124
116#define FMN_STNID_SEC_RSVD0 125 116#define FMN_STNID_SEC_RSVD0 125
117#define FMN_STNID_SEC_RSVD1 126 117#define FMN_STNID_SEC_RSVD1 126
118#define FMN_STNID_SEC_RSVD2 127 118#define FMN_STNID_SEC_RSVD2 127
119 119
120#define FMN_STNID_GMAC1 80 120#define FMN_STNID_GMAC1 80
121#define FMN_STNID_GMAC1_FR_0 81 121#define FMN_STNID_GMAC1_FR_0 81
122#define FMN_STNID_GMAC1_TX0 82 122#define FMN_STNID_GMAC1_TX0 82
123#define FMN_STNID_GMAC1_TX1 83 123#define FMN_STNID_GMAC1_TX1 83
124#define FMN_STNID_GMAC1_TX2 84 124#define FMN_STNID_GMAC1_TX2 84
125#define FMN_STNID_GMAC1_TX3 85 125#define FMN_STNID_GMAC1_TX3 85
126#define FMN_STNID_GMAC1_FR_1 87 126#define FMN_STNID_GMAC1_FR_1 87
127#define FMN_STNID_GMAC0 96 127#define FMN_STNID_GMAC0 96
128#define FMN_STNID_GMAC0_FR_0 97 128#define FMN_STNID_GMAC0_FR_0 97
129#define FMN_STNID_GMAC0_TX0 98 129#define FMN_STNID_GMAC0_TX0 98
130#define FMN_STNID_GMAC0_TX1 99 130#define FMN_STNID_GMAC0_TX1 99
131#define FMN_STNID_GMAC0_TX2 100 131#define FMN_STNID_GMAC0_TX2 100
132#define FMN_STNID_GMAC0_TX3 101 132#define FMN_STNID_GMAC0_TX3 101
133#define FMN_STNID_GMAC0_FR_1 103 133#define FMN_STNID_GMAC0_FR_1 103
134#define FMN_STNID_CMP_0 108 134#define FMN_STNID_CMP_0 108
135#define FMN_STNID_CMP_1 109 135#define FMN_STNID_CMP_1 109
136#define FMN_STNID_CMP_2 110 136#define FMN_STNID_CMP_2 110
137#define FMN_STNID_CMP_3 111 137#define FMN_STNID_CMP_3 111
138#define FMN_STNID_PCIE_0 116 138#define FMN_STNID_PCIE_0 116
139#define FMN_STNID_PCIE_1 117 139#define FMN_STNID_PCIE_1 117
140#define FMN_STNID_PCIE_2 118 140#define FMN_STNID_PCIE_2 118
141#define FMN_STNID_PCIE_3 119 141#define FMN_STNID_PCIE_3 119
142#define FMN_STNID_XLS_PK0 121 142#define FMN_STNID_XLS_PK0 121
143 143
144#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s) 144#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
145#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s) 145#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
@@ -175,25 +175,25 @@
175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) 175#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) 176#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
177 177
178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) 178#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) 179#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) 180#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
181#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b) 181#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
182#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v) 182#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
183 183
184#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0) 184#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
185#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1) 185#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
186#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2) 186#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
187#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3) 187#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
188 188
189#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v) 189#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
190#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v) 190#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
191#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v) 191#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
192#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v) 192#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
193 193
194#define FMN_STN_RX_QSIZE 256 194#define FMN_STN_RX_QSIZE 256
195#define FMN_NSTATIONS 128 195#define FMN_NSTATIONS 128
196#define FMN_CORE_NBUCKETS 8 196#define FMN_CORE_NBUCKETS 8
197 197
198static inline void nlm_msgsnd(unsigned int stid) 198static inline void nlm_msgsnd(unsigned int stid)
199{ 199{
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e768f032e83..ff4533d6ee64 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -35,66 +35,66 @@
35#ifndef _ASM_NLM_IOMAP_H 35#ifndef _ASM_NLM_IOMAP_H
36#define _ASM_NLM_IOMAP_H 36#define _ASM_NLM_IOMAP_H
37 37
38#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) 38#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
39#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 39#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
40#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 40#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
41#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 41#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
42#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 42#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
43#define NETLOGIC_IO_PIC_OFFSET 0x08000 43#define NETLOGIC_IO_PIC_OFFSET 0x08000
44#define NETLOGIC_IO_UART_0_OFFSET 0x14000 44#define NETLOGIC_IO_UART_0_OFFSET 0x14000
45#define NETLOGIC_IO_UART_1_OFFSET 0x15100 45#define NETLOGIC_IO_UART_1_OFFSET 0x15100
46 46
47#define NETLOGIC_IO_SIZE 0x1000 47#define NETLOGIC_IO_SIZE 0x1000
48 48
49#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 49#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
50 50
51#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 51#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000
52#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 52#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000
53 53
54#define NETLOGIC_IO_SRAM_OFFSET 0x07000 54#define NETLOGIC_IO_SRAM_OFFSET 0x07000
55 55
56#define NETLOGIC_IO_PCIX_OFFSET 0x09000 56#define NETLOGIC_IO_PCIX_OFFSET 0x09000
57#define NETLOGIC_IO_HT_OFFSET 0x0A000 57#define NETLOGIC_IO_HT_OFFSET 0x0A000
58 58
59#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 59#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000
60 60
61#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 61#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000
62#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 62#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000
63#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 63#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000
64#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 64#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000
65 65
66/* XLS devices */ 66/* XLS devices */
67#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 67#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000
68#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 68#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000
69#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 69#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000
70#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 70#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000
71 71
72#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 72#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000
73#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 73#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000
74#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 74#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000
75#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 75#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000
76 76
77#define NETLOGIC_IO_USB_0_OFFSET 0x24000 77#define NETLOGIC_IO_USB_0_OFFSET 0x24000
78#define NETLOGIC_IO_USB_1_OFFSET 0x25000 78#define NETLOGIC_IO_USB_1_OFFSET 0x25000
79 79
80#define NETLOGIC_IO_COMP_OFFSET 0x1D000 80#define NETLOGIC_IO_COMP_OFFSET 0x1D000
81/* end XLS devices */ 81/* end XLS devices */
82 82
83/* XLR devices */ 83/* XLR devices */
84#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 84#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000
85#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 85#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000
86#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 86#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000
87#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 87#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000
88/* end XLR devices */ 88/* end XLR devices */
89 89
90#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 90#define NETLOGIC_IO_I2C_0_OFFSET 0x16000
91#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 91#define NETLOGIC_IO_I2C_1_OFFSET 0x17000
92 92
93#define NETLOGIC_IO_GPIO_OFFSET 0x18000 93#define NETLOGIC_IO_GPIO_OFFSET 0x18000
94#define NETLOGIC_IO_FLASH_OFFSET 0x19000 94#define NETLOGIC_IO_FLASH_OFFSET 0x19000
95#define NETLOGIC_IO_TB_OFFSET 0x1C000 95#define NETLOGIC_IO_TB_OFFSET 0x1C000
96 96
97#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) 97#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000)
98 98
99/* 99/*
100 * Base Address (Virtual) of the PCI Config address space 100 * Base Address (Virtual) of the PCI Config address space
@@ -102,8 +102,8 @@
102 * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes 102 * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
103 * ie 1<<24 = 16M 103 * ie 1<<24 = 16M
104 */ 104 */
105#define DEFAULT_PCI_CONFIG_BASE 0x18000000 105#define DEFAULT_PCI_CONFIG_BASE 0x18000000
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108 108
109#endif 109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
index 7e39d40be4f5..c95d18edf12f 100644
--- a/arch/mips/include/asm/netlogic/xlr/msidef.h
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -45,21 +45,21 @@
45 */ 45 */
46 46
47#define MSI_DATA_VECTOR_SHIFT 0 47#define MSI_DATA_VECTOR_SHIFT 0
48#define MSI_DATA_VECTOR_MASK 0x000000ff 48#define MSI_DATA_VECTOR_MASK 0x000000ff
49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \ 49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
50 MSI_DATA_VECTOR_MASK) 50 MSI_DATA_VECTOR_MASK)
51 51
52#define MSI_DATA_DELIVERY_MODE_SHIFT 8 52#define MSI_DATA_DELIVERY_MODE_SHIFT 8
53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) 53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) 54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
55 55
56#define MSI_DATA_LEVEL_SHIFT 14 56#define MSI_DATA_LEVEL_SHIFT 14
57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) 57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) 58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
59 59
60#define MSI_DATA_TRIGGER_SHIFT 15 60#define MSI_DATA_TRIGGER_SHIFT 15
61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) 61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) 62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
63 63
64/* 64/*
65 * Shift/mask fields for msi address 65 * Shift/mask fields for msi address
@@ -69,16 +69,16 @@
69#define MSI_ADDR_BASE_LO 0xfee00000 69#define MSI_ADDR_BASE_LO 0xfee00000
70 70
71#define MSI_ADDR_DEST_MODE_SHIFT 2 71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) 72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) 73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
74 74
75#define MSI_ADDR_REDIRECTION_SHIFT 3 75#define MSI_ADDR_REDIRECTION_SHIFT 3
76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) 76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) 77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
78 78
79#define MSI_ADDR_DEST_ID_SHIFT 12 79#define MSI_ADDR_DEST_ID_SHIFT 12
80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ 81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
82 MSI_ADDR_DEST_ID_MASK) 82 MSI_ADDR_DEST_ID_MASK)
83 83
84#endif /* ASM_RMI_MSIDEF_H */ 84#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 9a691b1f91ba..2f549453585e 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -116,7 +116,7 @@
116#define PIC_TIMER_COUNT_0_BASE 0x120 116#define PIC_TIMER_COUNT_0_BASE 0x120
117#define PIC_TIMER_COUNT_1_BASE 0x130 117#define PIC_TIMER_COUNT_1_BASE 0x130
118 118
119#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) 119#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
120#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) 120#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
121 121
122#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) 122#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
@@ -130,9 +130,9 @@
130 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like 130 * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
131 * count/compare and FMN 131 * count/compare and FMN
132 */ 132 */
133#define PIC_IRQ_BASE 8 133#define PIC_IRQ_BASE 8
134#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) 134#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
135#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) 135#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
136 136
137#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE 137#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
138#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) 138#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
@@ -168,7 +168,7 @@
168#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) 168#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
169#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) 169#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
170#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) 170#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
171#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) 171#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
172/* XLS defines */ 172/* XLS defines */
173#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) 173#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
174#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) 174#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 09:31:52 -0400