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authorStefan Richter <stefanr@s5r6.in-berlin.de>2010-02-14 12:49:18 -0500
committerStefan Richter <stefanr@s5r6.in-berlin.de>2010-02-20 16:33:14 -0500
commit168cf9af699e87d5a6f44b684583714ecabb8e71 (patch)
tree2f491d28a4a129caf7c2be306aec33c437a5cb30 /arch/mips/include/asm/mmu.h
parent4a9bde9b8ab55a2bb51b57cad215a97bcf80bae2 (diff)
firewire: remove incomplete Bus_Time CSR support
The current implementation of Bus_Time read access was buggy since it did not ensure that Bus_Time.second_count_hi and second_count_lo came from the same 128 seconds period. Reported-by: HÃ¥kan Johansson <f96hajo@chalmers.se> Instead of a fix, remove Bus_Time register support altogether. The spec requires all cycle master capable nodes to implement this (all Linux nodes are cycle master capable) while it also says that it "may" be initialized by the bus manager or by the IRM standing in for a bus manager. (Neither Linux' firewire-core nor ieee1394 nodemgr implement this.) Since we cannot rely on Bus_Time having been initialized by a bus manager, it is better to return an error instead of a nonsensical value on a read request to Bus_Time. Alternatively, we could fix the Bus_Time read integrity bug _and_ implement (a) cycle master's write support of the register as well as (b) bus manager's Bus_Time initialization service, i.e. preservation of the Bus_Time when the cycle master node of a bus changes. However, that would be quite some code for a feature that is unreliable to begin with and very likely unused in practice. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Diffstat (limited to 'arch/mips/include/asm/mmu.h')
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