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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/include/asm/mach-powertv/interrupts.h
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-powertv/interrupts.h')
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h62
1 files changed, 31 insertions, 31 deletions
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
index 4fd652ceb52a..6c463be62156 100644
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -16,7 +16,7 @@
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */ 17 */
18 18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ 19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_ 20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21 21
22/* 22/*
@@ -49,9 +49,9 @@
49 * glue logic inside SPARC ILC 49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below, 50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */ 51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ 52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ 53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */ 54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- 55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside 56 * Ored by glue logic inside
57 * SPARC ILC (see 57 * SPARC ILC (see
@@ -99,9 +99,9 @@
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ 99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */ 100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ 101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */ 102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */ 103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */ 104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ 105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */ 106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
@@ -117,22 +117,22 @@
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ 117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ 118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ 119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */ 120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */ 121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */ 122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */ 123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */ 124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */ 125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */ 126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */ 127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */ 128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */ 129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */ 130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */ 131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */ 132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory 133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */ 134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit 135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */ 136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit 137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */ 138 * Interrupt */
@@ -140,7 +140,7 @@
140 * Interrupt */ 140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive 141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */ 142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive 143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */ 144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error 145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */ 146 * Interrupt */
@@ -166,7 +166,7 @@
166 * Module */ 166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O 167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */ 168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or 169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */ 170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or 171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */ 172 * Discontinuity 2 */
@@ -217,18 +217,18 @@
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ 217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error 218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */ 219 * Interrupt */
220/* 9 unused (bit 09) */ 220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */ 221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error 222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */ 223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error 224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */ 225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From 226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference - 227 * Forward Path Reference -
228 * every 3ms when forward Mbits 228 * every 3ms when forward Mbits
229 * and forward slot control 229 * and forward slot control
230 * bytes are updated. */ 230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from 231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference - 232 * Reverse Path Reference -
233 * delayed from forward mark by 233 * delayed from forward mark by
234 * the ranging delay plus a 234 * the ranging delay plus a
@@ -239,15 +239,15 @@
239 * 1.554 M upstream rates and 239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream 240 * every 6 ms for 256K upstream
241 * rate. */ 241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on 242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */ 243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental) 244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed 245 * Reservation Message Completed
246 * or Slotted aloha verify for 246 * or Slotted aloha verify for
247 * channel 1. */ 247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify 248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation 249 * Interrupt or Reservation
250 * increment completed for 250 * increment completed for
251 * channel 3. */ 251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ 252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ 253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 01:04:07 -0500