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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/mach-pnx8550
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-pnx8550')
-rw-r--r--arch/mips/include/asm/mach-pnx8550/cm.h43
-rw-r--r--arch/mips/include/asm/mach-pnx8550/glb.h86
-rw-r--r--arch/mips/include/asm/mach-pnx8550/int.h140
-rw-r--r--arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h262
-rw-r--r--arch/mips/include/asm/mach-pnx8550/nand.h121
-rw-r--r--arch/mips/include/asm/mach-pnx8550/pci.h185
-rw-r--r--arch/mips/include/asm/mach-pnx8550/uart.h30
-rw-r--r--arch/mips/include/asm/mach-pnx8550/usb.h32
-rw-r--r--arch/mips/include/asm/mach-pnx8550/war.h25
9 files changed, 924 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h
new file mode 100644
index 000000000000..bb0a56c7d011
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/cm.h
@@ -0,0 +1,43 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Clock module specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_CM_H
23#define __PNX8550_CM_H
24
25#define PNX8550_CM_BASE 0xBBE47000
26
27#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
28#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
29#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
30#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
31
32// Table not complete.....
33
34#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
35#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
36#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
37#define PNX8550_CM_PLL_N_MASK 0x01ff0000
38#define PNX8550_CM_PLL_M_MASK 0x00003f00
39#define PNX8550_CM_PLL_P_MASK 0x0000000c
40#define PNX8550_CM_PLL_PD_MASK 0x00000002
41
42
43#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h
new file mode 100644
index 000000000000..07aa85e609bc
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/glb.h
@@ -0,0 +1,86 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PNX8550 global definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_GLB_H
23#define __PNX8550_GLB_H
24
25#define PNX8550_GLB1_BASE 0xBBE63000
26#define PNX8550_GLB2_BASE 0xBBE4d000
27#define PNX8550_RESET_BASE 0xBBE60000
28
29/* PCI Inta Output Enable Registers */
30#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
31
32/* Bit 1:Enable DAC Powerdown
33 0:DACs are enabled and are working normally
34 1:DACs are powerdown
35*/
36#define PNX8550_GLB_DAC_PD 0x2
37/* Bit 0:Enable of PCI inta output
38 0 = Disable PCI inta output
39 1 = Enable PCI inta output
40*/
41#define PNX8550_GLB_ENABLE_INTA_O 0x1
42
43/* PCI Direct Mappings */
44#define PNX8550_PCIMEM 0x12000000
45#define PNX8550_PCIMEM_SIZE 0x08000000
46#define PNX8550_PCIIO 0x1c000000
47#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
48
49#define PNX8550_PORT_BASE KSEG1
50
51// GPIO def
52#define PNX8550_GPIO_BASE 0x1Be00000
53
54#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
55#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
56#define PNX8550_GPIO_MC_31_BIT 30
57#define PNX8550_GPIO_MC_30_BIT 28
58#define PNX8550_GPIO_MC_29_BIT 26
59#define PNX8550_GPIO_MC_28_BIT 24
60#define PNX8550_GPIO_MC_27_BIT 22
61#define PNX8550_GPIO_MC_26_BIT 20
62#define PNX8550_GPIO_MC_25_BIT 18
63#define PNX8550_GPIO_MC_24_BIT 16
64#define PNX8550_GPIO_MC_23_BIT 14
65#define PNX8550_GPIO_MC_22_BIT 12
66#define PNX8550_GPIO_MC_21_BIT 10
67#define PNX8550_GPIO_MC_20_BIT 8
68#define PNX8550_GPIO_MC_19_BIT 6
69#define PNX8550_GPIO_MC_18_BIT 4
70#define PNX8550_GPIO_MC_17_BIT 2
71#define PNX8550_GPIO_MC_16_BIT 0
72
73#define PNX8550_GPIO_MODE_PRIMOP 0x1
74#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
75#define PNX8550_GPIO_MODE_OPENDR 0x3
76
77// RESET module
78#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
79#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
80#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
81
82#define PNX8550_RST_REL_MIPS_RST_N 0x8
83#define PNX8550_RST_DO_SW_RST 0x4
84#define PNX8550_RST_REL_SYS_RST_OUT 0x2
85#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
86#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h
new file mode 100644
index 000000000000..0e0668b524f4
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/int.h
@@ -0,0 +1,140 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Interrupt specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_INT_H
23#define __PNX8550_INT_H
24
25#define PNX8550_GIC_BASE 0xBBE3E000
26
27#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
28#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
29#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
30#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
31#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
32#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
33#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
34#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
35#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
36#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
37
38// cp0 is two software + six hw exceptions
39#define PNX8550_INT_CP0_TOTINT 8
40#define PNX8550_INT_CP0_MIN 0
41#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
42
43#define MIPS_CPU_GIC_IRQ 2
44#define MIPS_CPU_TIMER_IRQ 7
45
46// GIC are 71 exceptions connected to cp0's first hardware exception
47#define PNX8550_INT_GIC_TOTINT 71
48#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
49#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
50
51#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
52#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
53#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
54#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
55#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
56#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
57#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
58#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
59#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
60#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
61
62#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
63#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
64#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
65#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
66#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
67#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
68#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
69#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
70#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
71#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
72
73#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
74#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
75#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
76#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
77#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
78#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
79#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
80#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
81#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
82#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
83
84#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
85#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
86#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
87#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
88#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
89#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
90#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
91#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
92#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
93#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
94
95#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
96#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
97#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
98#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
99#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
100#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
101#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
102#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
103#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
104#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
105
106#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
107#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
108#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
109#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
110#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
111#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
112#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
113#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
114#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
115#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
116
117#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
118#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
119#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
120#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
121#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
122#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
123#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
124#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
125#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
126#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
127
128#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
129
130// Timer are 3 exceptions connected to cp0's 7th hardware exception
131#define PNX8550_INT_TIMER_TOTINT 3
132#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
133#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
134
135#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
136#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
137#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
138#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
139
140#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
new file mode 100644
index 000000000000..bdde00c9199b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
@@ -0,0 +1,262 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 */
8#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
9#define __ASM_MACH_KERNEL_ENTRY_INIT_H
10
11#include <asm/cacheops.h>
12#include <asm/addrspace.h>
13
14#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
15#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
16#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
17#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
18#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
19
20#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
21#define DCACHE_SET_COUNT 128 /* Data cache set count */
22
23#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
24#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
25
26 .macro kernel_entry_setup
27 .set push
28 .set noreorder
29 /*
30 * PNX8550 entry point, when running a non compressed
31 * kernel. When loading a zImage, the head.S code in
32 * arch/mips/zboot/pnx8550 will init the caches and,
33 * decompress the kernel, and branch to kernel_entry.
34 */
35cache_begin: li t0, (1<<28)
36 mtc0 t0, CP0_STATUS /* cp0 usable */
37 HAZARD_CP0
38
39 mtc0 zero, CP0_CAUSE
40 HAZARD_CP0
41
42
43 /* Set static virtual to phys address translation and TLB disabled */
44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0
46
47 and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0
50
51 /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
52
53 init_icache
54 nop
55 init_dcache
56 nop
57
58 cachePr4450ICReset
59 nop
60
61 cachePr4450DCReset
62 nop
63
64 /* read ConfigPR into t0 */
65 mfc0 t0, CP0_CONFIG, 7
66 HAZARD_CP0
67
68 /* enable the TLB */
69 or t0, (1<<19)
70
71 /* disable the ICACHE: at least 10x slower */
72 /* or t0, (1<<26) */
73
74 /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
75 /* or t0, (1<<27) */
76
77 and t0, CO_CONFIGPR_VALID
78
79 /* enable TLB. */
80 mtc0 t0, CP0_CONFIG, 7
81 HAZARD_CP0
82cache_end:
83 /* Setup CMEM_0 to MMIO address space, 2MB */
84 lui t0, 0x1BE0
85 addi t0, t0, 0x3
86 mtc0 $8, $22, 4
87 nop
88
89 /* Setup CMEM_1, 128MB */
90 lui t0, 0x1000
91 addi t0, t0, 0xf
92 mtc0 $8, $22, 5
93 nop
94
95
96 /* Setup CMEM_2, 32MB */
97 lui t0, 0x1C00
98 addi t0, t0, 0xb
99 mtc0 $8, $22, 6
100 nop
101
102 /* Setup CMEM_3, 0MB */
103 lui t0, 0x0
104 addi t0, t0, 0x0
105 mtc0 $8, $22, 7
106 nop
107
108 /* Enable cache */
109 mfc0 t0, CP0_CONFIG
110 HAZARD_CP0
111 and t0, t0, 0xFFFFFFF8
112 or t0, t0, 3
113 mtc0 t0, CP0_CONFIG
114 HAZARD_CP0
115 .set pop
116 .endm
117
118 .macro init_icache
119 .set push
120 .set noreorder
121
122 /* Get Cache Configuration */
123 mfc0 t3, CP0_CONFIG, 1
124 HAZARD_CP0
125
126 /* get cache Line size */
127
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
131 nop
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
135
136 /* get max cache Index */
137 srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
138 andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
139 addiu t0, t2, 6
140 ori t2, zero, 1
141 sllv t2, t2, t0
142
143 /* get max cache way */
144 srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
145 andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
146 addiu t3, t3, 1
147
148 /* total no of cache lines */
149 multu t2, t3 /* max index * max way */
150 mflo t2
151 addiu t2, t2, -1
152
153 move t0, zero
154pr4450_next_instruction_cache_set:
155 cache Index_Invalidate_I, 0(t0)
156 addu t0, t0, t1 /* add bytes in a line */
157 bne t2, zero, pr4450_next_instruction_cache_set
158 addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
159pr4450_instr_cache_invalidated:
160 .set pop
161 .endm
162
163 .macro init_dcache
164 .set push
165 .set noreorder
166 move t1, zero
167
168 /* Store Tag Information */
169 mtc0 zero, CP0_TAGLO, 0
170 HAZARD_CP0
171
172 mtc0 zero, CP0_TAGHI, 0
173 HAZARD_CP0
174
175 /* Cache size is 16384 = 512 lines x 32 bytes per line */
176 or t2, zero, (128*4)-1 /* 512 lines */
177 /* Invalidate all lines */
1782:
179 cache Index_Store_Tag_D, 0(t1)
180 addiu t2, t2, -1
181 bne t2, zero, 2b
182 addiu t1, t1, 32 /* 32 bytes in a line */
183 .set pop
184 .endm
185
186 .macro cachePr4450ICReset
187 .set push
188 .set noreorder
189
190 /* Save CP0 status reg on entry; */
191 /* disable interrupts during cache reset */
192 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
193 HAZARD_CP0
194
195 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
196 HAZARD_CP0
197
198 or t1, zero, zero /* T1 = starting cache index (0) */
199 ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
200
201 icache_invd_loop:
202 /* 9 == register t1 */
203 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
205 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
210 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
211
212 /* Initialize the latches in the instruction cache tag */
213 /* that drive the way selection tri-state bus drivers, by doing a */
214 /* dummy load while the instruction cache is still disabled. */
215 /* TODO: Is this needed ? */
216 la t1, KSEG0 /* T1 = cached memory base address */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
218
219 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
220 HAZARD_CP0
221 .set pop
222 .endm
223
224 .macro cachePr4450DCReset
225 .set push
226 .set noreorder
227 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
228 HAZARD_CP0
229 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
230 HAZARD_CP0
231
232 /* Writeback/invalidate entire data cache sets/ways/lines */
233 or t1, zero, zero /* T1 = starting cache index (0) */
234 ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
235
236 dcache_wbinvd_loop:
237 /* 9 == register t1 */
238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
249 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
250
251 /* Initialize the latches in the data cache tag that drive the way
252 selection tri-state bus drivers, by doing a dummy load while the
253 data cache is still in the disabled mode. TODO: Is this needed ? */
254 la t1, KSEG0 /* T1 = cached memory base address */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
256
257 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
258 HAZARD_CP0
259 .set pop
260 .endm
261
262#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-pnx8550/nand.h b/arch/mips/include/asm/mach-pnx8550/nand.h
new file mode 100644
index 000000000000..aefbc514ab09
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/nand.h
@@ -0,0 +1,121 @@
1#ifndef __PNX8550_NAND_H
2#define __PNX8550_NAND_H
3
4#define PNX8550_NAND_BASE_ADDR 0x10000000
5#define PNX8550_PCIXIO_BASE 0xBBE40000
6
7#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
8#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
9#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
10#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
11#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
12#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
13#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
14#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
15#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
16#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
17#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
18#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
19#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
20#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
21#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
22#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
23
24#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
25#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
26#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
27#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
28#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
29#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
30#define PNX8550_XIO_SEL0_WAIT 0x00000200
31#define PNX8550_XIO_SEL0_OFFSET 0x00000020
32#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
33#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
34#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
35#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
36#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
37#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
38#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
39#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
40#define PNX8550_XIO_SEL0_ENAB 0x00000001
41
42#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
43 (PNX8550_XIO_SEL0_REN_HIGH*0)| \
44 (PNX8550_XIO_SEL0_REN_LOW*2) | \
45 (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
46 (PNX8550_XIO_SEL0_WEN_LOW*2) | \
47 (PNX8550_XIO_SEL0_WAIT*4) | \
48 (PNX8550_XIO_SEL0_OFFSET*0) | \
49 (PNX8550_XIO_SEL0_TYPE_NAND) | \
50 (PNX8550_XIO_SEL0_SIZE_32MB) | \
51 (PNX8550_XIO_SEL0_ENAB))
52
53#define PNX8550_GPXIO_PENDING 0x00000200
54#define PNX8550_GPXIO_DONE 0x00000100
55#define PNX8550_GPXIO_CLR_DONE 0x00000080
56#define PNX8550_GPXIO_INIT 0x00000040
57#define PNX8550_GPXIO_READ_CMD 0x00000010
58#define PNX8550_GPXIO_BEN 0x0000000F
59
60#define PNX8550_XIO_FLASH_64MB 0x00200000
61#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
62#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
63#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
64#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
65#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
66#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
67#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
68#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
69#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
70#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
71#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
72#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
73
74#define PNX8550_XIO_INT_ACK 0x00004000
75#define PNX8550_XIO_INT_COMPL 0x00002000
76#define PNX8550_XIO_INT_NONSUP 0x00000200
77#define PNX8550_XIO_INT_ABORT 0x00000004
78
79#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
80#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
81#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
82#define PNX8550_DMA_CTRL_BURST_8 0x00000000
83#define PNX8550_DMA_CTRL_BURST_16 0x00000020
84#define PNX8550_DMA_CTRL_BURST_32 0x00000040
85#define PNX8550_DMA_CTRL_BURST_64 0x00000060
86#define PNX8550_DMA_CTRL_BURST_128 0x00000080
87#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
88#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
89#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
90#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
91#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
92
93/* see PCI system arch, page 100 for the full list: */
94#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
95#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
96
97#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
98#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
99#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
100#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
101#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
102#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
103#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
104
105#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
106#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
107#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
108#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
109#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
110#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
111#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
112
113#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
114#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
115#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
116#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
117#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
118#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
119#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
120
121#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/pci.h b/arch/mips/include/asm/mach-pnx8550/pci.h
new file mode 100644
index 000000000000..b921508d701b
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/pci.h
@@ -0,0 +1,185 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_PCI_H
23#define __PNX8550_PCI_H
24
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29
30#define PCI_ACCESS_READ 0
31#define PCI_ACCESS_WRITE 1
32
33#define PCI_CMD_IOR 0x20
34#define PCI_CMD_IOW 0x30
35#define PCI_CMD_CONFIG_READ 0xa0
36#define PCI_CMD_CONFIG_WRITE 0xb0
37
38#define PCI_IO_TIMEOUT 1000
39#define PCI_IO_RETRY 5
40/* Timeout for IO and CFG accesses.
41 This is in 1/1024 th of a jiffie(=10ms)
42 i.e. approx 10us */
43#define PCI_IO_JIFFIES_TIMEOUT 40
44#define PCI_IO_JIFFIES_SHIFT 10
45
46#define PCI_BYTE_ENABLE_MASK 0x0000000f
47#define PCI_CFG_BUS_SHIFT 16
48#define PCI_CFG_FUNC_SHIFT 8
49#define PCI_CFG_REG_SHIFT 2
50
51#define PCI_BASE 0x1be00000
52#define PCI_SETUP 0x00040010
53#define PCI_DIS_REQGNT (1<<30)
54#define PCI_DIS_REQGNTA (1<<29)
55#define PCI_DIS_REQGNTB (1<<28)
56#define PCI_D2_SUPPORT (1<<27)
57#define PCI_D1_SUPPORT (1<<26)
58#define PCI_EN_TA (1<<24)
59#define PCI_EN_PCI2MMI (1<<23)
60#define PCI_EN_XIO (1<<22)
61#define PCI_BASE18_PREF (1<<21)
62#define SIZE_16M 0x3
63#define SIZE_32M 0x4
64#define SIZE_64M 0x5
65#define SIZE_128M 0x6
66#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
67#define PCI_SETUP_BASE18_EN (1<<17)
68#define PCI_SETUP_BASE14_PREF (1<<16)
69#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
70#define PCI_SETUP_BASE14_EN (1<<11)
71#define PCI_SETUP_BASE10_PREF (1<<10)
72#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
73#define PCI_SETUP_CFGMANAGE_EN (1<<1)
74#define PCI_SETUP_PCIARB_EN (1<<0)
75
76#define PCI_CTRL 0x040014
77#define PCI_SWPB_DCS_PCI (1<<16)
78#define PCI_SWPB_PCI_PCI (1<<15)
79#define PCI_SWPB_PCI_DCS (1<<14)
80#define PCI_REG_WR_POST (1<<13)
81#define PCI_XIO_WR_POST (1<<12)
82#define PCI_PCI2_WR_POST (1<<13)
83#define PCI_PCI1_WR_POST (1<<12)
84#define PCI_SERR_SEEN (1<<11)
85#define PCI_B10_SPEC_RD (1<<6)
86#define PCI_B14_SPEC_RD (1<<5)
87#define PCI_B18_SPEC_RD (1<<4)
88#define PCI_B10_NOSUBWORD (1<<3)
89#define PCI_B14_NOSUBWORD (1<<2)
90#define PCI_B18_NOSUBWORD (1<<1)
91#define PCI_RETRY_TMREN (1<<0)
92
93#define PCI_BASE1_LO 0x040018
94#define PCI_BASE1_HI 0x04001C
95#define PCI_BASE2_LO 0x040020
96#define PCI_BASE2_HI 0x040024
97#define PCI_RDLIFETIM 0x040028
98#define PCI_GPPM_ADDR 0x04002C
99#define PCI_GPPM_WDAT 0x040030
100#define PCI_GPPM_RDAT 0x040034
101#define PCI_GPPM_CTRL 0x040038
102#define GPPM_DONE (1<<10)
103#define INIT_PCI_CYCLE (1<<9)
104#define GPPM_CMD(X) (((X)&0xf)<<4)
105#define GPPM_BYTEEN(X) ((X)&0xf)
106#define PCI_UNLOCKREG 0x04003C
107#define UNLOCK_SSID(X) (((X)&0xff)<<8)
108#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
109#define UNLOCK_MAGIC 0xCA
110#define PCI_DEV_VEND_ID 0x040040
111#define DEVICE_ID(X) (((X)>>16)&0xffff)
112#define VENDOR_ID(X) (((X)&0xffff))
113#define PCI_CFG_CMDSTAT 0x040044
114#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
115#define PCI_CFG_COMMAND(X) ((X)&0xffff)
116#define PCI_CLASS_REV 0x040048
117#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
118#define PCI_REVID(X) ((X)&0xff)
119#define PCI_LAT_TMR 0x04004c
120#define PCI_BASE10 0x040050
121#define PCI_BASE14 0x040054
122#define PCI_BASE18 0x040058
123#define PCI_SUBSYS_ID 0x04006c
124#define PCI_CAP_PTR 0x040074
125#define PCI_CFG_MISC 0x04007c
126#define PCI_PMC 0x040080
127#define PCI_PWR_STATE 0x040084
128#define PCI_IO 0x040088
129#define PCI_SLVTUNING 0x04008C
130#define PCI_DMATUNING 0x040090
131#define PCI_DMAEADDR 0x040800
132#define PCI_DMAIADDR 0x040804
133#define PCI_DMALEN 0x040808
134#define PCI_DMACTRL 0x04080C
135#define PCI_XIOCTRL 0x040810
136#define PCI_SEL0PROF 0x040814
137#define PCI_SEL1PROF 0x040818
138#define PCI_SEL2PROF 0x04081C
139#define PCI_GPXIOADDR 0x040820
140#define PCI_NANDCTRLS 0x400830
141#define PCI_SEL3PROF 0x040834
142#define PCI_SEL4PROF 0x040838
143#define PCI_GPXIO_STAT 0x040FB0
144#define PCI_GPXIO_IMASK 0x040FB4
145#define PCI_GPXIO_ICLR 0x040FB8
146#define PCI_GPXIO_ISET 0x040FBC
147#define PCI_GPPM_STATUS 0x040FC0
148#define GPPM_DONE (1<<10)
149#define GPPM_ERR (1<<9)
150#define GPPM_MPAR_ERR (1<<8)
151#define GPPM_PAR_ERR (1<<7)
152#define GPPM_R_MABORT (1<<2)
153#define GPPM_R_TABORT (1<<1)
154#define PCI_GPPM_IMASK 0x040FC4
155#define PCI_GPPM_ICLR 0x040FC8
156#define PCI_GPPM_ISET 0x040FCC
157#define PCI_DMA_STATUS 0x040FD0
158#define PCI_DMA_IMASK 0x040FD4
159#define PCI_DMA_ICLR 0x040FD8
160#define PCI_DMA_ISET 0x040FDC
161#define PCI_ISTATUS 0x040FE0
162#define PCI_IMASK 0x040FE4
163#define PCI_ICLR 0x040FE8
164#define PCI_ISET 0x040FEC
165#define PCI_MOD_ID 0x040FFC
166
167/*
168 * PCI configuration cycle AD bus definition
169 */
170/* Type 0 */
171#define PCI_CFG_TYPE0_REG_SHF 0
172#define PCI_CFG_TYPE0_FUNC_SHF 8
173
174/* Type 1 */
175#define PCI_CFG_TYPE1_REG_SHF 0
176#define PCI_CFG_TYPE1_FUNC_SHF 8
177#define PCI_CFG_TYPE1_DEV_SHF 11
178#define PCI_CFG_TYPE1_BUS_SHF 16
179
180/*
181 * Ethernet device DP83816 definition
182 */
183#define DP83816_IRQ_ETHER 66
184
185#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/uart.h b/arch/mips/include/asm/mach-pnx8550/uart.h
new file mode 100644
index 000000000000..ad7608d44874
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/uart.h
@@ -0,0 +1,30 @@
1#ifndef __IP3106_UART_H
2#define __IP3106_UART_H
3
4#include <int.h>
5
6/* early macros for kgdb use. fixme: clean this up */
7
8#define UART_BASE 0xbbe4a000 /* PNX8550 */
9
10#define PNX8550_UART_PORT0 (UART_BASE)
11#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
12
13#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
14#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
15
16/* early macros needed for prom/kgdb */
17
18#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
22#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
23#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
24#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
25#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
26#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
27#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
28#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
29
30#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/usb.h b/arch/mips/include/asm/mach-pnx8550/usb.h
new file mode 100644
index 000000000000..483b7fc65d41
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/usb.h
@@ -0,0 +1,32 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * USB specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_USB_H
23#define __PNX8550_USB_H
24
25/*
26 * USB Host controller
27 */
28
29#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
30#define PNX8550_USB_OHCI_OP_LEN 0x1000
31
32#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
new file mode 100644
index 000000000000..d0458dd082f9
--- /dev/null
+++ b/arch/mips/include/asm/mach-pnx8550/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
9#define __ASM_MIPS_MACH_PNX8550_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 14:37:14 -0500