MIPS: Lantiq: add SoC specific code for XWAY family

Add support for the Lantiq XWAY family of Mips24KEc SoCs.

* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)

The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.

The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function

int lq_gpio_request(unsigned int pin, unsigned int alt0,
        unsigned int alt1, unsigned int dir, const char *name);

which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.

The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 224 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
new file mode 100644
index 000000000000..a1471d2dd0d2
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -0,0 +1,18 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef __LANTIQ_IRQ_H
+#define __LANTIQ_IRQ_H
+
+#include <lantiq_irq.h>
+
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
new file mode 100644
index 000000000000..b4465a888e20
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -0,0 +1,66 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_XWAY_IRQ_H__
+#define _LANTIQ_XWAY_IRQ_H__
+
+#define INT_NUM_IRQ0            8
+#define INT_NUM_IM0_IRL0        (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0        (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0        (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0        (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0        (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET       (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
+#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
+#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
+
+#define LTQ_ASC_ASE_TIR         INT_NUM_IM2_IRL0
+#define LTQ_ASC_ASE_RIR         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_ASC_ASE_EIR         (INT_NUM_IM2_IRL0 + 3)
+
+#define LTQ_SSC_TIR             (INT_NUM_IM0_IRL0 + 15)
+#define LTQ_SSC_RIR             (INT_NUM_IM0_IRL0 + 14)
+#define LTQ_SSC_EIR             (INT_NUM_IM0_IRL0 + 16)
+
+#define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM1_IRL0 + 21)
+#define LTQ_MEI_INT             (INT_NUM_IM1_IRL0 + 23)
+
+#define LTQ_TIMER6_INT          (INT_NUM_IM1_IRL0 + 23)
+#define LTQ_USB_INT             (INT_NUM_IM1_IRL0 + 22)
+#define LTQ_USB_OC_INT          (INT_NUM_IM4_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ              7
+
+#define LTQ_DMA_CH0_INT         (INT_NUM_IM2_IRL0)
+#define LTQ_DMA_CH1_INT         (INT_NUM_IM2_IRL0 + 1)
+#define LTQ_DMA_CH2_INT         (INT_NUM_IM2_IRL0 + 2)
+#define LTQ_DMA_CH3_INT         (INT_NUM_IM2_IRL0 + 3)
+#define LTQ_DMA_CH4_INT         (INT_NUM_IM2_IRL0 + 4)
+#define LTQ_DMA_CH5_INT         (INT_NUM_IM2_IRL0 + 5)
+#define LTQ_DMA_CH6_INT         (INT_NUM_IM2_IRL0 + 6)
+#define LTQ_DMA_CH7_INT         (INT_NUM_IM2_IRL0 + 7)
+#define LTQ_DMA_CH8_INT         (INT_NUM_IM2_IRL0 + 8)
+#define LTQ_DMA_CH9_INT         (INT_NUM_IM2_IRL0 + 9)
+#define LTQ_DMA_CH10_INT        (INT_NUM_IM2_IRL0 + 10)
+#define LTQ_DMA_CH11_INT        (INT_NUM_IM2_IRL0 + 11)
+#define LTQ_DMA_CH12_INT        (INT_NUM_IM2_IRL0 + 25)
+#define LTQ_DMA_CH13_INT        (INT_NUM_IM2_IRL0 + 26)
+#define LTQ_DMA_CH14_INT        (INT_NUM_IM2_IRL0 + 27)
+#define LTQ_DMA_CH15_INT        (INT_NUM_IM2_IRL0 + 28)
+#define LTQ_DMA_CH16_INT        (INT_NUM_IM2_IRL0 + 29)
+#define LTQ_DMA_CH17_INT        (INT_NUM_IM2_IRL0 + 30)
+#define LTQ_DMA_CH18_INT        (INT_NUM_IM2_IRL0 + 16)
+#define LTQ_DMA_CH19_INT        (INT_NUM_IM2_IRL0 + 21)
+
+#define LTQ_PPE_MBOX_INT        (INT_NUM_IM2_IRL0 + 24)
+
+#define INT_NUM_IM4_IRL14       (INT_NUM_IM4_IRL0 + 14)
+
+#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
new file mode 100644
index 000000000000..343e82cbf601
--- /dev/null
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -0,0 +1,140 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LTQ_XWAY_H__
+#define _LTQ_XWAY_H__
+
+#ifdef CONFIG_SOC_TYPE_XWAY
+
+#include <lantiq.h>
+
+/* Chip IDs */
+#define SOC_ID_DANUBE1          0x129
+#define SOC_ID_DANUBE2          0x12B
+#define SOC_ID_TWINPASS         0x12D
+#define SOC_ID_AMAZON_SE        0x152
+#define SOC_ID_ARX188           0x16C
+#define SOC_ID_ARX168           0x16D
+#define SOC_ID_ARX182           0x16F
+
+/* SoC Types */
+#define SOC_TYPE_DANUBE         0x01
+#define SOC_TYPE_TWINPASS       0x02
+#define SOC_TYPE_AR9            0x03
+#define SOC_TYPE_VR9            0x04
+#define SOC_TYPE_AMAZON_SE      0x05
+
+/* ASC0/1 - serial port */
+#define LTQ_ASC0_BASE_ADDR      0x1E100400
+#define LTQ_ASC1_BASE_ADDR      0x1E100C00
+#define LTQ_ASC_SIZE            0x400
+
+/* RCU - reset control unit */
+#define LTQ_RCU_BASE_ADDR       0x1F203000
+#define LTQ_RCU_SIZE            0x1000
+
+/* GPTU - general purpose timer unit */
+#define LTQ_GPTU_BASE_ADDR      0x18000300
+#define LTQ_GPTU_SIZE           0x100
+
+/* EBU - external bus unit */
+#define LTQ_EBU_GPIO_START      0x14000000
+#define LTQ_EBU_GPIO_SIZE       0x1000
+
+#define LTQ_EBU_BASE_ADDR       0x1E105300
+#define LTQ_EBU_SIZE            0x100
+
+#define LTQ_EBU_BUSCON0         0x0060
+#define LTQ_EBU_PCC_CON         0x0090
+#define LTQ_EBU_PCC_IEN         0x00A4
+#define LTQ_EBU_PCC_ISTAT       0x00A0
+#define LTQ_EBU_BUSCON1         0x0064
+#define LTQ_EBU_ADDRSEL1        0x0024
+#define EBU_WRDIS               0x80000000
+
+/* CGU - clock generation unit */
+#define LTQ_CGU_BASE_ADDR       0x1F103000
+#define LTQ_CGU_SIZE            0x1000
+
+/* ICU - interrupt control unit */
+#define LTQ_ICU_BASE_ADDR       0x1F880200
+#define LTQ_ICU_SIZE            0x100
+
+/* EIU - external interrupt unit */
+#define LTQ_EIU_BASE_ADDR       0x1F101000
+#define LTQ_EIU_SIZE            0x1000
+
+/* PMU - power management unit */
+#define LTQ_PMU_BASE_ADDR       0x1F102000
+#define LTQ_PMU_SIZE            0x1000
+
+#define PMU_DMA                 0x0020
+#define PMU_USB                 0x8041
+#define PMU_LED                 0x0800
+#define PMU_GPT                 0x1000
+#define PMU_PPE                 0x2000
+#define PMU_FPI                 0x4000
+#define PMU_SWITCH              0x10000000
+
+/* ETOP - ethernet */
+#define LTQ_PPE32_BASE_ADDR     0xBE180000
+#define LTQ_PPE32_SIZE          0x40000
+
+/* DMA */
+#define LTQ_DMA_BASE_ADDR       0xBE104100
+
+/* PCI */
+#define PCI_CR_BASE_ADDR        0x1E105400
+#define PCI_CR_SIZE             0x400
+
+/* WDT */
+#define LTQ_WDT_BASE_ADDR       0x1F8803F0
+#define LTQ_WDT_SIZE            0x10
+
+/* STP - serial to parallel conversion unit */
+#define LTQ_STP_BASE_ADDR       0x1E100BB0
+#define LTQ_STP_SIZE            0x40
+
+/* GPIO */
+#define LTQ_GPIO0_BASE_ADDR     0x1E100B10
+#define LTQ_GPIO1_BASE_ADDR     0x1E100B40
+#define LTQ_GPIO2_BASE_ADDR     0x1E100B70
+#define LTQ_GPIO_SIZE           0x30
+
+/* SSC */
+#define LTQ_SSC_BASE_ADDR       0x1e100800
+#define LTQ_SSC_SIZE            0x100
+
+/* MEI - dsl core */
+#define LTQ_MEI_BASE_ADDR       0x1E116000
+
+/* DEU - data encryption unit */
+#define LTQ_DEU_BASE_ADDR       0x1E103100
+
+/* MPS - multi processor unit (voice) */
+#define LTQ_MPS_BASE_ADDR       (KSEG1 + 0x1F107000)
+#define LTQ_MPS_CHIPID          ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
+
+/* request a non-gpio and set the PIO config */
+extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
+        unsigned int alt1, unsigned int dir, const char *name);
+extern void ltq_pmu_enable(unsigned int module);
+extern void ltq_pmu_disable(unsigned int module);
+
+static inline int ltq_is_ar9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_AR9);
+}
+
+static inline int ltq_is_vr9(void)
+{
+        return (ltq_get_soc_type() == SOC_TYPE_VR9);
+}
+
+#endif /* CONFIG_SOC_TYPE_XWAY */
+#endif /* _LTQ_XWAY_H__ */