MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip

Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 102 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
new file mode 100644
index 000000000000..f37318605452
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/base.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_MACH_JZ4740_BASE_H__
+#define __ASM_MACH_JZ4740_BASE_H__
+
+#define JZ4740_CPM_BASE_ADDR    0x10000000
+#define JZ4740_INTC_BASE_ADDR   0x10001000
+#define JZ4740_WDT_BASE_ADDR    0x10002000
+#define JZ4740_TCU_BASE_ADDR    0x10002010
+#define JZ4740_RTC_BASE_ADDR    0x10003000
+#define JZ4740_GPIO_BASE_ADDR   0x10010000
+#define JZ4740_AIC_BASE_ADDR    0x10020000
+#define JZ4740_MSC_BASE_ADDR    0x10021000
+#define JZ4740_UART0_BASE_ADDR  0x10030000
+#define JZ4740_UART1_BASE_ADDR  0x10031000
+#define JZ4740_I2C_BASE_ADDR    0x10042000
+#define JZ4740_SSI_BASE_ADDR    0x10043000
+#define JZ4740_SADC_BASE_ADDR   0x10070000
+#define JZ4740_EMC_BASE_ADDR    0x13010000
+#define JZ4740_DMAC_BASE_ADDR   0x13020000
+#define JZ4740_UHC_BASE_ADDR    0x13030000
+#define JZ4740_UDC_BASE_ADDR    0x13040000
+#define JZ4740_LCD_BASE_ADDR    0x13050000
+#define JZ4740_SLCD_BASE_ADDR   0x13050000
+#define JZ4740_CIM_BASE_ADDR    0x13060000
+#define JZ4740_IPU_BASE_ADDR    0x13080000
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d12e5c6477b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr   0
+#define cpu_has_counter         0
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc            1
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define kernel_uses_llsc        1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644
index 000000000000..3a5bc17e28fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
+#define __ASM_MIPS_MACH_JZ4740_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */