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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /arch/mips/include/asm/mach-ip27
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ip27')
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h54
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h50
-rw-r--r--arch/mips/include/asm/mach-ip27/irq.h22
-rw-r--r--arch/mips/include/asm/mach-ip27/kernel-entry-init.h59
-rw-r--r--arch/mips/include/asm/mach-ip27/kmalloc.h8
-rw-r--r--arch/mips/include/asm/mach-ip27/mangle-port.h25
-rw-r--r--arch/mips/include/asm/mach-ip27/mmzone.h36
-rw-r--r--arch/mips/include/asm/mach-ip27/spaces.h30
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h59
-rw-r--r--arch/mips/include/asm/mach-ip27/war.h25
10 files changed, 368 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
new file mode 100644
index 000000000000..7d3112b148d9
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -0,0 +1,54 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 07 Ralf Baechle
7 */
8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * IP27 only comes with R10000 family processors all using the same config
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_icache_snoops_remote_store 1
30#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0
32
33#define cpu_has_nofpuex 0
34#define cpu_has_64bits 1
35
36#define cpu_has_4kex 1
37#define cpu_has_3k_cache 0
38#define cpu_has_6k_cache 0
39#define cpu_has_4k_cache 1
40#define cpu_has_8k_cache 0
41#define cpu_has_tx39_cache 0
42
43#define cpu_has_inclusive_pcaches 1
44
45#define cpu_dcache_line_size() 32
46#define cpu_icache_line_size() 64
47#define cpu_scache_line_size() 128
48
49#define cpu_has_mips32r1 0
50#define cpu_has_mips32r2 0
51#define cpu_has_mips64r1 0
52#define cpu_has_mips64r2 0
53
54#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
new file mode 100644
index 000000000000..ed7e6222dc15
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -0,0 +1,50 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 */
9#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
10#define __ASM_MACH_IP27_DMA_COHERENCE_H
11
12#include <asm/pci/bridge.h>
13
14#define pdev_to_baddr(pdev, addr) \
15 (BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
16#define dev_to_baddr(dev, addr) \
17 pdev_to_baddr(to_pci_dev(dev), (addr))
18
19struct device;
20
21static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
22 size_t size)
23{
24 dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr));
25
26 return pa;
27}
28
29static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
30{
31 dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
32
33 return pa;
34}
35
36static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
37{
38 return dma_addr & ~(0xffUL << 56);
39}
40
41static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
42{
43}
44
45static inline int plat_device_is_coherent(struct device *dev)
46{
47 return 1; /* IP27 non-cohernet mode is unsupported */
48}
49
50#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h
new file mode 100644
index 000000000000..cf4384bfa846
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/irq.h
@@ -0,0 +1,22 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 Kanoj Sarcar
9 */
10#ifndef __ASM_MACH_IP27_IRQ_H
11#define __ASM_MACH_IP27_IRQ_H
12
13/*
14 * A hardwired interrupt number is completly stupid for this system - a
15 * large configuration might have thousands if not tenthousands of
16 * interrupts.
17 */
18#define NR_IRQS 256
19
20#include_next <irq.h>
21
22#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
new file mode 100644
index 000000000000..624d66c7f290
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Silicon Graphics, Inc.
7 * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
10#define __ASM_MACH_IP27_KERNEL_ENTRY_H
11
12#include <asm/sn/addrs.h>
13#include <asm/sn/sn0/hubni.h>
14#include <asm/sn/klkernvars.h>
15
16/*
17 * Returns the local nasid into res.
18 */
19 .macro GET_NASID_ASM res
20 dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
21 ld \res, (\res)
22 and \res, NSRI_NODEID_MASK
23 dsrl \res, NSRI_NODEID_SHFT
24 .endm
25
26/*
27 * Intentionally empty macro, used in head.S. Override in
28 * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
29 */
30 .macro kernel_entry_setup
31 GET_NASID_ASM t1
32 move t2, t1 # text and data are here
33 MAPPED_KERNEL_SETUP_TLB
34 .endm
35
36/*
37 * Do SMP slave processor setup necessary before we can savely execute C code.
38 */
39 .macro smp_slave_setup
40 GET_NASID_ASM t1
41 dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
42 KLDIR_OFF_POINTER + CAC_BASE
43 dsll t1, NASID_SHFT
44 or t0, t0, t1
45 ld t0, 0(t0) # t0 points to kern_vars struct
46 lh t1, KV_RO_NASID_OFFSET(t0)
47 lh t2, KV_RW_NASID_OFFSET(t0)
48 MAPPED_KERNEL_SETUP_TLB
49
50 /*
51 * We might not get launched at the address the kernel is linked to,
52 * so we jump there.
53 */
54 PTR_LA t0, 0f
55 jr t0
560:
57 .endm
58
59#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-ip27/kmalloc.h b/arch/mips/include/asm/mach-ip27/kmalloc.h
new file mode 100644
index 000000000000..426bd049b2d7
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/kmalloc.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_MACH_IP27_KMALLOC_H
2#define __ASM_MACH_IP27_KMALLOC_H
3
4/*
5 * All happy, no need to define ARCH_KMALLOC_MINALIGN
6 */
7
8#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/arch/mips/include/asm/mach-ip27/mangle-port.h b/arch/mips/include/asm/mach-ip27/mangle-port.h
new file mode 100644
index 000000000000..f6e4912ea062
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mangle-port.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 */
8#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
9#define __ASM_MACH_IP27_MANGLE_PORT_H
10
11#define __swizzle_addr_b(port) (port)
12#define __swizzle_addr_w(port) ((port) ^ 2)
13#define __swizzle_addr_l(port) (port)
14#define __swizzle_addr_q(port) (port)
15
16# define ioswabb(a, x) (x)
17# define __mem_ioswabb(a, x) (x)
18# define ioswabw(a, x) (x)
19# define __mem_ioswabw(a, x) cpu_to_le16(x)
20# define ioswabl(a, x) (x)
21# define __mem_ioswabl(a, x) cpu_to_le32(x)
22# define ioswabq(a, x) (x)
23# define __mem_ioswabq(a, x) cpu_to_le32(x)
24
25#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
new file mode 100644
index 000000000000..986a3b9b59a7
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_MACH_MMZONE_H
2#define _ASM_MACH_MMZONE_H
3
4#include <asm/sn/addrs.h>
5#include <asm/sn/arch.h>
6#include <asm/sn/hub.h>
7
8#define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr))
9
10#define LEVELS_PER_SLICE 128
11
12struct slice_data {
13 unsigned long irq_enable_mask[2];
14 int level_to_irq[LEVELS_PER_SLICE];
15};
16
17struct hub_data {
18 kern_vars_t kern_vars;
19 DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
20 cpumask_t h_cpus;
21 unsigned long slice_map;
22 unsigned long irq_alloc_mask[2];
23 struct slice_data slice[2];
24};
25
26struct node_data {
27 struct pglist_data pglist;
28 struct hub_data hub;
29};
30
31extern struct node_data *__node_data[];
32
33#define NODE_DATA(n) (&__node_data[(n)]->pglist)
34#define hub_data(n) (&__node_data[(n)]->hub)
35
36#endif /* _ASM_MACH_MMZONE_H */
diff --git a/arch/mips/include/asm/mach-ip27/spaces.h b/arch/mips/include/asm/mach-ip27/spaces.h
new file mode 100644
index 000000000000..b18802a0b17e
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/spaces.h
@@ -0,0 +1,30 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 99 Ralf Baechle
7 * Copyright (C) 2000, 2002 Maciej W. Rozycki
8 * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
9 */
10#ifndef _ASM_MACH_IP27_SPACES_H
11#define _ASM_MACH_IP27_SPACES_H
12
13/*
14 * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects
15 * uncached memory addressing.
16 */
17
18#define HSPEC_BASE 0x9000000000000000
19#define IO_BASE 0x9200000000000000
20#define MSPEC_BASE 0x9400000000000000
21#define UNCAC_BASE 0x9600000000000000
22
23#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
24#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK))
25
26#define HIGHMEM_START (~0UL)
27
28#include <asm/mach-generic/spaces.h>
29
30#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
new file mode 100644
index 000000000000..7785bec732f2
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -0,0 +1,59 @@
1#ifndef _ASM_MACH_TOPOLOGY_H
2#define _ASM_MACH_TOPOLOGY_H 1
3
4#include <asm/sn/hub.h>
5#include <asm/sn/types.h>
6#include <asm/mmzone.h>
7
8struct cpuinfo_ip27 {
9// cpuid_t p_cpuid; /* PROM assigned cpuid */
10 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
11 nasid_t p_nasid; /* my node ID in numa-as-id-space */
12 unsigned char p_slice; /* Physical position on node board */
13#if 0
14 unsigned long loops_per_sec;
15 unsigned long ipi_count;
16 unsigned long irq_attempt[NR_IRQS];
17 unsigned long smp_local_irq_count;
18 unsigned long prof_multiplier;
19 unsigned long prof_counter;
20#endif
21};
22
23extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
24
25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
26#define parent_node(node) (node)
27#define node_to_cpumask(node) (hub_data(node)->h_cpus)
28#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
29struct pci_bus;
30extern int pcibus_to_node(struct pci_bus *);
31
32#define pcibus_to_cpumask(bus) (cpu_online_map)
33
34extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
35
36#define node_distance(from, to) (__node_distances[(from)][(to)])
37
38/* sched_domains SD_NODE_INIT for SGI IP27 machines */
39#define SD_NODE_INIT (struct sched_domain) { \
40 .span = CPU_MASK_NONE, \
41 .parent = NULL, \
42 .child = NULL, \
43 .groups = NULL, \
44 .min_interval = 8, \
45 .max_interval = 32, \
46 .busy_factor = 32, \
47 .imbalance_pct = 125, \
48 .cache_nice_tries = 1, \
49 .flags = SD_LOAD_BALANCE \
50 | SD_BALANCE_EXEC \
51 | SD_WAKE_BALANCE, \
52 .last_balance = jiffies, \
53 .balance_interval = 1, \
54 .nr_balance_failed = 0, \
55}
56
57#include <asm-generic/topology.h>
58
59#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
new file mode 100644
index 000000000000..e2ddcc9b1fff
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_IP27_WAR_H
9#define __ASM_MIPS_MACH_IP27_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 1
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 02:11:24 -0500