MIPS: Alchemy: Merge PB1200 support into DB1200 code.

The PB1200 is basically a DB1200 with additional MMC and camera sockets
and different base addresses for external hardware (CPLD, IDE, Net, NAND).

This patch implements the missing PB1200 features in DB1200 support code
and runtime board detection.

Tested on DB1200 only.

Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2880/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 9 insertions, 2 deletions

diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
 #define BCSR_INT_PC1EJECT       0x0800
 #define BCSR_INT_SD0INSERT      0x1000
 #define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
 
-#define IDE_PHYS_ADDR           0x18800000
 #define IDE_REG_SHIFT           5
 
-#define DB1200_IDE_PHYS_ADDR    IDE_PHYS_ADDR
+#define DB1200_IDE_PHYS_ADDR    0x18800000
 #define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
 #define DB1200_ETH_PHYS_ADDR    0x19000300
 #define DB1200_NAND_PHYS_ADDR   0x20000000
 
+#define PB1200_IDE_PHYS_ADDR    0x0C800000
+#define PB1200_ETH_PHYS_ADDR    0x0D000300
+#define PB1200_NAND_PHYS_ADDR   0x1C000000
+
 /*
  * External Interrupts for DBAu1200 as of 8/6/2004.
  * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
         DB1200_PC1_EJECT_INT,
         DB1200_SD0_INSERT_INT,
         DB1200_SD0_EJECT_INT,
+        PB1200_SD1_INSERT_INT,
+        PB1200_SD1_EJECT_INT,
 
         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 };